IXDD404 4 Amp Dual Low-Side Ultrafast MOSFET Driver Features General Description • Built using the advantages and compatibility of CMOS and IXYS HDMOSTM processes • Latch-Up Protected up to 0.5A • High Peak Output Current: 4A Peak • Wide Operating Range: 4.5V to 35V • Ability to Disable Output under Faults • High Capacitive Load Drive Capability: 1800pF in <15ns • Matched Rise And Fall Times • Low Propagation Delay Time • Low Output Impedance • Low Supply Current • Two identical drivers in single chip The IXDD404 is comprised of two 4 Amp CMOS high speed MOSFET drivers. Each output can source and sink 4 A of peak current while producing voltage rise and fall times of less than 15ns to drive the latest IXYS MOSFETS & IGBT's. The input of the driver is compatible with TTL or CMOS and is fully immune to latch up over the entire operating range. Designed with small internal delays, cross conduction/current shootthrough is virtually eliminated in the IXDD404. Improved speed and drive capabilities are further enhanced by very low, matched rise and fall times. Additionally, each driver in the IXDD404 incorporates a unique ability to disable the output under fault conditions. When a logical low is forced into the Enable input of a driver, both of it's final output stage MOSFETs (NMOS and PMOS) are turned off. As a result, the respective output of the IXDD404 enters a tristate mode and achieves a Soft Turn-Off of the MOSFET/ IGBT when a short circuit is detected. This helps prevent damage that could occur to the MOSFET/IGBT if it were to be switched off abruptly due to a dv/dt over-voltage transient. Applications • • • • • • • • • • Driving MOSFETs and IGBTs Limiting di/dt under Short Circuit Motor Controls Line Drivers Pulse Generators Local Power ON/OFF Switch Switch Mode Power Supplies (SMPS) DC to DC Converters Pulse Transformer Driver Class D Switching Amplifiers The IXDD404 is available in the standard 8 pin P-DIP (PI), SOIC-8 (SIA) and SOIC-16 (SIA-16) packages. For enhanced thermal performance, the SOIC-8 and SOIC-16 are also available with an exposed grounded metal back package as the SI and SI-16 respectively. Ordering Information Part Number Package Type Temp. Range IXDD404PI 8-Pin PDIP IXDD404SI 8-Pin SOIC with Grounded Metal Back -55°C to IXDD404SIA 8-Pin SOIC +125°C IXDD404SI-16 16-Pin SOIC with Grounded Metal Back IXDD404SIA-16 16-Pin SOIC NOTE: Mounting or solder tabs on all packages are connected to ground Configuration Dual Non Inverting With Enable Figure 1 - Functional Diagram Vcc 200k OUTA 200k OUTB ENA INB ENB GND DS99046B(08/04) Copyright © IXYS CORPORATION 2004 First Release IXDD404 Absolute Maximum Ratings (Note 1) Parameter Supply Voltage All Other Pins Junction Temperature Storage Temperature Lead Temperature (10 sec) Operating Ratings Param eter Operating Tem perature Range Value -55 o C to 125 o C Therm al Im pedance (Junction to Am bient) 8 Pin PDIP (PI) (θ JA ) 120 o C/W 8 Pin SOIC (SIA) (θ JA ) 110 o C/W 8 Pin SOIC (SI) (θ JA ) with heat sink** 71 o C/W 2 Heat sink area of 1cm 16 Pin SOIC (SIA-16) (θ JA ) 110 o C/W Value 40 V -0.3 V to VCC + 0.3 V 150 oC -65 oC to 150 oC 300 oC **Heat sink area is 1 oz. copper on one side of .06" thick FR4 soldered to metal back plane. Electrical Characteristics Unless otherwise noted, TA = 25 oC, 4.5V ≤ VCC ≤ 35V . All voltage measurements with respect to GND. IXDD404 configured as described in Test Conditions. All specifications are for one channel. Symbol Parameter Test Conditions Min VIH High input voltage 4.5V ≤ VIN ≤ 18V 2.5 VIL Low input voltage 4.5V ≤ VIN ≤ 18V VIN Input voltage range IIN Input current VOH High output voltage VOL Low output voltage ROH Output resistance @ Output high Output resistance @ Output Low Peak output current ROL IPEAK IDC 0V ≤ VIN ≤ VCC V 0.8 V V -10 10 µA VCC - 0.025 V 0.025 V VCC = 18V 2 2.5 Ω VCC = 18V 1.5 2 Ω VCC = 18V 4 - 0.3 VENH High En Input Voltage 2/3 Vcc VENL Low En Input Voltage tR Rise time CL=1800pF Vcc=18V tF Fall time tONDLY VCC On-time propagation delay Off-time propagation delay Enable to output high delay time Disable to output low Disable delay time Power supply voltage ICC Power supply current REN Enable Pull-up Resistor tDOLD Units VCC + 0.3 VEN tENOH Max -5 Continuous output current Enable voltage range tOFFDLY Typ A 1 A Vcc + 0.3 V V 1/3 Vcc V 16 18 ns CL=1800pF Vcc=18V 13 17 ns CL=1800pF Vcc=18V 36 40 ns CL=1800pF Vcc=18V 35 39 ns 30 ns 30 ns 18 35 V 1 0 3 10 10 mA µA µA kΩ 4.5 VIN = 3.5V VIN = 0V VIN = + VCC 200 Specifications to change without notice Note 1: Operating the device beyond parameters with listed “absolute maximum ratings” may cause permanent damage to the device. Typical values indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. The guaranteed specifications apply only for the test conditions listed. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 2 IXDD404 Electrical Characteristics Unless otherwise noted, temperature over -55 oC to 150 oC, 4.5V ≤ VCC ≤ 35V . All voltage measurements with respect to GND. IXDD404 configured as described in Test Conditions. All specifications are for one channel. Symbol Parameter VIH High input voltage VIL Low input voltage VIN Input voltage range IIN Input current VOH High output voltage VOL Low output voltage ROH Output resistance @ Output high Output resistance @ Output Low Peak output current ROL IPEAK IDC tR Continuous output current Rise time tF tONDLY Test Conditions Min Typ Max 2 0V ≤ VIN ≤ VCC Units V 2.4 V -5 VCC + 0.3 V -10 10 µA VCC - 0.025 V 0.025 V VCC = 18V 3.4 Ω VCC = 18V 2 Ω VCC = 18V 3.2 A 1 A CL=1000pF Vcc=18V 11 ns Fall time CL=1000pF Vcc=18V 13 ns CL=1000pF Vcc=18V 60 ns CL=1000pF Vcc=18V 59 ns VCC On-time propagation delay Off-time propagation delay Power supply voltage 18 35 V ICC Power supply current 1 0 3 10 10 mA µA µA tOFFDLY 4.5 VIN = 3.5V VIN = 0V VIN = + VCC Specifications to change without notice 3 IXDD404 Pin Configurations 1 EN A SO8 (SI) 8 PIN DIP (PI) 2 IN A 3 GND 4 IN B I X D D 4 0 4 EN B 8 OUT A 7 SO16 (SI-16) VCC 6 OUT B 5 Pin Description SYMBOL FUNCTION EN A A Channel Enable IN A A Channel Input GND Ground IN B B Channel Input OUT B B Channel Output VCC Supply Voltage OUT A A Channel Output EN B B Channel Enable DESCRIPTION The Channel A enable pin. This pin, when driven low, disables the A Channel, forcing a high impedance state to the A Channel Output. A Channel Input signal-TTL or CMOS compatible. The system ground pin. Internally connected to all circuitry, this pin provides ground reference for the entire chip. This pin should be connected to a low noise analog ground plane for optimum performance. B Channel Input signal-TTL or CMOS compatible. B Channel Driver output. For application purposes, this pin is connected, through a resistor, to Gate of a MOSFET/IGBT. Positive power-supply voltage input. This pin provides power to the entire chip. The range for this voltage is from 4.5V to 35V. A Channel Driver output. For application purposes, this pin is connected, through a resistor, to Gate of a MOSFET/IGBT. The Channel B enable pin. This pin, when driven low, disables the B Channel, forcing a high impedance state to the B Channel Output. CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD procedures when handling and assembling this component. Figure 2 - Characteristics Test Diagram VIN 4 IXDD404 Typical Performance Characteristics Fig. 3 Fig. 4 Rise Times vs. Supply Voltage 80 70 70 60 60 Fall Times (ns) Rise Time (ns) 80 50 40 10000pF 30 6800p F 20 50 40 10000pF 30 6800pF 20 4700pF 1800pF 1000pF 10 Fall Times vs. Supply Voltage 4700pF 1800pF 1000pF 200pF 10 200pF 0 0 5 10 15 20 25 30 35 5 10 15 Fig. 5 70 60 30 35 8V 8V 70 10V 60 12V 50 18V 40 25V 35V 30 10V 50 12V 40 18V 25V 35V 30 20 20 10 10 0 0 0 2000 4000 6000 8000 10000 0 2000 Fig. 7 14 4000 6000 8000 10000 Load Capacitance (pF) Load Capacitance (pF) Rise And Fall Times vs. Temperature C L = 1000pF, V cc = 18V Fig. 8 2.5 M ax / M in Input vs. Tem perature C L = 1000pF, V cc = 18V 2.4 12 tR Max / Min Input Voltage 2.3 10 tF Time (ns) 25 Fall Times vs. Load Capacitance 80 Fall Time (ns) Rise Time (ns) Fig. 6 Rise Times vs. Load Capacitance 80 20 Supply Voltage (V) Supply Voltage (V) 8 6 4 2.2 M in Input H ig h 2.1 2 Max Inpu t Low 1.9 1.8 1.7 2 1.6 0 1.5 -60 -10 40 90 140 190 -60 Temperature (C) -10 40 90 Tem perature (C ) 5 140 190 IXDD404 Fig. 9 Supply Current vs. Load Capacitance Vcc = 8V 100 Supply Current vs. Frequency Vcc = 8V Fig. 10 1000 2 MHz 10000 pF 6800 pF 4700 pF 1800 pF 1000 pF 200 pF 90 100 Supply Current (ma) Supply Current (mA) 80 1 MHz 70 60 50 40 500 kHz 30 20 1 0.1 10 0 100 10 100 kHz 50 kHz 10 kHz 1000 0.01 10000 1 10 Load Capacitance (pF) Fig. 11 Supply Current vs. Load Capacitance Vcc = 12V 1 Mhz 10000 pF 6800 pF 4700 pF 1800 pF 1000 pF 200 pF 100 Supply Current (ma) Supply Current (mA) Supply Current vs. Frequency Vcc = 12V Fig. 12 80 70 60 500 kHz 50 40 30 20 10 1 0.1 100 kHz 50 kHz 10 kHz 10 1000 0.01 10000 1 10 Load Capacitance (pF) Supply Current vs. Load Capacitance Vcc = 18V 1 MHz Supply Current (ma) Supply Current (mA) 70 60 50 40 30 20 100 kHz 10 50 kHz 100 10 1 0.1 10 kHz 1000 10000 10000 pF 6800 pF 4700 pF 1800 pF 1000 pF 200 pF 500 kHz 80 0 100 1000 Supply Current vs. Frequency Vcc = 18V Fig. 14 1000 2 MHz 100 Frequency (kHz) 100 90 10000 1000 2 MHz 90 Fig. 13 1000 Frequency (kHz) 100 0 100 100 0.01 1 10000 10 100 Frequency (kHz) Load Capacitance (pF) 6 1000 10000 IXDD404 Supply Current vs. Load Capacitance Vcc = 35V Fig. 15 Supply Current vs. Frequency Vcc = 35V Fig. 16 100 1000 10000 pF 6800 pF 4700 pF 90 1800 pF 100 Supply Current (mA) Supply Current (mA) 80 2 MHz 70 1 MHz 60 500 kHz 50 40 100 kHz 30 20 1000 pF 200 pF 10 1 0.1 50 kHz 10 10 kHz 0 100 1000 0.01 10000 1 10 Propagation Delay vs. Supply Voltage CL = 1800pF Vin = 5V@1kHz Fig. 17 70 10000 50 45 Propagation Delay (ns) Propagation Delay (ns) 1000 Propagation Delay vs. Input Voltage C L = 1800pF V cc = 15V Fig. 18 60 tONDLY 100 Frequency (kHz) Load Capacitance (pF) 50 tONDLY 40 tOFFDLY 30 20 tONDLY 40 tOFFDLY 35 30 25 10 20 0 5 10 15 20 25 30 2 35 4 6 8 10 12 Input Voltage (V) Supply Voltage (V) Fig. 20 Propagation Delay Times vs. Temperature C L = 1000pF, V cc = 18V Fig. 19 0.3 Quiescent Vcc Input Current(mA) 60 55 Time (ns) 50 45 t OND LY 40 Quiescent Supply Current vs. Temperature Vcc = 18V, Vin = 5V@1kHz, CL = 1000pF t OFFDLY 35 30 25 0.25 0.2 0.15 0.1 0.05 0 20 -60 -10 40 90 140 -60 190 -10 40 90 Temperature (C) Temperature (C) 7 140 190 IXDD404 Fig. 21 High State Ouput Resistance vs. Supply Voltage Fig. 22 Low State Output Resistance vs. Supply Voltage 6 Low State Output Resistance (Ohms) High State Output Resistance (Ohms) 6 5 4 3 2 1 5 4 3 2 1 0 0 5 10 15 20 25 30 5 35 10 Supply Voltage (V) Vcc vs. P Channel Output Current Fig. 24 14 -2 12 -4 -6 -8 -10 -12 5 10 15 20 25 30 35 8 6 4 2 5 10 15 20 25 30 35 Vcc (V) Fig. 26 6 N Channel Output Current (A) P Channel Output Current (A) 30 0 35 P Channel Output Current vs. Temperature Vcc = 18V, CL = 1000pF 6 25 10 Vcc (V) Fig. 25 20 Vcc vs. N Channel Ouput Current 0 N Channel Output Current (A) P Channel Output Current (A) Fig. 23 15 Supply Voltage (V) 5 4 3 2 1 N Channel Output Current vs. Temperature V cc = 18V C L = 1000pF 5 4 3 2 1 0 0 -80 -30 20 70 120 -80 170 -30 20 70 Temperature (C) Temperature (C) 8 120 170 IXDD404 Fig. 27 Enable Threshold vs. Supply Voltage 20 18 Enable Threshold (V) 16 14 12 10 8 6 4 2 0 0 5 10 15 20 25 30 35 40 Supply Voltage (V) Figure 28 - Typical Application Short Circuit di/dt Limit 9 IXDD404 APPLICATIONS INFORMATION Short Circuit di/dt Limit A short circuit in a high-power MOSFET such as the IXFN100N20, (20A, 1000V), as shown in Figure 26, can cause the current through the module to flow in excess of 60A for 10µs or more prior to self-destruction due to thermal runaway. For this reason, some protection circuitry is needed to turn off the MOSFET module. However, if the module is switched off too fast, there is a danger of voltage transients occuring on the drain due to Ldi/dt, (where L represents total inductance in series with drain). If these voltage transients exceed the MOSFET's voltage rating, this can cause an avalanche breakdown. caused by the inductance of the wire connecting the source resistor to ground. (Those glitches might cause false triggering of the comparator). The comparator's output should be connected to a SRFF(Set Reset Flip Flop). The flip-flop controls both the Enable signal, and the low power MOSFET gate. Please note that CMOS 4000series devices operate with a VCC range from 3 to 15 VDC, (with 18 VDC being the maximum allowable limit). A low power MOSFET, such as the 2N7000, in series with a resistor, will enable the IXFN100N20 gate voltage to drop gradually. The resistor should be chosen so that the RC time constant will be 100us, where "C" is the Miller capacitance of the IXFN100N20. The IXDD404 has the unique capability to softly switch off the high-power MOSFET module, significantly reducing these Ldi/dt transients. Thus, the IXDD404 helps to prevent device destruction from both dangers; over-current, and avalanche breakdown due to di/dt induced over-voltage transients. For resuming normal operation, a Reset signal is needed at the SRFF's input to enable the IXDD404 again. This Reset can be generated by connecting a One Shot circuit between the IXDD408 Input signal and the SRFF restart input. The One Shot will create a pulse on the rise of the IXDD404 input, and this pulse will reset the SRFF outputs to normal operation. The IXDD404 is designed to not only provide ±4A per output under normal conditions, but also to allow it's outputs to go into a high impedance state. This permits the IXDD404 output to control a separate weak pull-down circuit during detected overcurrent shutdown conditions to limit and separately control dVGS/dt gate turnoff. This circuit is shown in Figure 27. When a short circuit occurs, the voltage drop across the lowvalue, current-sensing resistor, (Rs=0.005 Ohm), connected between the MOSFET Source and ground, increases. This triggers the comparator at a preset level. The SRFF drives a low input into the Enable pin disabling the IXDD404 output. The SRFF also turns on the low power MOSFET, (2N7000). Referring to Figure 27, the protection circuitry should include a comparator, whose positive input is connected to the source of the IXFD100N20. A low pass filter should be added to the input of the comparator to eliminate any glitches in voltage In this way, the high-power MOSFET module is softly turned off by the IXDD404, preventing its destruction. Figure 29 - Application Test Diagram + Ld 10uH - VB Rd IXDD404 0.1ohm VCC VCCA Rg OUT IN EN + - VCC + - VIN High_Power IXFN100N20 1ohm Rsh 1600ohm DGND SUB Rs Low_Power 2N7002/PLP Ls R+ 10kohm One ShotCircuit Rcomp 5kohm NAND CD4011A NOT1 CD4049A NOT2 CD4049A Ccomp 1pF Ros 0 Comp LM339 V+ V- + C+ 100pF + R 1Mohm Cos 1pF REF Q NOT3 CD4049A NOR1 CD4001A EN NOR2 CD4001A SR Flip-Flop 10 S 20nH - IXDD404 TTL to High Voltage CMOS Level Translation Supply Bypassing and Grounding Practices, Output Lead inductance The enable (EN) input to the IXDD404 is a high voltage CMOS logic level input where the EN input threshold is ½ VCC, and may not be compatible with 5V CMOS or TTL input levels. The IXDD404 EN input was intentionally designed for enhanced noise immunity with the high voltage CMOS logic levels. In a typical gate driver application, VCC =15V and the EN input threshold at 7.5V, a 5V CMOS logical high input applied to this typical IXDD404 application’s EN input will be misinterpreted as a logical low, and may cause undesirable or unexpected results. The note below is for optional adaptation of TTL or 5V CMOS levels. When designing a circuit to drive a high speed MOSFET utilizing the IXDD404, it is very important to keep certain design criteria in mind, in order to optimize performance of the driver. Particular attention needs to be paid to Supply Bypassing, Grounding, and minimizing the Output Lead Inductance. Say, for example, we are using the IXDD404 to charge a 2500pF capacitive load from 0 to 25 volts in 25ns. Using the formula: I= ∆V C / ∆t, where ∆V=25V C=2500pF & ∆t=25ns we can determine that to charge 2500pF to 25 volts in 25ns will take a constant current of 2.5A. (In reality, the charging current won’t be constant, and will peak somewhere around 4A). The circuit in Figure 28 alleviates this potential logic level misinterpretation by translating a TTL or 5V CMOS logic input to high voltage CMOS logic levels needed by the IXDD404 EN input. From the figure, VCC is the gate driver power supply, typically set between 8V to 20V, and VDD is the logic power supply, typically between 3.3V to 5.5V. Resistors R1 and R2 form a voltage divider network so that the Q1 base is positioned at the midpoint of the expected TTL logic transition levels. SUPPLY BYPASSING In order for our design to turn the load on properly, the IXDD404 must be able to draw this 2.5A of current from the power supply in the 25ns. This means that there must be very low impedance between the driver and the power supply. The most common method of achieving this low impedance is to bypass the power supply at the driver with a capacitance value that is a magnitude larger than the load capacitance. Usually, this would be achieved by placing two different types of bypassing capacitors, with complementary impedance curves, very close to the driver itself. (These capacitors should be carefully selected, low inductance, low resistance, high-pulse current-service capacitors). Lead lengths may radiate at high frequency due to inductance, so care should be taken to keep the lengths of the leads between these bypass capacitors and the IXDD404 to an absolute minimum. GROUNDING In order for the design to turn the load off properly, the IXDD404 must be able to drain this 2.5A of current into an adequate grounding system. There are three paths for returning current that need to be considered: Path #1 is between the IXDD404 and it’s load. Path #2 is between the IXDD404 and it’s power supply. Path #3 is between the IXDD404 and whatever logic is driving it. All three of these paths should be as low in resistance and inductance as possible, and thus as short as practical. In addition, every effort should be made to keep these three ground paths distinctly separate. Otherwise, (for instance), the returning ground current from the load may develop a voltage that would have a detrimental effect on the logic line driving the IXDD404. OUTPUT LEAD INDUCTANCE Of equal importance to Supply Bypassing and Grounding are issues related to the Output Lead Inductance. Every effort should be made to keep the leads between the driver and it’s load as short and wide as possible. If the driver must be placed farther than 2” from the load, then the output leads should be treated as transmission lines. In this case, a twisted-pair should be considered, and the return line of each twisted pair should be placed as close as possible to the ground pin of the A TTL or 5V CMOS logic low, VTTLLOW=~<0.8V, input applied to the Q1 emitter will drive it on. This causes the level translator output, the Q1 collector output to settle to VCESATQ1 + VTTLLOW=<~2V, which is sufficiently low to be correctly interpreted as a high voltage CMOS logic low (<1/3VCC=5V for VCC =15V given in the IXDD404 data sheet.) A TTL high, VTTLHIGH=>~2.4V, or a 5V CMOS high, V5VCMOSHIGH=~>3.5V, applied to the EN input of the circuit in Figure 28 will cause Q1 to be biased off. This results in Q1 collector being pulled up by R3 to VCC=15V, and provides a high voltage CMOS logic high output. The high voltage CMOS logical EN output applied to the IXDD404 EN input will enable it, allowing the gate driver to fully function as a ±4 Amp output driver. The total component cost of the circuit in Figure 28 is less than $0.10 if purchased in quantities >1K pieces. It is recommended that the physical placement of the level translator circuit be placed close to the source of the TTL or CMOS logic circuits to maximize noise rejection. Figure 30 - TTL to High Voltage CMOS Level Translator CC (From Gate Driver Power Supply) 10K R3 VDD (From Logic Power Supply) 3.3K Q1 2N3904 3.3K driver, and connect directly to the ground terminal of the load. or TTLInput) 11 R1 R2 High Voltage CMOSEN Output (To IXDD404 EN Input) IXDD404 Dimenional Outline: IXDD404PI Dimenional Outlines: IXDD404SI-CT and IXDD404SIA Dimenional Outlines: IXDD404SI-16CT and IXDD404SIA-16 IXYS Corporation 3540 Bassett St; Santa Clara, CA 95054 Tel: 408-982-0700; Fax: 408-496-0670 e-mail: [email protected] IXYS Semiconductor GmbH Edisonstrasse15 ; D-68623; Lampertheim Tel: +49-6206-503-0; Fax: +49-6206-503627 e-mail: [email protected] 12