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INTER
1- 888-
HFA1205
TM
Dual, 425MHz, Low Power, Video
Operational Amplifier
• Low Supply Current . . . . . . . . . . . . . . . . . 5.8mA/Op Amp
• High Input Impedance . . . . . . . . . . . . . . . . . . . . . . . 2MΩ
• Wide -3dB Bandwidth (AV = +2) . . . . . . . . . . . . . 425MHz
These amplifiers deliver 425MHz bandwidth and 1350V/μs
slew rate, on only 60mW of quiescent power. They are
specifically designed to meet the performance, power, and
cost requirements of high volume video applications. The
excellent gain flatness and differential gain/phase
performance make these amplifiers well suited for
component or composite video applications. Video
performance is maintained even when driving a back
terminated cable (RL = 150Ω), and degrades only slightly
when driving two back terminated cables (RL = 75Ω). RGB
applications will benefit from the high slew rates, and high
full power bandwidth.
The HFA1205 is a pin compatible, low power, high
performance upgrade for the popular Intersil HA5023. For a
dual amplifier with output disable capability, please see the
HFA1245 data sheet.
Part # Information
• Very Fast Slew Rate . . . . . . . . . . . . . . . . . . . . . 1350V/μs
• Gain Flatness (to 50MHz). . . . . . . . . . . . . . . . . . . . . ±0.04dB
• Differential Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.03%
• Differential Phase. . . . . . . . . . . . . . . . . . . . . 0.03 Degrees
• Pin Compatible Upgrade to HA5023
Applications
• Flash A/D Drivers
• High Resolution Monitors
• Video Switching and Routing
• Professional Video Processing
• Video Digitizing Boards/Systems
• Multimedia Systems
• RGB Preamps
TEMP.
RANGE (oC)
PACKAGE
PKG.
NO.
HFA1205IP
-40 to 85
8 Ld PDIP
E8.3
HFA1205IB
(H1205I)
-40 to 85
8 Ld SOIC
M8.15
HA5023EVAL
FN3605.6
Features
The HFA1205 is a dual, high speed, low power current
feedback amplifier built with Intersil’s proprietary
complementary bipolar UHF-1 process.
PART NUMBER
(BRAND)
July 2004
• Medical Imaging
• Hand Held and Miniaturized RF Equipment
• Battery Powered Communications
• High Speed Oscilloscopes and Analyzers
High Speed Op Amp DIP Evaluation Board
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
Pinout
HFA1205
(PDIP, SOIC)
TOP VIEW
OUT1
1
-IN1
2
+IN1
3
V-
1
4
+
+
8
V+
7
OUT2
6
-IN2
5
+IN2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation.
Copyright © Intersil Corporation 2000, 2004
HFA1205
Absolute Maximum Ratings
Thermal Information
Voltage Between V+ and V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSUPPLY
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V
Output Current (Note 2) . . . . . . . . . . . . . . . . . Short Circuit Protected
30mA Continuous
60mA ≤ 50% Duty Cycle
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) . . . 600V
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
105
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
160
Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. Output is short circuit protected to ground. Brief short circuits to ground will not degrade reliability, however continuous (100% duty cycle) output
current must not exceed 30mA for maximum reliability.
Electrical Specifications
VSUPPLY = ±5V, AV = +1, RF = 560Ω, RL = 100Ω, Unless Otherwise Specified
(NOTE 3)
TEST
LEVEL
TEMP.
(oC)
MIN
TYP
MAX
UNITS
Input Offset Voltage
A
25
-
2
5
mV
A
Full
-
3
8
mV
Average Input Offset Voltage Drift
B
Full
-
1
10
μV/ oC
PARAMETER
TEST CONDITIONS
INPUT CHARACTERISTICS
Input Offset Voltage
Common-Mode Rejection Ratio
ΔVCM = ±1.8V
A
25
45
48
-
dB
ΔVCM = ±1.8V
A
85
43
46
-
dB
ΔVCM = ±1.2V
A
-40
43
46
-
dB
Input Offset Voltage
Power Supply Rejection Ratio
ΔVPS = ±1.8V
A
25
48
52
-
dB
ΔVPS = ±1.8V
A
85
46
50
-
dB
ΔVPS = ±1.2V
A
-40
46
50
-
dB
Non-Inverting Input Bias Current
A
25
-
6
15
μA
A
Full
-
10
25
μA
Non-Inverting Input Bias Current Drift
B
Full
-
5
60
nA/ oC
Non-Inverting Input Bias Current
Power Supply Sensitivity
Non-Inverting Input Resistance
ΔVPS = ±1.8V
A
25
-
0.5
1
μA/V
ΔVPS = ±1.8V
A
85
-
0.8
3
μA/V
ΔVPS = ±1.2V
A
-40
-
0.8
3
μA/V
ΔVCM = ±1.8V
A
25
0.8
2
-
MΩ
ΔVCM = ±1.8V
A
85
0.5
1.3
-
MΩ
ΔVCM = ±1.2V
A
-40
0.5
1.3
-
MΩ
Inverting Input Bias Current
A
25
-
2
8.5
μA
A
Full
-
5
15
μA
Inverting Input Bias Current Drift
B
Full
-
60
200
nA/ oC
Inverting Input Bias Current
Common-Mode Sensitivity
2
ΔVCM = ±1.8V
A
25
-
3
6
μA/V
ΔVCM = ±1.8V
A
85
-
4
8
μA/ V
ΔVCM = ±1.2V
A
-40
-
4
8
μA/V
HFA1205
Electrical Specifications
VSUPPLY = ±5V, AV = +1, RF = 560Ω, RL = 100Ω, Unless Otherwise Specified (Continued)
PARAMETER
(NOTE 3)
TEST
LEVEL
TEMP.
(oC)
MIN
TYP
MAX
UNITS
ΔVPS = ±1.8V
A
25
-
2
5
μA/V
ΔVPS = ±1.8V
A
85
-
4
8
μA/V
TEST CONDITIONS
Inverting Input Bias Current
Power Supply Sensitivity
A
-40
-
4
8
μA/V
Inverting Input Resistance
ΔVPS = ±1.2V
C
25
-
55
-
Ω
Input Capacitance
C
25
-
1.5
-
pF
Input Voltage Common Mode Range
(Implied by VIO CMRR, +RIN, and -IBIAS CMS
tests)
A
25, 85
±1.8
±2.4
-
V
A
-40
±1.2
±1.7
-
V
Input Noise Voltage Density (Note 6)
f = 100kHz
B
25
-
3.5
-
nV/√Hz
Non-Inverting Input Noise Current Density (Note 6) f = 100kHz
B
25
-
2.5
-
pA/√Hz
Inverting Input Noise Current Density (Note 6)
B
25
-
25
-
pA/√Hz
C
25
-
400
-
kΩ
AV = +1, +RS = 432Ω
B
25
-
300
-
MHz
AV = +2
B
25
-
425
-
MHz
AV = -1, RF = 332Ω
B
25
-
350
-
MHz
Full Power Bandwidth
(VOUT = 5VP-P at AV = +2/-1,
4VP-P at AV = +1, Note 6)
AV = +1, RS = 432Ω
B
25
-
135
-
MHz
AV = +2
B
25
-
130
-
MHz
AV = -1, RF = 332Ω
B
25
-
200
-
MHz
Gain Flatness
(AV = +2,VOUT = 0.2VP-P, Note 6)
To 25MHz
B
25
-
±0.04
-
dB
To 50MHz
B
25
-
±0.04
-
dB
f = 100kHz
TRANSFER CHARACTERISTICS
Open Loop Transimpedance Gain (Note 6)
AC CHARACTERISTICS
AV = +2, RF = 464Ω, Unless Otherwise Specified
-3dB Bandwidth (VOUT = 0.2VP-P, Note 6)
To 100MHz
Minimum Stable Gain
Crosstalk (AV = +2, Note 6)
B
25
-
±0.07
-
dB
A
Full
-
1
-
V/V
5MHz
B
25
-
-60
-
dB
10MHz
B
25
-
-54
-
dB
AV = -1, RL = 100Ω
RF = 560Ω
A
25
±3
±3.5
-
V
A
Full
±2.8
±3
-
V
AV = -1, RL = 50Ω
RF = 560Ω
A
25, 85
50
60
-
mA
A
-40
28
42
-
mA
OUTPUT CHARACTERISTICS
Output Voltage Swing (Note 6)
Output Current (Note 6)
Output Short Circuit Current
RF = 560Ω
B
25
-
90
-
mA
Closed Loop Output Impedance (Note 6)
DC, AV = +2, RF = 464Ω
B
25
-
0.07
-
Ω
Second Harmonic Distortion
(AV = +2, RF = 464Ω, VOUT = 2VP-P)
10MHz
B
25
-
-53
-
dBc
20MHz
B
25
-
-45
-
dBc
Third Harmonic Distortion
(AV = +2, RF = 464Ω, VOUT = 2VP-P)
10MHz
B
25
-
-55
-
dBc
20MHz
B
25
-
-50
-
dBc
TRANSIENT CHARACTERISTICS
AV = +2, RF = 464Ω, Unless Otherwise Specified
Rise and Fall Times (VOUT = 0.5VP-P)
Rise Time
B
25
-
1.0
-
ns
Fall Time
B
25
-
1.4
-
ns
Overshoot
(VOUT = 0 to 0.5V, VIN tRISE = 1ns, Note 4)
+OS
B
25
-
5
-
%
-OS
B
25
-
4
-
%
Overshoot
(VOUT = 0.5VP-P, VIN tRISE = 1ns, Note 4)
+OS
B
25
-
5
-
%
-OS
B
25
-
10
-
%
3
HFA1205
Electrical Specifications
VSUPPLY = ±5V, AV = +1, RF = 560Ω, RL = 100Ω, Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
(NOTE 3)
TEST
LEVEL
TEMP.
(oC)
MIN
TYP
MAX
UNITS
Slew Rate
(VOUT = 4VP-P, AV = +1, +RS = 432Ω)
+SR
B
25
-
1150
-
V/μs
-SR (Note 5)
B
25
-
800
-
V/μs
Slew Rate (VOUT = 5VP-P, AV = +2)
+SR
B
25
-
1425
-
V/μs
-SR (Note 5)
B
25
-
900
-
V/μs
+SR
B
25
-
2400
-
V/μs
-SR (Note 5)
B
25
-
1350
-
V/μs
Slew Rate
(VOUT = 5VP-P, AV = -1, RF = 332Ω)
Settling Time
(VOUT = +2V to 0V step, Note 6)
Overdrive Recovery Time
VIDEO CHARACTERISTICS
To 0.1%
B
25
-
23
-
ns
To 0.05%
B
25
-
33
-
ns
To 0.025%
B
25
-
85
-
ns
VIN = ±2V
B
25
-
10
-
ns
AV = +2, RF = 464Ω, Unless Otherwise Specified
RL = 150Ω
B
25
-
0.03
-
%
RL = 75Ω
B
25
-
0.03
-
%
RL = 150Ω
B
25
-
0.03
-
Degrees
RL = 75Ω
B
25
-
0.05
-
Degrees
Power Supply Range
C
25
±4.5
-
±5.5
V
Power Supply Current (Note 6)
A
25
5.6
5.8
6.1
mA/
Op Amp
A
Full
5.4
5.9
6.3
mA/
Op Amp
Differential Gain (f = 3.58MHz)
Differential Phase (f = 3.58MHz)
POWER SUPPLY CHARACTERISTICS
NOTES:
3. Test Level: A. Production Tested.; B. Typical or Guaranteed Limit Based on Characterization.; C. Design Typical for Information Only.
4. Undershoot dominates for output signal swings below GND (e.g., 0.5VP-P), yielding a higher overshoot limit compared to the
VOUT = 0V to 0.5V condition. See the “Application Information “section for details.
5. Slew rates are asymmetrical if the output swings below GND (e.g., a bipolar signal). Positive unipolar output signals have symmetric positive
and negative slew rates comparable to the +SR specification. See the “Application Information” text, and the pulse response graphs for details.
6. See Typical Performance Curves for more information.
Application Information
Optimum Feedback Resistor
Although a current feedback amplifier’s bandwidth
dependency on closed loop gain isn’t as severe as that of a
voltage feedback amplifier, there can be an appreciable
decrease in bandwidth at higher gains. This decrease may
be minimized by taking advantage of the current feedback
amplifier’s unique relationship between bandwidth and RF .
All current feedback amplifiers require a feedback resistor,
even for unity gain applications, and RF , in conjunction with
the internal compensation capacitor, sets the dominant pole
of the frequency response. Thus, the amplifier’s bandwidth is
inversely proportional to RF . The HFA1205 design is
optimized for a 464Ω RF at a gain of +2. Decreasing RF
decreases stability, resulting in excessive peaking and
overshoot (Note: Capacitive feedback will cause the same
problems due to the feedback impedance decrease at higher
4
frequencies). At higher gains the amplifier is more stable, so
RF can be decreased in a trade-off of stability for bandwidth.
Table 1 lists recommended RF values for various gains, and
the expected bandwidth. For good channel-to-channel gain
matching, it is recommended that all resistors (termination
as well as gain setting) be ±1% tolerance or better. Note that
a series input resistor, on +IN, is required for a gain of +1, to
reduce gain peaking and increase stability.
TABLE 1. OPTIMUM FEEDBACK RESISTOR
GAIN
(ACL )
RF (Ω)
BANDWIDTH
(MHz)
-1
332
350
+1
464 (+RS = 432Ω)
300
+2
464
425
+5
215
270
+10
180
115
HFA1205
For best operation, the DC source impedance seen by the
non-inverting input should be ≥50Ω. This is especially
important in inverting gain configurations where the noninverting input would normally be connected directly to GND.
Pulse Undershoot and Asymmetrical Slew Rates
The HFA1205 utilizes a quasi-complementary output stage
to achieve high output current while minimizing quiescent
supply current. In this approach, a composite device
replaces the traditional PNP pulldown transistor. The
composite device switches modes after crossing 0V,
resulting in added distortion for signals swinging below
ground, and an increased undershoot on the negative
portion of the output waveform (see Figures 7, 11, 15 and
19). This undershoot isn’t present for small bipolar signals,
or large positive signals (see Figures 5, 6, 9, 10, 13, 14, 17
and 18). Another artifact of the composite device is
asymmetrical slew rates for output signals with a negative
voltage component. The slew rate degrades as the output
signal crosses through 0V (see Figures 7, 11, 15, and 19),
resulting in a slower overall negative slew rate. Positive only
signals have symmetrical slew rates as illustrated in the
large signal positive pulse response graphs (see Figures 5,
9, 13 and 17).
PC Board Layout
The frequency response of this amplifier depends greatly on
the amount of care taken in designing the PC board. The
use of low inductance components such as chip
resistors and chip capacitors is strongly recommended,
while a solid ground plane is a must!
Attention should be given to decoupling the power supplies.
A large value (10μF) tantalum in parallel with a small value
(0.1μF) chip capacitor works well in most cases.
Terminated microstrip signal lines are recommended at the
input and output of the device. Capacitance directly on the
output must be minimized, or isolated as discussed in the
next section.
Care must also be taken to minimize the capacitance to
ground at the amplifier’s inverting input (-IN). The larger this
capacitance, the worse the gain peaking, resulting in pulse
overshoot and possible instability. Reduce this capacitance
by removing the ground plane under traces connected to IN, and keep connections to -IN as short as possible.
Driving Capacitive Loads
Capacitive loads, such as an A/D input, or an improperly
terminated transmission line will degrade the amplifier’s
phase margin resulting in frequency response peaking and
possible oscillations. In most cases, the oscillation can be
avoided by placing a resistor (RS) in series with the output
prior to the capacitance.
5
Figure 1 details starting points for the selection of this
resistor. The points on the curve indicate the RS and CL
combinations for the optimum bandwidth, stability, and
settling time, but experimental fine tuning is recommended.
Picking a point above or to the right of the curve yields an
overdamped response, while points below or left of the curve
indicate areas of underdamped performance.
RS and CL form a low pass network at the output, thus
limiting system bandwidth well below the amplifier
bandwidth of 425MHz (for AV = +2). By decreasing RS as
CL increases (as illustrated in the curves), the maximum
bandwidth is obtained without sacrificing stability. In spite
of this, bandwidth still decreases as the load capacitance
increases. For example, at AV = +2, RS = 50Ω, CL = 22pF,
the overall bandwidth is limited to 230MHz, and bandwidth
drops to 80MHz at AV = +2, RS = 7Ω, CL = 390pF.
50
SERIES OUTPUT RESISTANCE (Ω)
Non-inverting Input Source Impedance
AV = +2
40
30
20
10
0
0
50
100
150
200
250
300
350
400
LOAD CAPACITANCE (pF)
FIGURE 1. RECOMMENDED SERIES OUTPUT RESISTOR vs
LOAD CAPACITANCE
Evaluation Board
The performance of the HFA1205 may be evaluated using
the HA5023 Evaluation Board.
The performance of the HFA1205IB (SOIC) may be
evaluated using the HA5023 Evaluation Board and a SOIC
to DIP adaptor like the Aries Electronics Part Number
08-350000-10.
The schematic for amplifier 1 and the board layout are
shown in Figure 2 and Figure 3. Resistors RF, RG and RS
may require a change to the appropriate value (see
“Optimum Feedback Resistor” section) for the gain being
evaluated.
To order evaluation boards (Part Number HA5023EVAL),
please contact your local sales office.
HFA1205
50Ω
OUT
RG
1
RF
2
IN
50Ω
3
RS
+5V
8
0.1μF
7
+
10μF
6
4
5
GND
GND
−5V
10μF
0.1μF
FIGURE 2. MODIFIED EVALUATION BOARD SCHEMATIC
FIGURE 3A. TOP LAYOUT
FIGURE 3B. BOTTOM LAYOUT
FIGURE 3. EVALUATION BOARD LAYOUT
6
HFA1205
Typical Performance Curves
VSUPPLY = ±5V, RF = Value From the Optimum Feedback Resistor Table, TA = 25oC, RL = 100Ω,
Unless Otherwise Specified
300
3.0
AV = +2
250
2.5
200
2.0
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (mV)
AV = +2
150
100
50
0
-100
0
TIME (5ns/DIV.)
FIGURE 5. LARGE SIGNAL POSITIVE PULSE RESPONSE
2.0
AV = +2
150
1.5
100
1.0
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (mV)
0.5
-1.0
TIME (5ns/DIV.)
FIGURE 4. SMALL SIGNAL POSITIVE PULSE RESPONSE
50
0
-50
-100
-150
0
-0.5
-1.0
TIME (5ns/DIV.)
FIGURE 7. LARGE SIGNAL BIPOLAR PULSE RESPONSE
300
3.0
AV = +1
AV = +1
2.5
200
OUTPUT VOLTAGE (V)
2.0
150
100
50
0
-50
-100
0.5
-2.0
TIME (5ns/DIV.)
FIGURE 6. SMALL SIGNAL BIPOLAR PULSE RESPONSE
250
AV = +2
-1.5
-200
OUTPUT VOLTAGE (mV)
1.0
-0.5
-50
200
1.5
1.5
1.0
0.5
0
-0.5
TIME (5ns/DIV.)
FIGURE 8. SMALL SIGNAL POSITIVE PULSE RESPONSE
7
-1.0
TIME (5ns/DIV.)
FIGURE 9. LARGE SIGNAL POSITIVE PULSE RESPONSE
HFA1205
Typical Performance Curves
VSUPPLY = ±5V, RF = Value From the Optimum Feedback Resistor Table, TA = 25oC, RL = 100Ω,
Unless Otherwise Specified (Continued)
2.0
200
1.5
1.0
100
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (mV)
150
AV = +1
AV = +1
50
0
-50
-100
-2.0
TIME (5ns/DIV.)
FIGURE 10. SMALL SIGNAL BIPOLAR PULSE RESPONSE
TIME (5ns/DIV.)
FIGURE 11. LARGE SIGNAL BIPOLAR PULSE RESPONSE
300
3.0
AV = -1
AV = -1
2.5
200
2.0
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (mV)
-0.5
-1.5
-200
150
100
50
0
-50
-100
0
-1.0
-150
250
0.5
1.5
1.0
0.5
0
-0.5
-1.0
TIME (5ns/DIV.)
FIGURE 12. SMALL SIGNAL POSITIVE PULSE RESPONSE
8
TIME (5ns/DIV.)
FIGURE 13. LARGE SIGNAL POSITIVE PULSE RESPONSE
HFA1205
Typical Performance Curves
VSUPPLY = ±5V, RF = Value From the Optimum Feedback Resistor Table, TA = 25oC, RL = 100Ω,
Unless Otherwise Specified (Continued)
2.0
200
AV = -1
1.5
1.0
100
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (mV)
150
AV = -1
50
0
-50
-100
0.5
0
-0.5
-1.0
-150
-1.5
-200
-2.0
TIME (5ns/DIV.)
FIGURE 14. SMALL SIGNAL BIPOLAR PULSE RESPONSE
FIGURE 15. LARGE SIGNAL BIPOLAR PULSE RESPONSE
3.0
300
250
2.5
AV = +5
AV = +5
2.0
200
AV = +10
150
100
50
AV = +5
0
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (mV)
TIME (5ns/DIV.)
-50
1.5
1.0
0.5
AV = +5
0
-0.5
-100
-1.0
TIME (5ns/DIV.)
TIME (5ns/DIV.)
FIGURE 16. SMALL SIGNAL POSITIVE PULSE RESPONSE
FIGURE 17. LARGE SIGNAL POSITIVE PULSE RESPONSE
2.0
200
150
1.5
AV = +5
AV = +5
1.0
AV = +10
50
0
-50
AV = +5
-100
OUTPUT VOLTAGE (V)
100
OUTPUT VOLTAGE (mV)
AV = +10
AV = +10
0.5
0
-0.5
-1.0
AV = +5
-1.5
-150
-2.0
-200
TIME (5ns/DIV.)
FIGURE 18. SMALL SIGNAL BIPOLAR PULSE RESPONSE
9
TIME (5ns/DIV.)
FIGURE 19. LARGE SIGNAL BIPOLAR PULSE RESPONSE
HFA1205
Typical Performance Curves
VSUPPLY = ±5V, RF = Value From the Optimum Feedback Resistor Table, TA = 25oC, RL = 100Ω,
Unless Otherwise Specified (Continued)
630
AV = +2
VOUT = 2V
CH2
200
20
0.025
0
-0.025
-0.05
6.3
2.0
0.63
90
0.2
45
20
30
40
50
60
TIME (ns)
70
80
90
100
0.001
AV = +1, CH1
PHASE
AV = -1
0
90
AV = +1
BOTH CHANNELS SHOWN
1
AV = -1
10
100
FREQUENCY (MHz)
FIGURE 22. FREQUENCY RESPONSE
10
180
270
360
1000
NORMALIZED GAIN (dB)
AV = +1, CH2
GAIN
-3
0.01
0.1
1
3 6 10
FREQUENCY (MHz)
100
500
FIGURE 21. OPEN LOOP TRANSIMPEDANCE
NORMALIZED PHASE (DEGREES)
GAIN (dB)
FIGURE 20. SETTLING TIME RESPONSE
VOUT = 200mVP-P
0
VOUT = 200mVP-P
3
AV = +2, CH2
GAIN
0
AV = +2, CH1
AV = +5
-3
-6
PHASE
AV = +10
0
90
AV = +10
AV = +5
AV = +2
180
270
360
BOTH CHANNELS SHOWN
1
10
100
FREQUENCY (MHz)
FIGURE 23. FREQUENCY RESPONSE
1000
PHASE (DEGREES)
10
-6
135
0.063
-0.1
0
180
PHASE
PHASE (DEGREES)
0.05
3
GAIN
63
GAIN (kΩ)
SETTLING ERROR (%)
0.1
HFA1205
Typical Performance Curves
VSUPPLY = ±5V, RF = Value From the Optimum Feedback Resistor Table, TA = 25oC, RL = 100Ω,
AV = +1
GAIN (dB)
VOUT = 1VP-P , CH2
GAIN
0
VOUT = 1VP-P , CH1
-3
VOUT = 2.5VP-P
-6
GAIN
0
VOUT = 4VP-P
-3
VOUT = 1VP-P , CH1
-6
VOUT = 4VP-P
PHASE
0
90
VOUT = 4VP-P
VOUT = 2.5VP-P
VOUT = 1VP-P
180
270
360
10
100
FREQUENCY (MHz)
90
VOUT = 4VP-P
VOUT = 2.5VP-P
VOUT = 1VP-P
180
270
360
1000
1
AV = -1
10
100
FREQUENCY (MHz)
1000
FIGURE 25. FREQUENCY RESPONSE FOR VARIOUS OUTPUT
VOLTAGES
BOTH CHANNELS SHOWN
VOUT = 1VP-P
-3
VOUT = 4VP-P
-6
PHASE
VOUT = 2.5VP-P
0
VOUT = 4VP-P
90
VOUT = 2.5VP-P
180
VOUT = 1VP-P
270
360
BOTH CHANNELS SHOWN
1
10
100
FREQUENCY (MHz)
NORMALIZED GAIN (dB)
GAIN
0
NORMALIZED PHASE (DEGREES)
GAIN (dB)
0
BOTH CHANNELS SHOWN
FIGURE 24. FREQUENCY RESPONSE FOR VARIOUS OUTPUT
VOLTAGES
3
VOUT = 2.5VP-P
PHASE
BOTH CHANNELS SHOWN
1
VOUT = 1VP-P , CH2
3
PHASE (DEGREES)
AV = +2
3
PHASE (DEGREES)
NORMALIZED GAIN (dB)
Unless Otherwise Specified (Continued)
3
0
AV = +2, VOUT = 5VP-P
-3
AV = +1, VOUT = 4VP-P
-6
-9
1000
AV = -1, VOUT = 5VP-P
1
10
100
FREQUENCY (MHz)
FIGURE 26. FREQUENCY RESPONSE FOR VARIOUS OUTPUT
VOLTAGES
1000
FIGURE 27. FULL POWER BANDWIDTH
-40
VOUT = 200mVP-P
-45
AV = +1, CH2
0.3
AV = -1
0.2
AV = +2, CH2
0.1
0
-0.1
AV = +2, CH1
-0.2
-0.3
RL = 100Ω
-50
CROSSTALK (dB)
NORMALIZED GAIN (dB)
0.4
RL = 1kΩ
-55
-60
-65
-70
-75
-80
AV = +1, CH1
-85
-0.4
BOTH CHANNELS SHOWN
1
10
FREQUENCY (MHz)
FIGURE 28. GAIN FLATNESS
11
100
0.3
1
10
FREQUENCY (MHz)
FIGURE 29. CROSSTALK
100
HFA1205
Typical Performance Curves
VSUPPLY = ±5V, RF = Value From the Optimum Feedback Resistor Table, TA = 25oC, RL = 100Ω,
Unless Otherwise Specified (Continued)
10
AV = +2
20
OUTPUT RESISTANCE (Ω)
AV = +2
ISOLATION (dB)
30
40
AV = +1
50
60
70
80
1K
100
10
1
0.1
0.01
90
100
10
100
FREQUENCY (MHz)
0.3
1000
1
10
FIGURE 30. REVERSE ISOLATION (S12)
100
100
AV = +2
NOISE VOLTAGE (nV/√Hz)
TOI (dBm)
25
20
15
10
0
50
100
INI-
INI+
ENI
0.1
TOTAL SUPPLY CURRENT (mA)
OUTPUT VOLTAGE (V)
25oC
3.3
3.2
|-VOUT| (RL = 50Ω)
3.1
+VOUT (RL = 50Ω)
3.0
100
16
+VOUT (RL = 100Ω)
3.4
1
10
FREQUENCY (kHz)
FIGURE 33. INPUT NOISE CHARACTERISTICS
|-VOUT| (RL = 100Ω)
3.5
1
1
150
FIGURE 32. 3rd ORDER INTERCEPT vs FREQUENCY
AV = -1
10
10
FREQUENCY (MHz)
3.6
1000
FIGURE 31. OUTPUT RESISTANCE
30
5
100
FREQUENCY (MHz)
NOISE CURRENT (pA/√Hz)
1
2.9
2.8
14
-55oC
12
125oC
10
25oC
8
6
2.7
2.6
-50
-25
0
25
50
75
TEMPERATURE (oC)
100
FIGURE 34. OUTPUT VOLTAGE vs TEMPERATURE
12
125
4
3
4
5
6
SUPPLY VOLTAGE (±V)
7
FIGURE 35. SUPPLY CURRENT vs SUPPLY VOLTAGE
8
HFA1205
Die Characteristics
DIE DIMENSIONS:
SUBSTRATE POTENTIAL (POWERED UP):
69 mils x 92 mils
1750μm x 2330μm
Floating (Recommend Connection to V-)
PASSIVATION:
METALLIZATION:
Type: Nitride
Thickness: 4kÅ ± 0.5kÅ
Type: Metal 1: AICu (2%)/TiW
Thickness: Metal 1: 8kÅ ± 0.4kÅ
Type: Metal 2: AICu (2%)
Thickness: Metal 2: 16kÅ ± 0.8kÅ
TRANSISTOR COUNT:
180
Metallization Mask Layout
HFA1205
-IN1
OUT1
NC
V+
NC
OUT2
+IN1
NC
NC
-IN2
NC
V-
NC
13
+IN2
HFA1205
Dual-In-Line Plastic Packages (PDIP)
E8.3 (JEDEC MS-001-BA ISSUE D)
N
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
1 2 3
INCHES
N/2
-B-
-AD
E
BASE
PLANE
-C-
SEATING
PLANE
A2
A
L
D1
e
B1
D1
A1
eC
B
0.010 (0.25) M
C A B S
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.210
-
5.33
4
A1
0.015
-
0.39
-
4
A2
0.115
0.195
2.93
4.95
-
B
0.014
0.022
0.356
0.558
-
C
L
B1
0.045
0.070
1.15
1.77
8, 10
eA
C
0.008
0.014
0.204
C
D
0.355
0.400
9.01
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.
0.005
-
0.13
-
5
E
0.300
0.325
7.62
8.25
6
E1
0.240
0.280
6.10
7.11
5
e
0.100 BSC
eA
0.300 BSC
3. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication No. 95.
eB
-
L
0.115
5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
14
5
D1
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
4. Dimensions A, A1 and L are measured with the package seated
in JEDEC seating plane gauge GS-3.
0.355
10.16
N
8
2.54 BSC
7.62 BSC
0.430
-
0.150
2.93
8
6
10.92
7
3.81
4
9
Rev. 0 12/93
HFA1205
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
N
INDEX
AREA
0.25(0.010) M
H
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
B M
E
INCHES
-B-
1
2
SYMBOL
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
e
µα
A1
B
0.25(0.010) M
C
C A M
B S
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
MILLIMETERS
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.1890
0.1968
4.80
5.00
3
E
0.1497
0.1574
3.80
4.00
4
0.050 BSC
1.27 BSC
-
H
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
8o
0o
N
NOTES:
MAX
A1
e
0.10(0.004)
MIN
α
8
0o
8
7
8o
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
15
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