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February 2002
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Dual 8-bit, +3.3V, 130/210+MSPS, High
Speed D/A Converter
ISL5629
FN6018.1
Features
• Speed Grades . . . . . . . . . . . . . . . . 130M and 210+MSPS
The ISL5629 is a dual 8-bit, 130/210+MSPS (Mega Samples
Per Second), CMOS, high speed, low power, D/A (digital to
analog) converter, designed specifically for use in
communication systems.
This device complements the ISL5x61 and ISL5x29 families
of high speed converters, which include 8-, 10-, 12-, and 14bit devices.
• Low Power . . . . . 233mW with 20mA Output at 130MSPS
• Adjustable Full Scale Output Current . . . . . 2mA to 20mA
• Guaranteed Gain Matching < 0.14dB
• +3.3V Power Supply
• 3V LVCMOS Compatible Inputs
• Excellent Spurious Free Dynamic Range
(67dBc to Nyquist, f S = 130MSPS, fOUT = 10MHz)
Ordering Information
• Dual, 3.3V, Lower Power Replacement for AD9709
TEMP.
RANGE
(oC)
PACKAGE
ISL5629IN
-40 to 85
48 Ld LQFP
Q48.7x7A 130MHz
• Quadrature Transmit with IF Range 0-80MHz
ISL5629/2IN
-40 to 85
48 Ld LQFP
Q48.7x7A 210MHz
• Medical/Test Instrumentation and Equipment
PART
NUMBER
ISL5629EVAL1
25
PKG. NO.
Evaluation Platform
CLOCK
SPEED
210MHz
Applications
• Wireless Communication Systems
Pinout
NC
NC
NC
NC
NC
NC
ID7 (MSB)
ID4
ID5
ID6
ID3
ID2
ISL5629
(LQFP)
TOP VIEW
ID1
1
48 47 46 45 44 43 42 41 40 39 38 37
36
(LSB) ID0
2
35
QD1
NC
NC
3
34
QD2
4
33
NC
5
32
NC
6
7
31
QD3
QD4
QD5
30
QD6
NC
8
29
SLEEP
DVDD
9
28
QD7 (MSB)
CLK
10
27
DGND
11
12
26
AGND
1
NC
QCOMP
AVDD
QOUTB
QOUTA
AGND
FSADJ
REFIO
REFLO
IOUTA
IOUTB
ICOMP
25
13 14 15 16 17 18 19 20 21 22 23 24
NC
AGND
AVDD
NC
QD0 (LSB)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
ISL5629
ID2
ID3
ID4
ID5
ID6
ID7 (MSB)
NC
NC
NC
NC
NC
NC
Typical Applications Circuit
SLEEP
DVPP
C1
0.1F
ICOMP
C2
0.1F
AVPP
48 47 46 45 44 43 42 41 40 39 38 37
36
1
35
2
34
3
33
4
32
5
31
6
30
7
29
8
CLK 28
9
DGND 27
10 DVDD
AGND 26
11 AGND
25
12
13 14 15 16 17 18 19 20 21 22 23 24
REFIO
REFLO
AGND
FSADJ
ID1
(LSB) ID0
NC
NC
NC
NC
NC
NC
AVDD
AVDD
C4
0.1F
QD0 (LSB)
QD1
QD2
QD3
QD4
QD5
QD6
QD7 (MSB)
R1
50
QCOMP
C3
0.1F
AVPP
C5
0.1F
C6
0.1F
RSET
1.91k
50
R3
R2
50
1:1 TRANSFORMER
(50)
REPRESENTS
ANY 50 LOAD
(50)
QOUT
IOUT
BEAD
FERRITE
+ C11
10F
L1
10H
DVPP (DIGITAL POWER PLANE) = +3.3V
C9
0.1F
C10
1F
C12
0.1F
C13
1F
+3.3V POWER SOURCE
FERRITE
BEAD
+ C14
10F
2
L2
10H
AVPP (ANALOG POWER PLANE) = +3.3V
FN6018.1
February 2002
ISL5629
Functional Block Diagram
NC
QOUTA
NC
QOUTB
NC
NC
NC
INPUT
LATCH
CASCODE
NC
34
(LSB) QD0
SWITCH
MATRIX
34
CURRENT
SOURCE
QD1
QD2
3 LSBs
QD3
QD4
QD5
QD6
+
31 MSB
SEGMENTS
UPPER
5-BIT
DECODER
(MSB) QD7
QCOMP
SLEEP
INT/EXT
VOLTAGE
CLK
BIAS
GENERATION
REFERENCE
FSADJ
REFIO
REFLO
ICOMP
NC
NC
IOUTA
NC
NC
NC
IOUTB
INPUT
LATCH
CASCODE
NC
34
(LSB) ID0
SWITCH
MATRIX
34
CURRENT
SOURCE
ID1
ID2
3 LSBs
ID3
ID4
ID5
ID6
UPPER
5-BIT
+
31 MSB
SEGMENTS
DECODER
(MSB) ID7
3
FN6018.1
February 2002
ISL5629
Pin Descriptions
PIN NO.
PIN NAME
PIN DESCRIPTION
11, 19, 26
AGND
Analog ground.
13, 24
AVDD
Analog supply (+2.7V to +3.6V).
28
CLK
Clock input.
27
DGND
Connect to digital ground.
10
DVDD
Digital supply (+2.7V to +3.6V).
20
FSADJ
Full scale current adjust. Use a resistor to ground to adjust full scale output current. Full scale output
current = 32 x VFSADJ/RSET.
14, 23
NC
12, 25
ICOMP, QCOMP
1-2, 29-36,
43-48
ID7-ID0, QD7-QD0
15, 22
IOUTA, QOUTA
Current outputs of the device. Full scale output current is achieved when all input bits are set to binary 1.
16, 21
IOUTB, QOUTB
Complementary current outputs of the device. Full scale output current is achieved on the complementary
outputs when all input bits are set to binary 0.
17
REFIO
Reference voltage input if Internal reference is disabled. The internal reference is not intended to drive an
external load. Use 0.1F cap to ground when internal reference is enabled.
18
REFLO
Connect to analog ground to enable internal 1.2V reference or connect to AVDD to disable internal reference.
3-8, 37-42
NC
No connect (NC). Not internally connected. No termination required, may be used for device migration to
higher resolution DACs.
9
SLEEP
Not internally connected. Recommend no connect.
Compensation pin for internal bias generation. Each pin should be individually decoupled to AGND with
a 0.1F capacitor.
Digital data input ports. Bit 7 is most significant bit (MSB) and bit 0 is the least significant bit (LSB).
Connect to digital ground or leave floating for normal operation. Connect to DVDD for sleep mode.
4
FN6018.1
February 2002
ISL5629
Absolute Maximum Ratings
Thermal Information
Digital Supply Voltage DVDD to DGND . . . . . . . . . . . . . . . . . . +3.6V
Analog Supply Voltage AVDD to AGND . . . . . . . . . . . . . . . . . . +3.6V
Grounds, AGND TO DGND . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Digital Input Voltages (DATA, CLK, SLEEP) . . . . . . . . DVDD + 0.3V
Reference Input Voltage Range. . . . . . . . . . . . . . . . . . AVDD + 0.3V
Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA
Thermal Resistance (Typical, Note 1)
JA(°C/W)
LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
AVDD = DVDD = +3.3V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25°C for All Typical Values
TA = -40°C TO 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
8
-
-
Bits
SYSTEM PERFORMANCE
Resolution
Integral Linearity Error, INL
“Best Fit” Straight Line (Note 7)
-0.5
0.05
+0.5
LSB
Differential Linearity Error, DNL
(Note 7)
-0.5
0.05
+0.5
LSB
Offset Error, IOS
IOUTA (Note 7)
+0.006
% FSR
Offset Drift Coefficient
(Note 7)
-
0.1
-
ppm
FSR/°C
Full Scale Gain Error, FSE
With External Reference (Notes 2, 7)
-3
0.5
+3
% FSR
With Internal Reference (Notes 2, 7)
-3
0.5
+3
% FSR
With External Reference (Note 7)
-
50
-
ppm
FSR/°C
With Internal Reference (Note 7)
-
100
-
ppm
FSR/°C
fCLK = 100MSPS, fOUT = 10MHz
-
83
-
dB
Full Scale Gain Drift
Crosstalk
fCLK = 100MSPS, fOUT = 40MHz
-0.006
-
74
-
dB
As a percentage of Full Scale Range
-1.6
0.6
+1.6
% FSR
In dB Full Scale Range
-0.14
0.05
+0.14
dB FSR
2
20
22
mA
(Note 3)
-1.0
-
1.25
V
Maximum Clock Rate, fCLK
ISL5629/2IN
210
250
-
MHz
Maximum Clock Rate, fCLK
ISL5629IN
130
150
-
MHz
Gain Matching Between Channels
(DC Measurement)
Full Scale Output Current, IFS
Output Voltage Compliance Range
DYNAMIC CHARACTERISTICS
Output Rise Time
Full Scale Step
-
1
-
ns
Output Fall Time
Full Scale Step
-
1
-
ns
-
5
-
pF
IOUTFS = 20mA
-
50
-
pA/Hz
IOUTFS = 2mA
-
30
-
pA/Hz
Output Capacitance
Output Noise
5
FN6018.1
February 2002
ISL5629
Electrical Specifications
AVDD = DVDD = +3.3V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25°C for All Typical Values (Continued)
TA = -40°C TO 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
AC CHARACTERISTICS (Using Figure 6 with RDIFF = 50 and RLOAD = 50, Full Scale Output = -2.5dBm
Spurious Free Dynamic Range,
SFDR Within a Window
Spurious Free Dynamic Range,
SFDR to Nyquist (fCLK/2)
fCLK = 210MSPS, fOUT = 80.8MHz, 30MHz Span (Notes 4, 7)
-
62
-
dBc
fCLK = 210MSPS, fOUT = 40.4MHz, 30MHz Span (Notes 4, 7)
-
66
-
dBc
fCLK = 130MSPS, fOUT = 20.2MHz, 20MHz Span (Notes 4, 7)
-
66
-
dBc
fCLK = 210MSPS, fOUT = 80.8MHz (Notes 4, 7)
-
50
-
dBc
fCLK = 210MSPS, fOUT = 40.4MHz (Notes 4, 7, 9)
-
58
-
dBc
fCLK = 200MSPS, fOUT = 20.2MHz, T = 25°C (Notes 4, 7)
56
62
-
dBc
fCLK = 200MSPS, fOUT = 20.2MHz, T = -40°C to 85°C (Notes 4, 7)
54
-
-
dBc
fCLK = 130MSPS, fOUT = 50.5MHz (Notes 4, 7)
-
52
-
dBc
fCLK = 130MSPS, fOUT = 40.4MHz (Notes 4, 7)
-
55
-
dBc
fCLK = 130MSPS, fOUT = 20.2MHz (Notes 4, 7)
-
65
-
dBc
63
67
-
dBc
fCLK = 130MSPS, fOUT = 5.05MHz (Notes 4, 7)
-
67
-
dBc
fCLK = 100MSPS, fOUT = 40.4MHz (Notes 4, 7)
-
56
-
dBc
fCLK = 80MSPS, fOUT = 30.3MHz (Notes 4, 7)
-
59
-
dBc
fCLK = 130MSPS, fOUT = 10.1MHz, T = -40°C to 85°C (Notes 4, 7)
fCLK = 80MSPS, fOUT = 20.2MHz (Notes 4, 7)
-
66
-
dBc
fCLK = 80MSPS, fOUT = 10.1MHz (Notes 4, 7, 9)
-
66
-
dBc
fCLK = 80MSPS, fOUT = 5.05MHz (Notes 4, 7)
-
67
-
dBc
fCLK = 50MSPS, fOUT = 20.2MHz (Notes 4, 7)
-
60
-
dBc
fCLK = 50MSPS, fOUT = 10.1MHz (Notes 4, 7)
-
66
-
dBc
fCLK = 50MSPS, fOUT = 5.05MHz (Notes 4, 7)
-
66
-
dBc
fCLK = 210MSPS, fOUT = 28.3MHz to 45.2MHz, 2.1MHz Spacing,
50MHz Span (Notes 4, 7, 9)
-
58
-
dBc
fCLK = 130MSPS, fOUT = 17.5MHz to 27.9MHz, 1.3MHz Spacing,
35MHz Span (Notes 4, 7)
-
60
-
dBc
fCLK = 80MSPS, fOUT = 10.8MHz to 17.2MHz, 811kHz Spacing,
15MHz Span (Notes 4, 7)
-
60
-
dBc
fCLK = 50MSPS, fOUT = 6.7MHz to 10.8MHz, 490kHz Spacing,
10MHz Span (Notes 4, 7)
-
60
-
dBc
1.2
1.23
1.3
V
-
40
-
ppm/°C
-
0
-
A
Reference Input Impedance
-
1
-
M
Reference Input Multiplying Bandwidth (Note 7)
-
1.0
-
MHz
Spurious Free Dynamic Range,
SFDR in a Window with Eight Tones
VOLTAGE REFERENCE
Internal Reference Voltage, VFSADJ
Pin 20 Voltage with Internal Reference
Internal Reference Voltage Drift
Internal Reference Output Current
Sink/Source Capability
DIGITAL INPUTS
Reference is not intended to drive an external load
D7-D0, CLK
Input Logic High Voltage with
3.3V Supply, VIH
(Note 3)
2.3
3.3
-
V
Input Logic Low Voltage with
3.3V Supply, VIL
(Note 3)
-
0
1.0
V
Sleep Input Current, IIH
-25
-
+25
A
Input Logic Current, IIH, IL
-20
-
+20
A
6
FN6018.1
February 2002
ISL5629
Electrical Specifications
AVDD = DVDD = +3.3V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25°C for All Typical Values (Continued)
TA = -40°C TO 85°C
PARAMETER
TEST CONDITIONS
Clock Input Current, IIH, IL
Digital Input Capacitance, CIN
MIN
TYP
MAX
UNITS
-10
-
+10
A
-
3
-
pF
TIMING CHARACTERISTICS
Data Setup Time, tSU
See Figure 8
-
1.5
-
ns
Data Hold Time, tHLD
See Figure 8
-
1.5
-
ns
Propagation Delay Time, tPD
See Figure 8
-
1
-
Clock
Period
CLK Pulse Width, tPW1 , tPW2
See Figure 8 (Note 3)
2
-
-
ns
POWER SUPPLY CHARACTERISTICS
AVDD Power Supply
(Note 8)
2.7
3.3
3.6
V
DVDD Power Supply
(Note 8)
2.7
3.3
3.6
V
Analog Supply Current (IAVDD)
3.3V, IOUTFS = 20mA
-
60
62
mA
3.3V, IOUTFS = 2mA
-
24
-
mA
3.3V (Note 5)
-
11
15
mA
3.3V (Note 6)
-
17
21
mA
Supply Current (IAVDD) Sleep Mode
3.3V, IOUTFS = Don’t Care
-
5
-
mA
Power Dissipation
3.3V, IOUTFS = 20mA (Note 5)
-
233
255
mW
3.3V, IOUTFS = 20mA (Note 6)
-
253
274
mW
3.3V, IOUTFS = 2mA (Note 5)
-
115
-
mW
-0.125
-
+0.125
%FSR/V
Digital Supply Current (IDVDD)
Power Supply Rejection
Single Supply (Note 7)
NOTES:
2. Gain Error measured as the error in the ratio between the full scale output current and the current through RSET (typically 625A). Ideally the
ratio should be 32.
3. Parameter guaranteed by design or characterization and not production tested.
4. Spectral measurements made with differential transformer coupled output and no external filtering. For multitone testing, the same pattern was
used at different clock rates, producing different output frequencies but at the same ratio to the clock rate.
5. Measured with the clock at 130MSPS and the output frequency at 10MHz.
6. Measured with the clock at 200MSPS and the output frequency at 20MHz.
7. See Definition of Specifications.
8. Recommended operation is from 3.0V to 3.6V. Operation below 3.0V is possible with some degradation in spectral performance. Reduction in
analog output current may be necessary to maintain spectral performance.
9. See Typical Performance plots.
7
FN6018.1
February 2002
ISL5629
Typical Performance (+3.3V Supply, Using Figure 6 with RDIFF = 100 and RLOAD = 50)
FIGURE 1. ONE TONE AT 10.1MHz, 80MSPS CLOCK
(66dBc - NYQUIST, 6dB PAD)
FIGURE 2. ONE TONE AT 40.4MHz, 210MSPS CLOCK
(56dBc - NYQUIST, 6dB PAD)
FIGURE 3. EIGHT TONES (CREST FACTOR=8.9) AT 37MHz,
210MSPS CLOCK, 2.1MHz SPACING
(57dBc - NYQUIST)
FIGURE 4. TWO TONES (CF=6) AT 8.5MHz, 50MSPS CLOCK,
500kHz SPACING (67dBc - 10MHz WINDOW,
6dB PAD)
FIGURE 5. FOUR TONES (CF=8.1) AT 14MHz, 80MSPS
CLOCK, 800kHz SPACING (61dBc - NYQUIST,
6dB PAD)
8
FN6018.1
February 2002
ISL5629
Definition of Specifications
Crosstalk, is the measure of the channel isolation from one
DAC to the other. It is measured by generating a sinewave in
one DAC while the other DAC is clocked with a static input,
and comparing the output power of each DAC at the
frequency generated.
Differential Linearity Error, DNL, is the measure of the
step size output deviation from code to code. Ideally the step
size should be one LSB. A DNL specification of one LSB or
less guarantees monotonicity.
EDGE, Enhanced Data for Global Evolution, a TDMA
standard for cellular applications which uses 200kHz BW,
8-PSK modulated carriers.
Full Scale Gain Drift, is measured by setting the data inputs
to be all logic high (all 1s) and measuring the output voltage
through a known resistance as the temperature is varied
from TMIN to TMAX . It is defined as the maximum deviation
from the value measured at room temperature to the value
measured at either TMIN or TMAX . The units are ppm of FSR
(full scale range) per °C.
Full Scale Gain Error, is the error from an ideal ratio of 32
between the output current and the full scale adjust current
(through RSET).
Gain Matching, is a measure of the full scale amplitude
match between the I and Q channels given the same input
pattern. It is typically measured with all 1s at the input to both
channels, and the full scale output voltage developed into
matching loads is compared for the I and Q outputs.
Integral Linearity Error, INL, is the measure of the worst
case point that deviates from a best fit straight line of data
values along the transfer curve.
Internal Reference Voltage Drift, is defined as the
maximum deviation from the value measured at room
temperature to the value measured at either TMIN or TMAX .
The units are ppm per °C.
Offset Drift, is measured by setting the data inputs to all
logic low (all 0s) and measuring the output voltage at IOUTA
through a known resistance as the temperature is varied
from TMIN to TMAX . It is defined as the maximum deviation
from the value measured at room temperature to the value
measured at either TMIN or TMAX . The units are ppm of FSR
(full scale range) per degree °C.
Offset Error, is measured by setting the data inputs to all
logic low (all 0s) and measuring the output voltage of IOUTA
through a known resistance. Offset error is defined as the
maximum deviation of the IOUTA output current from a value
of 0mA.
Output Voltage Compliance Range, is the voltage limit
imposed on the output. The output impedance should be
9
chosen such that the voltage developed does not violate the
compliance range.
Power Supply Rejection, is measured using a single power
supply. The nominal supply voltage is varied 10% and the
change in the DAC full scale output is noted.
Reference Input Multiplying Bandwidth, is defined as the
3dB bandwidth of the voltage reference input. It is measured
by using a sinusoidal waveform as the external reference
with the digital inputs set to all 1s. The frequency is
increased until the amplitude of the output waveform is
0.707 (-3dB) of its original value.
Spurious Free Dynamic Range, SFDR, is the amplitude
difference from the fundamental signal to the largest
harmonically or non-harmonically related spur within the
specified frequency window.
Total Harmonic Distortion, THD, is the ratio of the RMS
value of the fundamental output signal to the RMS sum of
the first five harmonic components.
Detailed Description
The ISL5629 is a dual 8-bit, current out, CMOS, digital to
analog converter. The maximum update rate is at least
210+MSPS and can be powered by a single power supply in
the recommended range of +3.0V to +3.6V. Operation with
clock rates higher than 210MSPS is possible; please contact
the factory for more information. It consumes less than
125mW of power per channel when using a +3.3V supply,
the maximum 20mA of output current, and the data switching
at 210MSPS. The architecture is based on a segmented
current source arrangement that reduces glitch by reducing
the amount of current switching at any one time. In previous
architectures that contained all binary weighted current
sources or a binary weighted resistor ladder, the converter
might have a substantially larger amount of current turning
on and off at certain, worst-case transition points such as
midscale and quarter scale transitions. By greatly reducing
the amount of current switching at these major transitions,
the overall glitch of the converter is dramatically reduced,
improving settling time, transient problems, and accuracy.
Digital Inputs and Termination
The ISL5629 digital inputs are formatted as offset binary and
guaranteed to 3V LVCMOS levels. The internal register is
updated on the rising edge of the clock. To minimize
reflections, proper termination should be implemented. If the
lines driving the clock and the digital inputs are long 50
lines, then 50 termination resistors should be placed as
close to the converter inputs as possible connected to the
digital ground plane (if separate grounds are used). These
termination resistors are not likely needed as long as the
digital waveform source is within a few inches of the DAC.
For pattern drivers with very high speed edge rates, it is
recommended that the user consider series termination (50-
FN6018.1
February 2002
ISL5629
200prior to the DAC’s inputs in order to reduce the
amount of noise.
Power Supply
Separate digital and analog power supplies are
recommended. The allowable supply range is +2.7V to
+3.6V. The recommended supply range is +3.0 to 3.6V
(nominally +3.3V) to maintain optimum SFDR. However,
operation down to +2.7V is possible with some degradation
in SFDR. Reducing the analog output current can help the
SFDR at +2.7V. The SFDR values stated in the table of
specifications were obtained with a +3.3V supply.
Ground Planes
Separate digital and analog ground planes should be used.
All of the digital functions of the device and their
corresponding components should be located over the
digital ground plane and terminated to the digital ground
plane. The same is true for the analog components and the
analog ground plane.
Noise Reduction
To minimize power supply noise, 0.1F capacitors should be
placed as close as possible to the converter’s power supply
pins, AVDD and DVDD . Also, the layout should be designed
using separate digital and analog ground planes and these
capacitors should be terminated to the digital ground for
DVDD and to the analog ground for AVDD . Additional filtering
of the power supplies on the board is recommended.
Voltage Reference
The internal voltage reference of the device has a nominal
value of +1.23V with a 40ppm/°C drift coefficient over the
full temperature range of the converter. It is recommended
that a 0.1F capacitor be placed as close as possible to the
REFIO pin, connected to the analog ground. The REFLO pin
selects the reference. The internal reference can be selected
if REFLO is tied low (ground). If an external reference is
desired, then REFLO should be tied high (the analog supply
voltage) and the external reference driven into REFIO. The
full scale output current of the converter is a function of the
voltage reference used and the value of RSET. IOUT should
be within the 2mA to 22mA range, though operation below
2mA is possible, with performance degradation.
If the internal reference is used, VFSADJ will equal
approximately 1.2V. If an external reference is used, VFSADJ
will equal the external reference. The calculation for IOUT
(Full Scale) is:
IOUT(Full Scale) = (VFSADJ/RSET) X 32.
If the full scale output current is set to 20mA by using the
internal voltage reference (1.23V) and a 1.91k RSET
resistor, then the input coding to output current will resemble
the following:
10
TABLE 1. INPUT CODING vs OUTPUT CURRENT WITH
INTERNAL REFERENCE (1.23V TYP) AND
RSET=1.91K
INPUT CODE (D7-D0)
IOUTA (mA)
IOUTB (mA)
1111 1111
20.6
0
1000 0000
10.3
10.3
0000 0000
0
20.6
Analog Output
IOUTA and IOUTB are complementary current outputs. The
sum of the two currents is always equal to the full scale
output current minus one LSB. If single ended use is
desired, a load resistor can be used to convert the output
current to a voltage. It is recommended that the unused
output be either grounded or equally terminated. The voltage
developed at the output must not violate the output voltage
compliance range of -1.0V to 1.25V. ROUT (the impedance
loading each current output) should be chosen so that the
desired output voltage is produced in conjunction with the
output full scale current. If a known line impedance is to be
driven, then the output load resistor should be chosen to
match this impedance. The output voltage equation is:
VOUT = IOUT X ROUT.
The most effective method for reducing the power
consumption is to reduce the analog output current, which
dominates the supply current. The maximum recommended
output current is 20mA.
Differential Output
IOUTA and IOUTB can be used in a differential-to-singleended arrangement to achieve better harmonic rejection.
With RDIFF= 50and RLOAD=50, the circuit in Figure 6
will provide a 500mV (-2.5dBm) signal at the output of the
transformer if the full scale output current of the DAC is set
to 20mA (used for the electrical specifications table). Values
of RDIFF= 100and RLOAD=50 were used for the typical
performance curves to increase the output power and the
dynamic range. The center tap in Figure 6 must be
grounded.
In the circuit in Figure 7, the user is left with the option to
ground or float the center tap. The DC voltage that will exist
at either IOUTA or IOUTB if the center tap is floating is
IOUTDC x (RA//RB) V because RDIFF is DC shorted by the
transformer. If the center tap is grounded, the DC voltage is
0V. Recommended values for the circuit in Figure 7 are
RA=RB=50, RDIFF=100, assuming RLOAD=50. The
performance of Figure 6 and Figure 7 is basically the same,
however leaving the center tap of Figure 7 floating allows the
circuit to find a more balanced virtual ground, theoretically
improving the even order harmonic rejection, but likely
reducing the signal swing available due to the output voltage
compliance range limitations.
FN6018.1
February 2002
ISL5629
Propagation Delay
REQ = 0.5 x (RLOAD // RDIFF)
AT EACH OUTPUT
OUTA
RDIFF
ISL5629
The converter requires two clock rising edges for data to be
represented at the output. Each rising edge of the clock
captures the present data word and outputs the previous
data. The propagation delay is therefore 1/CLK, plus <2ns of
processing. See Figure 8.
VOUT = (2 x OUTA x REQ)V
1:1
RLOAD
OUTB
Test Service
Intersil offers customer-specific testing of converters with a
service called Testdrive. To submit a request, fill out the
Testdrive form at www.intersil.com/testdrive. Or, send a
request to the technical support center.
RLOAD REPRESENTS THE
LOAD SEEN BY THE TRANSFORMER
FIGURE 6. OUTPUT LOADING FOR DATASHEET
MEASUREMENTS
REQ = 0.5 x (RLOAD // RDIFF// RA), WHERE RA=RB
AT EACH OUTPUT
RA
OUTA
VOUT = (2 x OUTA x REQ)V
RDIFF
ISL5629
OUTB
RLOAD
RB
RLOAD REPRESENTS THE
LOAD SEEN BY THE TRANSFORMER
FIGURE 7. ALTERNATIVE OUTPUT LOADING
Timing Diagram
tPW2
tPW1
50%
CLK
tSU
tSU
tHLD
D7-D0
W0
tSU
tHLD
tHLD
W1
W2
W3
tPD
tPD
OUTPUT=W0
IOUT
OUTPUT=W-1
OUTPUT=W1
FIGURE 8. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
11
FN6018.1
February 2002
ISL5629
Thin Plastic Quad Flatpack Packages (LQFP)
D
Q48.7x7A (JEDEC MS-026BBC ISSUE B)
48 LEAD THIN PLASTIC QUAD FLATPACK PACKAGE
D1
-D-
INCHES
SYMBOL
-A-
-B-
E E1
e
PIN 1
SEATING
A PLANE
-H-
0.08
0.003
-C-
MIN
MAX
MILLIMETERS
MIN
MAX
NOTES
A
-
0.062
-
1.60
-
A1
0.002
0.005
0.05
0.15
-
A2
0.054
0.057
1.35
1.45
-
b
0.007
0.010
0.17
0.27
6
b1
0.007
0.009
0.17
0.23
-
D
0.350
0.358
8.90
9.10
3
D1
0.272
0.280
6.90
7.10
4, 5
E
0.350
0.358
8.90
9.10
3
E1
0.272
0.280
6.90
7.10
4, 5
L
0.018
0.029
0.45
0.75
-
N
48
48
7
e
0.020 BSC
0.50 BSC
Rev. 2 1/99
NOTES:
1. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
2. All dimensions and tolerances per ANSI Y14.5M-1982.
0.08
0.003 M
C A-B S
11o-13o
0.020
0.008 MIN
b
4. Dimensions D1 and E1 to be determined at datum plane
-H- .
0.09/0.16
A2 A1 0.004/0.006
GAGE
PLANE
BASE METAL
WITH PLATING
L
0o-7o
3. Dimensions D and E to be determined at seating plane -C- .
b1
0o MIN
0.25
0.010
D S
11o-13o
0.09/0.20
0.004/0.008
5. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is 0.25mm (0.010 inch) per side.
6. Dimension b does not include dambar protrusion. Allowable
dambar protrusion shall not cause the lead width to exceed
the maximum b dimension by more than 0.08mm (0.003
inch).
7. “N” is the number of terminal positions.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
12
FN6018.1
February 2002
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