DATASHEET

HI1177
TM
Data Sheet
January 1999
File Number
4114.2
8-Bit, 40MSPS, 2-Channel D/A Converter
Features
The HI1177 is a dual 8-bit CMOS digital-to-analog converter.
It has input/output equivalent to 2 channels of Y and C for
video use or I and Q for modulators.
• Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-Bit
The HI1177 is available in the industrial temperature range
and is supplied in a 32 lead plastic metric quad flatpack
(MQFP) package.
Ordering Information
PART
NUMBER
HI1177JCQ
• YC 2-Channel Input/Output
• Differential Linearity Error. . . . . . . . . . . . . . . . . . ±0.3 LSB
• Low Power Consumption . . . . . . . . . . . . . . . . . . . .160mW
(200Ω Load for 2VP-P Output)
• Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . +5V Single
TEMP.
RANGE (oC)
PACKAGE
-40 to 85
• Maximum Conversion Speed . . . . . . . . . . . . . . . . . 40MHz
32 Ld MQFP
PKG. NO.
Q32.7x7-S
• Power-Down Mode
• Low Glitch Noise
• Direct Replacement for Sony CXD1177
Pinout
Applications
• YC Video
VREF
CO
YO
• I/Q Modulation
CO
VG
YO
DVDD
AVDD
HI1177
(MQFP)
TOP VIEW
• Digital TV
• Wireless Transmitters
21
DVSS
Y4
5
20
CCK
Y5
6
19
YCK
Y6
7
18
CE
Y7
8
17
9 10 11 12 13 14 15 16
3-1
IREF
BLK
C7
C6
VB
4
C5
22
Y3
C4
AVSS
3
C3
23
Y2
C2
32 31 30 29 28 27 26 25
24
2
C1
1
Y1
C0
Y0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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HI1177
Functional Block Diagram
(LSB) Y0
1
Y1
2
Y2
3
Y3
4
Y4
5
Y5
6
Y6
7
Y7
8
(LSB) C0
9
C1
10
C2
11
C3
12
C4
13
C5
14
C6
15
2 LSBs
CURRENT
CELLS
32
DVDD
31
AVDD
28
Y0
29
Y0
19
YCK
23
AVSS
21
DVSS
26
C0
27
C0
20
CCK
30
VG
25
VREF
CURRENT CELLS
(FOR FULL SCALE)
24
IREF
BIAS VOLTAGE
GENERATOR
22
VB
DECODER
6 MSBs
CURRENT
CELLS
LATCHES
C7
DECODER
CLOCK
GENERATOR
2 LSBs
CURRENT
CELLS
DECODER
6 MSBs
CURRENT
CELLS
LATCHES
DECODER
CLOCK
GENERATOR
16
-
+
BLK
17
CE
18
Pin Descriptions
NUMBER
SYMBOL
1 to 8
Y0 to Y7
9 to 16
C0 to C7
EQUIVALENT CIRCUIT
DVDD
DESCRIPTION
Digital Input.
1
16
DVSS
17
BLK
DVDD
17
DVSS
3-2
Blanking Pin. No signal at “H” (Output 0V).
Output condition at “L”.
HI1177
Pin Descriptions
NUMBER
SYMBOL
22
VB
(Continued)
EQUIVALENT CIRCUIT
DESCRIPTION
Connect a capacitor of about 0.1µF.
DVDD
DVDD
22
DVSS
19
YCK
20
CLK
Clock Pin. Moreover all input pins are
TTL-CMOS compatible.
DVDD
+
19
-
20
DVSS
21
DVSS
Digital GND.
23
AVSS
Analog GND.
18
CE
Chip Enable Pin. No signal (Output 0V) at “H”
and minimizes power consumption.
DVDD
18
DVSS
24
IREF
25
VREF
30
VG
31
AVDD
AVDD
AVDD
+
24
Connect a resistance 16 times “16R” that of
output resistance value “R”.
Set full scale output value.
Connect a capacitor of about 0.1µF.
AVDD
AVSS
25
Analog VDD .
AVDD
30
AVSS
AVSS
27
CO
29
YO
26
CO
28
YO
AVDD
Current Output Pin. Voltage output can be
obtained by connecting a resistance.
Inverted Current Output Pin. Normally
dropped to analog GND.
27
29
AVSS
AVDD
26
28
AVSS
32
DVDD
Digital VDD .
3-3
HI1177
Absolute Maximum Ratings
TA = 25oC
Thermal Information
Thermal Resistance (Typical, Note 7)
θJA (oC/W)
MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
122
Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(MQFP - Lead Tips Only)
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V
Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD to VSS
Output Current (For Each Channel), lOUT . . . . . . . . . . 0mA to 15mA
Operating Conditions
Supply Voltage
AVDD, AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.75V to 5.25V
DVDD, DVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.75V to 5.25V
Reference Input Voltage, VREF . . . . . . . . . . . . . . . . . . . . . . . . . 2.0V
Clock Pulse Width
tPW1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5ns (Min)
tPW0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5ns (Min)
Temperature Range, TOPR . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
fCLK = 40MHz, VDD = 5V, ROUT = 200Ω, VREF = 2.0V, TA = 25oC
SYMBOL
Resolution
TEST
LEVEL
OR NOTES
TEST CONDITIONS
MIN
TYP
MAX
UNITS
n
-
8
-
bit
fMAX
40
-
-
MHz
Linearity Error
EL
-2.5
-
2.5
LSB
Differential Linearity Error
ED
-0.3
-
0.3
LSB
Full Scale Output Voltage
VFS
1.9
2.0
2.2
V
Full Scale Output Ratio
FSR
0
1.5
3
%
Maximum Conversion Speed
Note 1
Full Scale Output Current
IFS
-
10
15
mA
Offset Output Voltage
VOS
-
-
1
mV
Power Supply Current
IDD
-
-
32
mA
Digital Input
Current
High Level
IIH
-
-
5
µA
Low Level
IIL
-5
-
-
µA
Setup Time
tS
5
-
-
ns
Hold Time
tH
10
-
-
ns
Propagation Delay Time
tPD
-
10
-
ns
Glitch Energy
GE
ROUT = 75Ω
-
30
-
pV-s
Cross Talk
CT
1MHz Sin Wave Output
-
57
-
dB
14.3MHz, at Color Bar Data Input
NOTE:
Full-scale voltage of channel
1. Full scale output ratio = ------------------------------------------------------------------------------------------------------------------------------- ( – 1 ) x100(%) .
Average of the full-scale voltage of the channels
I/O Correspondence Table
(Output Full Scale Voltage: 2V)
INPUT CODE
MSB
1
OUTPUT VOLTAGE
LSB
1
1
1
1
1
1
1
2.0V
0
0
0
0
1.0V
0
0
0
0
0V
•
•
•
1
0
0
0
•
•
•
0
3-4
0
0
0
HI1177
Timing Diagram
tPW1
tPW0
CLK
tS
tS
tS
tHL
tHL
tHL
DATA
tPD
100%
D/AOUT
50%
tPD
tPD
0%
FIGURE 1.
Test Circuits
Y0 ~ Y7
1~8
8-BIT
COUNTER
WITH
LATCH
C0 ~ C7
9 ~ 18
Y0 29
200
OSCILLOSCOPE
AVSS
C0 27
200
17
BLK
18
CE
22
VB
AVSS
0.1µ
VG 30
0.1µ
DVSS
CLK
40MHz
SQUARE
WAVE
AVDD
19
YCK
20
CCK
VREF 25
1K
IREF 24
3.3K
FIGURE 2. MAXIMUM CONVERSION
3-5
AVSS
HI1177
Test Circuits
(Continued)
Y0 29
Y0 ~ Y7
1~8
8-BIT
COUNTER
WITH
LATCH
75
OSCILLOSCOPE
AVSS
C0 ~ C7
9 ~ 18
C0 27
75
DELAY
CONTROLLER
17
BLK
18
CE
22
VB
AVSS
0.1µ
AVDD
VG 30
0.1µ
DVSS
CLK
1MHz
SQUARE
WAVE
DELAY
CONTROLLER
19
YCK
20
CCK
VREF 25
1K
IREF 24
1.2K
AVSS
FIGURE 3. SETUP HOLD TIME AND GLITCH ENERGY
ALL “1”
Y0 29
Y0 ~ Y7
1~8
DIGITAL
WAVEFORM
GENERATOR
200
SPECTRUM
ANALYZER
AVSS
C0 ~ C7
9 ~ 18
C0 27
200
17
BLK
18
CE
22
VB
AVSS
0.1µ
VG 30
0.1µ
DVSS
CLK
40MHz
SQUARE
WAVE
AVDD
19
YCK
20
CCK
VREF 25
1K
IREF 24
3.3K
AVSS
FIGURE 4. CROSSTALK
Y0 ~ Y7
1~8
Y0 29
200
CONTROLLER
C0 ~ C7
9 ~ 18
AVSS
DVM
C0 27
200
17
BLK
18
CE
22
VB
AVSS
0.1µ
VG 30
0.1µ
DVSS
CLK
40MHz
SQUARE
WAVE
AVDD
19
YCK
20
CCK
VREF 25
1K
IREF 24
3.3K
FIGURE 5. DC CHARACTERISTICS
3-6
AVSS
HI1177
Test Circuits
(Continued)
Y0 29
Y0 ~ Y7
1~8
200
FREQUENCY
DEMULTIPLIER
OSCILLOSCOPE
AVSS
C0 ~ C7
9 ~ 18
C0 27
200
17
BLK
18
CE
22
VB
19
YCK
20
CCK
AVSS
0.1µ
AVDD
VG 30
0.1µ
DVSS
CLK
10MHz
SQUARE
WAVE
VREF 25
1K
IREF 24
3.3K
AVSS
FIGURE 6. PROPAGATION DELAY TIME
VFS, OUTPUT FULL SCALE VOLTAGE (V)
Typical Performance Curves
200
2
100
1
VDD = 5.0V
R = 200Ω
16R = 3.3kΩ
TA = 25oC
100
OUTPUT RESISTANCE (Ω)
1
2
VREF , REFERENCE VOLTAGE (V)
FIGURE 7. OUTPUT FULL SCALE VOLTAGE vs REFERENCE
VOLTAGE
200
FIGURE 8. GLITCH ENERGY vs OUTPUT RESISTANCE
CROSSTALK (dB)
OUTPUT FULL SCALE VOLTAGE (V)
60
2.0
1.9
VDD = 5V
VREF = 2V
R = 200Ω
16R = 3.3kΩ
40
0
-25
0
25
50
75
AMBIENT TEMPERATURE (oC)
100
FIGURE 9. OUTPUT FULL SCALE VOLTAGE vs AMBIENT
TEMPERATURE
3-7
50
100K
1M
10M
OUTPUT FREQUENCY (Hz)
FIGURE 10. CROSSTALK vs OUTPUT FREQUENCY
HI1177
Application Circuit
Y OUT
C OUT
200
200
AVSS
DVDD
AVSS
AVDD
AVDD
AVSS
0.1µF
32
(LSB)
31
30
29
28
27
26
1K
AVSS
25
1
24
2
23
3
22
4
21
5
20
6
19
7
18
3.3K
AVSS
0.1µF
Y IN
DVSS
CLOCK
(MSB)
8
17
9
10
11
12
13
14
15
(LSB)
16
DVSS
(MSB)
C IN
FIGURE 11.
Operation
• How to select the output resistance:
- The HI1177 is a D/A converter of the current output type.
To obtain the output voltage connect the resistance to IO
pin (Y0, C0). For specifications we have:
Output full scale voltage
Output full scale current
VFS = less than 2V
IFS = less than 15mA
- Calculate the output resistance value from the relation
of VFS = IFS X R. Also, 16 times resistance of the output
resistance is connected to reference current pin IREF. In
some cases, however, this turns out to be a value that
does not actually exist. In such a case a value close to it
can be used as a substitute. Here please note that VFS
becomes VFS = VREF X 16R/R’. R is the resistance
connected to IO while R’ is connected to IREF.
Increasing the resistance value can curb power
consumption. On the other hand glitch energy and data
settling time will inversely increase. Set the most
suitable value according to the desired application.
• Phase relation between data and clock:
- To obtain the expected performance as a D/A converter,
it is necessary to set properly the phase relation
between data and clock applied from the exterior. Be
sure to satisfy the provisions of the set up time (tS) and
hold time (tH) as stipulated in the Electrical
Characteristics.
• VDD, VSS :
- To reduce noise effects separate analog and digital
systems in the device periphery. For VDD pins, both
digital and analog, bypass respective GNDs by using a
ceramic capacitor of about 0.1µF, as close as possible
to the pin.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
3-8
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