CXD1171M 8-bit 40MSPS High Speed D/A Converter Description The CXD1171M is a 8-bit 40 MHz high speed D/A converter. The adoption of a current output system reduces power consumption to 80 mW (200 Ω load at 2 Vp-p output). This IC is suitable for digital TV and graphic display applications. Features • Resolution 8-bit • Max. conversion speed 40MSPS • Non linearity error within ±0.25 LSB • Low glitch noise • TTL CMOS compatible input • +5 V single power supply • Low power consumption 80 mW (200 Ω load at 2 Vp-p output) Function 8-bit 40 MHz D/A converter Structure Silicon gate CMOS IC 24 pin SOP (Plastic) Absolute Maximum Ratings (Ta=25 °C) • Supply voltage AVDD, DVDD 7 V • Input voltage (All pins) VIN VDD +0.5 to VSS –0.5 V • Output current IOUT 15 mA • Storage temperature Tstg –55 to +150 °C Recommended Operating Conditions • Supply voltage AVDD, AVSS 4.75 to 5.25 V V DVDD, DVSS 4.75 to 5.25 • Reference input voltage VREF 2.0 V • Clock pulse width Tpw1,Tpw0 11.2 ns (min) to 1.1 µs (max) • Operating temperature Topr –40 to +85 °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. —1— E89X38F01 CXD1171M Block Diagram and Pin Configuration (LSB) D0 1 24 DVDD D1 2 23 DVDD D2 3 22 AVDD D3 4 DECODER 2LSB'S CURRENT CELLS LATCHES D4 5 D5 6 D6 7 (MSB) D7 8 BLK 9 6MSB'S CURRENT CELLS IO 20 IO 19 AVDD 18 AVDD DECODER 17 VG 16 VREF CURRENT CELLS (FOR FULL SCALE) DVSS 10 BIAS VOLTAGE GENERATOR VB 11 CLK 12 21 CLOCK GENERATOR 15 IREF 14 AVSS 13 DVSS —2— CXD1171M Pin Description and I/O Pins Equivalent Circuit No. Symbol I/O Equivalent circuit Description DVDD Digital input. D0 (LSB) to D7 (MSB) D0 and D1 have a pull-down resistor. 1 1 to 8 D0 to D7 I to 8 DVSS DVDD 9 BLK I Blanking input. This is synchronized with the clock signal. No signal at “H” (Output 0 V). Output condition at “L”. 9 DVSS DVDD DVDD 11 VB O Connect a capacitor of about 0.1 µF. 11 DVSS DVDD 12 CLK I Clock input. 12 DVSS 10, 13 14 DVSS AVSS — — Digital ground. Analog ground. —3— CXD1171M No. 15 Symbol IREF I/O Equivalent circuit AVDD O Description AVDD Connect a resistor “RIR” 16 times against the output resistance value “ROUT” connected to Pin 20 (IO). 15 AVDD 16 VREF I AVSS AVDD 16 17 AVSS 17 VG 18, 19, 22 AVDD Set full-scale output value. O AVSS — Connect a capacitor of about 0.1 µF. Analog power supply. AVDD 20 IO 20 AVSS O 21 Current output. Voltage output can be obtained by connecting a resistance. AVDD Inverted current output. Normally connected to analog GND. 21 IO AVSS 23, 24 DVDD — Digital power supply. —4— CXD1171M (FCLK=40 MHz, AVDD=DVDD=5 V, ROUT=200 Ω, VREF=2.0 V, Ta=25 °C) Electrical Characteristics Resolution Item Symbol n Conversion speed FCLK Integral non-linearity error Differential non-linearity error Output full-scale voltage Output full-scale current Output offset voltage Glitch energy Supply current Analog input resistance Input capacitance EL ED VFS IFS VOS GE IDD RIN CI VIH VIL Digital input voltage Digital input current IIH IIL Setup time Hold time Propagation delay time tS tH tPD Measurement conditions AVDD=DVDD=4.75 to 5.25 V Ta=–40 to 85 °C Endpoint When D0 to D7=00000000 input ROUT=75 Ω When 14.3 MHz color bar data input VREF } Max. Unit bit 0.5 40 MSPS –0.5 –0.25 1.9 1.3 0.25 2.1 15 1 LSB LSB V mA mV pV · s mA MΩ pF 13 1 Typ. 8 2.0 10 30 14.5 16 9 AVDD=DVDD=4.75 to 5.25 V Ta=–20 to +75 °C AVDD=DVDD=4.75 to 5.25 V D0, D1 Ta=–20 to +75 °C D2 to 7, BLK, CLK ROUT=75 Ω ROUT=75 Ω 2.4 –5 0.8 240 –5 5 5 10 10 Electrical Characteristics Measurement Circuit Analog Input Resistance Digital Input Current Min. Measurement Circuit +5.25V AVDD, DVDD A CXD1171M V AVSS, DVSS —5— V µA ns ns ns CXD1171M Maximum Conversion Speed Measurement Circuit OSCILLOSCOPE IO 20 1 D0 (LSB) 8bit COUNTER with LATCH 200 2 • • • 8 D7 AVDD VG 17 9 BLK 0.1µ 0.1µ VREF 16 1k 2V 11 VB CLK 40MHZ SQUARE WAVE AVss 12 CLK IREF 15 3.3k DC Characteristics Measurement Circuit 1 CONTROLLER DVM IO 20 D0 (LSB) 200 2 • •• 8 D7 AVDD VG 17 9 BLK 0.1µ 0.1µ VREF 16 CLK 40MHZ SQUARE WAVE 1k 2V 11 VB AVss 12 CLK IREF 15 3.3k Propagation Delay Time Measurement Circuit OSCILLOSCOPE IO 20 1 D0 (LSB) 200 2 • •• 8 D7 AVDD VG 17 CLK 10MHZ SQUARE WAVE Setup Time Hold Time Glitch Energy } 9 BLK FREQUENCY DEMULTIPLIER 0.1µ 0.1µ VREF 16 1k 11 VB AVss 12 CLK IREF 15 3.3k measurement Circuit 8bit COUNTER with LATCH IO 20 1 D0 (LSB) OSCILLOSCOPE 75 • •• 2 8 D7 AVDD VG 17 DELAY CONTROLLER CLK 1MHZ SQUARE WAVE DELAY CONTROLLER 9 BLK 0.1µ 0.1µ VREF 16 11 VB 1k 1V AVss 12 CLK IREF 15 1.2k —6— CXD1171M Operation tPW1 tPW0 Timing Chart CLK AA AAAAAAA AA AA AA AAA AA AAAAAAA tS tH tS tH 2V tS tH DATA tPD D/A OUT 100% 50% tPD tPD 0% I/O Chart (when full-scale output voltage at 2.00 V) Input code MSB LSB 11111111 : 10000000 : 00000000 Output voltage 2.0 V 1.0 V 0V Application Circuit DVDD (LSB) 1 24 2 23 3 22 4 21 5 20 AVDD 8bit DIGITAL INPUT AGND D/A OUT 200 6 19 7 18 8 17 9 16 10 15 11 14 12 13 0.1µ 2V 0.1µ 1k 3.3k DGND Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. —7— CXD1171M Notes on Operation • How to select the output resistance The CXD1171M is a D/A converter of the current output type. To obtain the output voltage connect the resistance to the current output pin IO. For specifications we have: Output full scale voltage VFS = 1.9 to 2.1 [V] Output full scale current IFS = less than 15 [mA] Calculate the output resistance value from the relation of VFS = IFS × ROUT. Also, 16 times resistance of the output resistance is connected to reference current pin IREF. In some cases, however, this turns out to be a value that does not actually exist. In such a case a value close to it can be used as a substitute. Here please note that VFS becomes VFS = VREF × 16ROUT/RIR. ROUT is the resistance connected to IO while RIR is connected to IREF. Increasing the resistance value can curb power consumption. On the other hand glitch energy and data settling time will inversely increase. Set the most suitable value according to the desired application. • Phase relation between data and clock To obtain the expected performance as a D/A converter, it is necessary to set properly the phase relation between data and clock applied from the exterior. Be sure to satisfy the provisions of the setup time (tS) and hold time (tH) as stipulated in the Electrical Characteristics. • Power supply and ground To reduce noise effects separate analog and digital systems in the device periphery. For the power supply pins, both digital and analog, bypass respective grounds by using a ceramic capacitor of about 0.1 µF, as close as possible to the pin. • Latch up AVDD and DVDD have to be common at the PCB power supply source. This is to prevent latch up due to voltage difference between AVDD and DVDD pins when power supply is turned ON. • IO pin The IO pin is the inverted current output pin described in the Pin Description. The sum of the currents output from the IO pin and the IO pin becomes the constant value for any input data. However, the performances such as the linearity error of the IO pin output current is not guaranteed. —8— CXD1171M Latch Up Prevention The CXD1171M is a CMOS IC which requires latch up precautions. Latch up is mainly generated by the lag in the voltage rising time of AVDD (Pins 18, 19 and 22) and DVDD (Pins 23 and 24), when power supply is ON. 1. Correct usage a. When analog and digital supplies are from different sources DVDD AVDD 23 24 22 18 19 AVDD +5V +5V DVDD CXD1171M C AVSS 14 C DIGITAL IC DVSS 10 13 AVSS DVSS b. When analog and digital supplies are from a common source (i) DVDD 18 19 22 23 AVDD 24 DVDD +5V CXD1171M C AVSS DVSS 14 10 13 AVSS C DIGITAL IC C DIGITAL IC DVSS (ii) DVDD 18 19 22 23 AVDD 24 DVDD +5V C CXD1171M AVSS 14 DVSS 10 13 AVSS DVSS —9— CXD1171M 2. Example when latch up easily occurs a. When analog and digital supplies are from different sources DVDD AVDD 18 19 23 24 22 AVDD +5V +5V DVDD CXD1171M C C AVSS DVSS 13 10 14 AVSS DIGITAL IC DVSS b. When analog and digital supplies are from common source (i) DVDD AVDD 23 24 22 18 19 AVDD DVDD +5V C CXD1171M C AVSS DVSS 10 13 14 AVSS DIGITAL IC DVSS (ii) DVDD AVDD 23 24 22 18 19 AVDD DVDD +5V C CXD1171M AVSS AVSS 14 DVSS 10 13 DVSS —10— DIGITAL IC CXD1171M 2.0 Glitch energy GE [pV · s] Output full scale voltage VFS [V] 200 1.0 AVDD=DVDD=5.0V ROUT=200Ω RIR=3.3kΩ Ta=25°C 0 1.0 Output full-scale voltage VFS [V] 1.9 AVDD=DVDD= 5.0V VREF=2.0V ROUT=200Ω RIR=3.3kΩ 0 25 50 100 200 Output resistance ROUT [Ω] Output resistance vs. Glitch energy 2.0 0 100 0 2.0 Reference voltage VREF [V] Reference voltage vs. Output full scale voltage –25 AVDD=DVDD=5.0V VREF=2.0V RIR ≈ 16ROUT Ta=25°C 75 Ambient temperature Ta [°C] Ambient temperature vs. Output full scale voltage —11— CXD1171M Unit : mm 24PIN SOP (PLASTIC) + 0.4 1.85 – 0.15 + 0.4 15.0 – 0.1 0.15 24 0.24 6.9 + 0.2 0.1 – 0.05 1.27 + 0.1 0.2 – 0.05 0.5 ± 0.2 12 1 0.45 ± 0.1 7.9 ± 0.4 13 + 0.3 5.3 – 0.1 Package Outline M PACKAGE STRUCTURE MOLDING COMPOUND EPOXY RESIN SONY CODE SOP-24P-L01 LEAD TREATMENT SOLDER PLATING EIAJ CODE SOP024-P-0300 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.3g JEDEC CODE —12—