DATASHEET

12-Bit, 10-Bit and 8-Bit, 1MSPS SAR ADCs
ISL26712, ISL26710, ISL26708
Features
The ISL26712, ISL26710, ISL26708 are 12-bit, 10-bit and 8-bit,
1MSPS sampling SAR-type ADCs featuring excellent linearity over
supply and temperature variations. The robust, fully-differential
input offers high impedance to minimize errors due to leakage
currents, and the specified measurement accuracy is maintained
with input signals up to the supply rails.
• Differential Input
The reference accepts inputs from 0.1V to 2.2V for 3V operation
and 0.1V to 3.5V for 5V operation, providing design flexibility in a
wide variety of applications. The ISL26712/10/08 also features
up to 8kV Human Body Model ESD survivability.
• Low Operating Current
The serial digital interface is SPI compatible and is easily
interfaced to popular FPGAs and microcontrollers. Power
dissipation is 8.5mW at a sampling rate of 1MSPS, and just 5µW
between conversions utilizing Auto Power-Down mode (with a 5V
supply), making the ISL26712/10/08 excellent solutions for
remote industrial sensors and battery-powered instruments.
• Power-down Current between Conversions: 1µA
The ISL26712/10/08 are available in an 8 Ld TDFN or an SOT-23
package, and are specified for operation over the Industrial
temperature range (–40°C to +85°C).
• Available in SOT-23 Package
• Simple SPI-compatible Serial Digital Interface
• Guaranteed No Missing Codes
• 1MHz Sampling Rate
• 3V or 5V Operation
- 1.25mA at 1MSPS with 3V Supplies
- 1.70mA at 1MSPS with 5V Supplies
• Excellent Differential Non-Linearity
• Low THD: -83dB (typ)
• Pb-Free (RoHS Compliant)
• Available in TDFN Package (3x3mm)
Applications
• Remote Data Acquisition
• Battery Operated Systems
• Industrial Process Control
• Energy Measurement
• Data Acquisition Systems
• Pressure Sensors
• Flow Controllers
1.0
0.8
VDD
0.6
0.4
AIN+
SAR
LOGIC
AIN–
SERIAL
INTERFACE
SCLK
SDATA
CS
DNL (LSB)
DAC
VREF
0.2
0.0
-0.2
DAC
-0.4
VREF
-0.6
GND
-0.8
-1.0
0
1024
2048
3072
4096
CODE
FIGURE 1. BLOCK DIAGRAM
September 5, 2012
FN7999.3
1
FIGURE 2. ISL26712 DIFFERENTIAL LINEARITY ERROR vs CODE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL26712, ISL26710, ISL26708
Typical Connection Diagram
+3V/5V
SUPPLY
VREF
+
VREF
0.1µF
+
10µF
VDD
REF P-P
AIN+
SCLK
REF P-P
AIN–
SDATA
GND
CS
µP/µC
SERIAL INTERFACE
Pin Configurations
Pin Description
ISL26712/10/08
(8 LD TDFN)
TOP VIEW
VREF
ISL26712/10/08
PIN
NAME
PIN
NUMBER
(TDFN)
PIN
NUMBER
(SOT-23)
DESCRIPTION
1
8
VDD
AIN+ 2
7
SCLK
VDD
8
1
Supply voltage, +2.7V to 5.25V.
AIN- 3
6
SDATA
SCLK
7
2
4
5
CS
Serial clock input. Controls digital
I/O timing and clocks the
conversion.
SDATA
6
3
Digital conversion output.
CS
5
4
Chip select input. Generally controls
the start of a conversion though not
always the sampling signal.
GND
4
5
Ground
AIN–
3
6
Negative analog input.
AIN+
2
7
Positive analog input.
VREF
1
8
Reference voltage.
GND
ISL26712/10/08
(8 LD SOT-23)
TOP VIEW
VDD
1
8
VREF
SCLK
2
7
AIN+
SDATA
3
6
AIN-
CS
4
5
GND
Pin-Compatible Family
2
PART NUMBER
RESOLUTION
(Bits)
ISL26712
12
ISL26710
10
ISL26708
8
FN7999.3
September 5, 2012
ISL26712, ISL26710, ISL26708
Ordering Information
PART NUMBER
(Note 4)
PART
MARKING
VDD RANGE
(V)
TEMP RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL26712IRTZ (Note 3)
6712
2.7 to 5.25
-40 to +85
8 Ld TDFN
L8.3x3I
ISL26712IRTZ-T (Notes 1, 3)
6712
2.7 to 5.25
-40 to +85
8 Ld TDFN
L8.3x3I
ISL26712IRTZ-T7A (Notes 1, 3)
6712
2.7 to 5.25
-40 to +85
8 Ld TDFN
L8.3x3I
ISL26710IRTZ (Note 3)
6710
2.7 to 5.25
-40 to +85
8 Ld TDFN
L8.3x3I
ISL26710IRTZ-T (Notes 1, 3)
6710
2.7 to 5.25
-40 to +85
8 Ld TDFN
L8.3x3I
ISL26710IRTZ-T7A (Notes 1, 3)
6710
2.7 to 5.25
-40 to +85
8 Ld TDFN
L8.3x3I
ISL26708IRTZ (Note 3)
6708
2.7 to 5.25
-40 to +85
8 Ld TDFN
L8.3x3I
ISL26708IRTZ-T (Notes 1, 3)
6708
2.7 to 5.25
-40 to +85
8 Ld TDFN
L8.3x3I
ISL26712IHZ-T (Notes 1, 2)
6712 (Note 5)
2.7 to 5.25
-40 to +85
8 Ld SOT-23
P8.064
ISL26712IHZ-T7A (Notes 1, 2)
6712 (Note 5)
2.7 to 5.25
-40 to +85
8 Ld SOT-23
P8.064
ISL26710IHZ-T (Notes 1, 2)
6710 (Note 5)
2.7 to 5.25
-40 to +85
8 Ld SOT-23
P8.064
ISL26710IHZ-T7A (Notes 1, 2)
6710 (Note 5)
2.7 to 5.25
-40 to +85
8 Ld SOT-23
P8.064
ISL26708IHZ-T (Notes 1, 2)
6708 (Note 5)
2.7 to 5.25
-40 to +85
8 Ld SOT-23
P8.064
ISL26708IHZ-T7A (Notes 1, 2)
6708 (Note 5)
2.7 to 5.25
-40 to +85
8 Ld SOT-23
P8.064
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pbfree products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. For Moisture Sensitivity Level (MSL), please see device information page fo ISL26712, ISL26710, ISL26708. For more information on MSL please see
techbrief TB363.
5. The part marking is located on the bottom of the part.
3
FN7999.3
September 5, 2012
ISL26712, ISL26710, ISL26708
Table of Contents
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
ADC Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Reference Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Converter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Short Cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ACQUISITION TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power vs Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
13
14
15
17
17
17
17
17
17
Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Signal-to-(Noise + Distortion) Ratio (SINAD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Total Harmonic Distortion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak Harmonic or Spurious Noise (SFDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Intermodulation Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Aperture Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Aperture Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Full Power Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Common-Mode Rejection Ratio (CMRR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Integral Nonlinearity (INL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential Nonlinearity (DNL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Zero-Code Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Positive Gain Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Negative Gain Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Track and Hold Acquisition Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply Rejection Ratio (PSRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
17
17
18
18
18
18
18
18
18
18
18
18
18
18
Application Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Grounding and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Small Outline Transistor Plastic Packages (SOT23-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
P8.064 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
L8.3x3I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4
FN7999.3
September 5, 2012
ISL26712, ISL26710, ISL26708
Absolute Maximum Ratings
Thermal Information
Any Pin to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V
Analog Input to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V
Digital I/O to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V
Digital Input Voltage to GND . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V
Maximum Current In to Any Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
ESD Rating
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 8kV
Machine Model (Tested per JESD22-A115B) . . . . . . . . . . . . . . . . . 400V
Charged Device Model (Tested per JESD22-C101E)
TDFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0kV
SOT-23 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5kV
Latch Up (Tested per JESD78C; Class 2, Level A) . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
8 Ld TDFN Package (Notes 6, 8) . . . . . . . . .
41
6
8 Ld SOT-23 Package (Notes 7, 9). . . . . . . .
135
99
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
6. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
7. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
8. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
9. For θJC, the “case temp” location is taken at the package top center.
Electrical Specifications VDD = +3.0V to +3.6V, FSCLK = 18MHz, FS = 1MSPS, VREF = 2.0V; VDD = +4.75V to +5.25V, FSCLK = 18MHz,
FS = 1MSPS, VREF = 2.5V; VCM = VREF, unless otherwise noted. Typical values are at TA = +25°C. Boldface limits apply over the operating temperature
range, -40°C to +85°C.
ISL26712
SYMBOL
ISL26710
MIN
(Note 10)
TYP
FIN = 100kHz
VDD = +4.75V to +5.25V
70.0
71.4
61.0
61.6
49.0
49.8
dB
FIN = 100kHz
VDD = +3.0V to +3.6V
68.5
70.5
60.7
61.5
49.0
49.8
dB
PARAMETER
TEST CONDITIONS
MAX
MIN
(Note 10) (Note 10)
ISL26708
TYP
MAX
MIN
(Note 10) (Note 10)
TYP
MAX
(Note 10) UNITS
DYNAMIC PERFORMANCE
SINAD Signal-to (Noise +
Distortion) Ratio
THD
Total Harmonic
Distortion
FIN = 100kHz
VDD = +4.75V to +5.25V
-84
-76
-82
-74
-75
-60
dB
FIN = 100kHz
VDD = +3.0V to +3.6V
-84
-74
-82
-72
-73
-60
dB
-87
-76
-82
-76
-68
-60
dB
FIN = 100kHz
VDD = +3.0V to +3.6V
-85
-74
-82
-74
-68
-60
dB
2nd and 3rd order,
FIN = 90kHz, 110kHz
-89
-83
-81
dB
SFDR Spurious Free Dynamic FIN = 100kHz
VDD = +4.75V to +5.25V
Range
IMD
Intermodulation
Distortion
tpd
Aperture Delay
1
1
1
ns
Δtpd
Aperture Jitter
15
15
15
ps
15
15
15
MHz
β3dB Full Power Bandwidth
@ –3dB
DC ACCURACY
N
Resolution
12
INL
Integral Nonlinearity
-1
±0.4
1
-0.5
±0.1
0.5
-0.2
±0.03
0.2
LSB
DNL
Differential Nonlinearity Guaranteed no missing
codes
-0.95
±0.3
0.95
-0.5
±0.1
0.5
-0.2
±0.03
0.2
LSB
-6
±0.2
6
-2.5
±0.2
2.5
-1.25
±0.03
1.25
LSB
OFFSET Zero-Code Error
Zero Volt Differential Input
5
10
8
Bits
FN7999.3
September 5, 2012
ISL26712, ISL26710, ISL26708
Electrical Specifications VDD = +3.0V to +3.6V, FSCLK = 18MHz, FS = 1MSPS, VREF = 2.0V; VDD = +4.75V to +5.25V, FSCLK = 18MHz,
FS = 1MSPS, VREF = 2.5V; VCM = VREF, unless otherwise noted. Typical values are at TA = +25°C. Boldface limits apply over the operating temperature
range, -40°C to +85°C. (Continued)
ISL26712
SYMBOL
GAIN
PARAMETER
Positive Gain Error
TEST CONDITIONS
± REF input range
Negative Gain Error
ISL26710
MAX
MIN
(Note 10) (Note 10)
ISL26708
MIN
(Note 10)
TYP
-2
±0.1
2
-1
±0.1
1
-0.75
±0.04
0.75
LSB
-2
±0.1
2
-1
±0.1
1
-0.75
±0.04
0.75
LSB
TYP
MAX
MIN
(Note 10) (Note 10)
MAX
(Note 10) UNITS
TYP
ANALOG INPUT (Note 11)
|AIN| Full-Scale Input Span
2 x VREF
(AIN+) – (AIN–)
(AIN+) – (AIN–)
(AIN+) – (AIN–)
V
VCM ±VREF/2
VCM ±VREF/2
VCM ±VREF/2
V
VCM± VREF/2
VCM± VREF/2
VCM± VREF/2
V
AIN+, Absolute Input Voltage Range
AIN–,
AIN+
VCM = VREF
AIN–
ILEAK Input DC Leakage
Current
CVIN
Input Capacitance
-1
1
Track/Hold mode
-1
13/5
1
-1
1
µA
13/5
13/5
pF
REFERENCE INPUT
VREF VREF Input Voltage
Range
VDD = 3V (1% tolerance
for specified
performance)
2.0
2.0
2.0
V
VDD = 5V (1% tolerance
for specified
performance)
2.5
2.5
2.5
V
ILEAK DC Leakage Current
CREF
-1
1
VREF Input Capacitance Track/Hold mode
-1
21/18.5
1
-1
21/18.5
1
21/18.5
µA
pF
LOGIC INPUTS
VIH
Input High Voltage
VIL
Input Low Voltage
2.4
2.4
0.8
ILEAK Input Leakage Current
CIN
2.4
-1
1
Input Capacitance
V
0.8
-1
10
1
-1
10
0.8
V
1
µA
10
pF
LOGIC OUTPUTS
VOH
Output High Voltage
ISOURCE = 200µA
VOL
Output Low Voltage
ISINK = 200µA
IOZ
Floating-State Output
Current
COUT
Floating-State
Output Capacitance
VDD - 0.3
VDD - 0.3
VDD - 0.3
0.4
-1
1
0.4
-1
10
1
-1
10
Output Coding
V
0.4
V
1
µA
10
pF
Two’s Complement
CONVERSION RATE
tCONV Conversion Time
FSCLK = 18MHz
888
888
888
ns
tACQ
Acquisition Time
FSCLK = 18MHz
200
200
200
ns
Fmax
Throughput Rate
1000
1000
1000
kSPS
POWER REQUIREMENTS
VDD
Positive Supply Voltage
Range
6
2.7
3.6
2.7
3.6
2.7
3.6
V
4.75
5.25
4.75
5.25
4.75
5.25
V
FN7999.3
September 5, 2012
ISL26712, ISL26710, ISL26708
Electrical Specifications VDD = +3.0V to +3.6V, FSCLK = 18MHz, FS = 1MSPS, VREF = 2.0V; VDD = +4.75V to +5.25V, FSCLK = 18MHz,
FS = 1MSPS, VREF = 2.5V; VCM = VREF, unless otherwise noted. Typical values are at TA = +25°C. Boldface limits apply over the operating temperature
range, -40°C to +85°C. (Continued)
ISL26712
SYMBOL
IDD
PARAMETER
TEST CONDITIONS
MIN
(Note 10)
TYP
ISL26710
MAX
MIN
(Note 10) (Note 10)
TYP
ISL26708
MAX
MIN
(Note 10) (Note 10)
TYP
MAX
(Note 10) UNITS
Positive Supply Input Current
Static
Dynamic
1
1
1
µA
3V
1250
1250
1250
µA
5V
1700
1700
1700
µA
VDD = 3V
3
3
3
µW
VDD = 5V
5
5
5
µW
VDD = 3V, fsmpl = 1MSPS
3.75
3.75
3.75
mW
VDD = 5V, fsmpl = 1MSPS
8.50
8.50
8.50
mW
Power Dissipation
Static Mode
Dynamic
NOTES:
10. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
11. The absolute voltage applied to each analog input must be between GND and VDD to guarantee datasheet performance.
Timing Specifications
VDD = 3.0V to 3.6V, fSCLK = 18MHz, fS = 1MSPS, VREF = 2.0V; VDD = 4.75V to 5.25V, fSCLK = 18MHz,
fS = 1MSPS, VREF = 2.5V; VCM = VREF unless otherwise noted. Boldface limits apply over the operating temperature range, -40°C to +85°C.
PARAMETER
(Note 12)
SYMBOL
TEST CONDITIONS
MIN
(Note 10)
MAX
(Note 10)
UNITS
18
MHz
fSCLK
Clock Frequency
tSCLK
Clock Period
tACQ
Acquisition Time (Note 13)
tCONV
Conversion Time
tCSW
CS Pulse Width
10
ns
tCSS
CS Falling Edge to SCLK Falling Edge Setup Time
10
ns
tCDV
CS Falling Edge to SDATA Valid
20
ns
tCLKDV
SCLK Falling Edge to SDATA Valid
40
ns
tSDH
SCLK Falling Edge to SDATA Hold
tSW
SCLK Pulse Width
tDISABLE
tQUIET
0.01
TYP
55
ns
ns
888
CSB Rising Edge to SDATA Disable Time
(Note 14)
10
Extrapolated back to true bus relinquish
Quiet Time Before Sample
ns
ns
0.4 x tSCLK
0.6 x tSCLK
ns
10
35
ns
60
ns
NOTES:
12. Limits established by characterization and are not production tested.
13. See “ACQUISITION TIME” on page 17.
14. During characterization, tDISABLE is measured from the release point with a 10pF load (see Figure 4).
7
FN7999.3
September 5, 2012
ISL26712, ISL26710, ISL26708
tCSW
tCONV
tCSS
1
3
2
4
tCDV
12 BIT SDATA
5
6
7
8
tCLKDV
0
0
0
0
D11
9
10
11
12
13
14
15
D10
D9
D8
16
tACQ
tSW
tDISABLE
D7
D6
D5
D4
D3
D2
HI-Z
D1
D0
tQUIET
tACQ
10 BIT SDATA
0
0
0
0
D9
D8
D7
D6
D5
D4
D3
D2
HI-Z
D1
D0
tACQ
8 BIT SDATA
0
0
0
0
D7
D6
D5
D4
D3
D2
HI-Z
D1
D0
FIGURE 3. SERIAL INTERFACE TIMING DIAGRAM
VDD
RL
2.85k
OUTPUT PIN
CL
10pF
FIGURE 4. EQUIVALENT LOAD CIRCUIT
8
FN7999.3
September 5, 2012
ISL26712, ISL26710, ISL26708
Typical Performance Characteristics
0
75
8192-POINT FFT
fSAMPLE = 1MSPS
fIN = 95.2kHz
SINAD = 72.0dB
THD = -91dB
SFDR = 93dB
5.25V
-20
4.75V
3.6V
2.7V
-40
AMPLITUDE (dBFS)
SINAD (dBc)
70
65
-60
-80
-100
60
-120
55
-140
10
100
INPUT FREQUENCY (kHz)
-10
0.8
-20
0.6
-30
0.4
-40
0.2
DNL (LSB)
1.0
-50
300
400
500
-60
0.0
-0.2
-70
-0.4
-80
-0.6
-90
-0.8
-1.0
100k
1k
10k
0
1024
2048
3072
4096
CODE
FREQUENCY (Hz)
FIGURE 7. CMRR vs FREQUENCY FOR VDD = 5V
FIGURE 8. TYPICAL DNL FOR THE ISL26712 FOR VDD = 5V
0
1.0
250mVP-P SINE WAVE ON VDD
NO DECOUPLING ON VDD
0.8
-20
0.6
0.4
INL (LSB)
-40
PSRR (dB)
200
FIGURE 6. ISL26712 DYNAMIC PERFORMANCE WITH VDD = 5V
0
-100
10k
100
FREQUENCY (kHz)
FIGURE 5. ISL26712 SINAD vs ANALOG INPUT FREQUENCY FOR
VARIOUS SUPPLY VOLTAGES
CMRR (dB)
0
1k
-60
-80
0.2
0.0
-0.2
-0.4
-0.6
-100
-0.8
-120
0
100
200
300
400
500
600
700
800
900
1000
FREQUENCY (kHz)
FIGURE 9. PSRR vs SUPPLY RIPPLE FREQUENCY WITHOUT SUPPLY
DECOUPLING
9
-1.0
0
1024
2048
3072
4096
CODE
FIGURE 10. TYPICAL INL FOR THE ISL26712 FOR VDD = 5V
FN7999.3
September 5, 2012
ISL26712, ISL26710, ISL26708
Typical Performance Characteristics
(Continued)
3.0
2.5
2.5
2.0
1.5
POS INL
1.0
1.5
INL (LSB)
DNL (LSB)
2.0
1.0
POS DNL
0.5
0.5
NEG INL
0.0
-0.5
NEG DNL
0.0
-1.0
-0.5
-1.5
-1.0
-2.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
3.5
0.5
1.0
2.0
5
ZERO CODE ERROR (LSB)
6
DNL (LSB)
1.5
POS DNL
0.5
NEG DNL
-0.5
4
3
2
3V VDD
1
0
5V VDD
-1
-2
-1.0
0.0
0.5
1.0
1.5
2.0
0.0
2.5
0.5
1.0
1.5
VREF (V)
2.0
2.5
3.0
3.5
VREF (V)
FIGURE 13. CHANGE IN DNL vs VREF FOR THE ISL26712 FOR
VDD = 3V
FIGURE 14. CHANGE IN OFFSET ERROR vs REFERENCE VOLTAGE FOR
VDD = 5V AND 3V FOR THE ISL26712
5
12.0
4
11.5
3
11.0
2
10.5
POS INL
ENOB (BITS)
INL (LSB)
2.5
FIGURE 12. CHANGE IN INL vs VREF FOR THE ISL26712 FOR
VDD = 3V
2.5
0.0
2.0
VREF (V)
VREF (V)
FIGURE 11. CHANGE IN DNL vs VREF FOR THE ISL26712 FOR
VDD = 5V
1.0
1.5
1
0
-1
NEG INL
5V VDD
3V VDD
10.0
9.5
9.0
-2
8.5
-3
8.0
-4
7.5
7.0
-5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VREF (V)
FIGURE 15. CHANGE IN INL vs VREF FOR THE ISL26712 FOR
VDD = 5V
10
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VREF (V)
FIGURE 16. CHANGE IN ENOB vs REFERENCE VOLTAGE FOR
VDD = 5V AND 3V FOR THE ISL26712
FN7999.3
September 5, 2012
ISL26712, ISL26710, ISL26708
Typical Performance Characteristics
(Continued)
70k
0.5
0.4
60k
65,516
CODES
0.3
50k
0.2
0.1
DNL (LSB)
HITS
40k
30k
0
-0.1
-0.2
20k
-0.3
10k
10
CODES
0
2044
2045
-0.4
10
CODES
2046
2047
2048
-0.5
2049
0
2050
256
512
FIGURE 17. HISTOGRAM OF 10,000 CONVERSIONS OF A DC INPUT
FOR THE ISL26712 WITH VDD = 5V
1024
FIGURE 18. TYPICAL DNL FOR THE ISL26710 FOR VDD = 5V
0.5
0
8192-POINT FFT
fSAMPLE = 1MSPS
fIN = 95.2kHz
SINAD = 61.6dB
THD = -75dB
SFDR = 81dB
-20
-40
0.4
0.3
0.2
INL (LSB)
AMPLITUDE (dBFS)
768
CODE
CODE
-60
-80
0.1
0
-0.1
-0.2
-100
-0.3
-120
-0.4
-140
-0.5
0
100
200
300
400
500
0
512
256
FREQUENCY (kHz)
FIGURE 20. TYPICAL INL FOR THE ISL26710 FOR VDD = 5V
0.25
0.25
0.20
0.20
0.15
0.15
0.10
0.10
0.05
0.05
INL (LSB)
DNL (LSB)
FIGURE 19. ISL26710 DYNAMIC PERFORMANCE WITH VDD = 5V
0.00
-0.05
0.00
-0.05
-0.10
-0.10
-0.15
-0.15
-0.20
-0.20
-0.25
0
32
64
96
128
160
192
224
CODE
FIGURE 21. TYPICAL DNL FOR THE ISL26708 FOR VDD = 5V
11
1024
768
CODE
256
-0.25
0
32
64
96
128
160
192
224
256
CODE
FIGURE 22. TYPICAL INL FOR THE ISL26708 FOR VDD = 5V
FN7999.3
September 5, 2012
ISL26712, ISL26710, ISL26708
Typical Performance Characteristics
(Continued)
0
8192-POINT FFT
fSAMPLE = 1MSPS
fIN = 95.2kHz
SINAD = 49.8dB
THD = -76dB
SFDR = 67dB
AMPLITUDE (dBFS)
-20
-40
-60
-80
-100
-120
-140
0
100
200
300
400
500
FREQUENCY (kHz)
FIGURE 23. ISL26708 DYNAMIC PERFORMANCE WITH VDD = 5V
12
FN7999.3
September 5, 2012
ISL26712, ISL26710, ISL26708
Functional Description
011...111
DAC
CONV
011...110
ADC CODE
The ISL26712/10/08 are based on a successive approximation
register (SAR) architecture utilizing capacitive charge
redistribution digital-to-analog converters (DACs). Figure 24
shows a simplified representation of the converter. During the
acquisition phase (ACQ), the differential input is stored on the
sampling capacitors (CS). The comparator is in a balanced state
since the switch across its inputs is closed. The signal is fully
acquired after tACQ has elapsed and the switches then transition
to the conversion phase (CONV) so the stored voltage may be
converted to digital format. The comparator will become
unbalanced when the differential switch opens and the input
switches transition (assuming that the stored voltage is not
exactly at mid-scale). The comparator output reflects whether the
stored voltage is above or below mid-scale, which sets the value
of the MSB. The SAR logic then forces the capacitive DACs to
adjust up or down by one quarter of full-scale by switching in
binarily weighted capacitors. Again, the comparator output
reflects whether the stored voltage is above or below the new
value, setting the value of the next lowest bit. This process
repeats until all 12 bits have been resolved.
000...001
000...000
111...111
100...010
100...001
100...000
–VREF
+ ½LSB
AIN–
CONV
0V
+VREF +VREF
– 1½LSB – 1LSB
ANALOG INPUT
AIN+ – (AIN–)
FIGURE 25. IDEAL TRANSFER CHARACTERISTICS
Analog Input
The ISL26712/10/08 feature a fully differential input with a
nominal full-scale range equal to twice the applied VREF voltage.
Each input swings VREF VP-P, 180° out-of-phase from one
another for a total differential input of 2*VREF (refer to
Figure 26).
CS
AIN+
ACQ
ACQ
1LSB = 2•VREF/4096
ACQ
CONV
CS
VCM
DAC
VREF
VREF(P-P)
AIN+
VREF(P-P)
AIN–
SAR
LOGIC
FIGURE 26. DIFFERENTIAL INPUT SIGNALING
FIGURE 24. SAR ADC ARCHITECTURAL BLOCK DIAGRAM
An external clock must be applied to the SCLK pin to generate a
conversion result. The allowable frequency range for SCLK is
10kHz to 18MHz (556SPS to 1MSPS). Serial output data is
transmitted on the falling edge of SCLK. The receiving device
(FPGA, DSP or Microcontroller) may latch the data on the rising
edge of SCLK to maximize set-up and hold times.
A stable, low-noise reference voltage must be applied to the
VREF pin to set the full-scale input range and common-mode
voltage. See “Voltage Reference Input” on page 14 for more
details.
ADC Transfer Function
The output coding for the ISL26712/10/08 is twos complement.
The first code transition occurs at successive LSB values (i.e.,
1 LSB, 2 LSB, and so on). The LSB size of the ISL26712 is
2*VREF/4096, while the LSB size of the ISL26710 is
2*VREF/1024 and the ISL26708 is 2*VREF/512. The ideal
transfer characteristic of the ISL26712/10/08 is shown in
Figure 25.
13
Differential signaling offers several benefits over a single-ended
input, such as:
• Doubling of the full-scale input range (and therefore the
dynamic range)
• Improved even order harmonic distortion
• Better noise immunity due to common mode rejection
Figure 27 shows the relationship between the reference voltage
and the full-scale input range for two different values of VREF.
Note that there is a trade-off between VREF and the allowable
common mode input voltage (VCM). The full-scale input range is
proportional to VREF; therefore the VCM range must be limited
for larger values of VREF in order to keep the absolute maximum
and minimum voltages on the AIN+ and AIN– pins within
specification. Figures 28 and 29 illustrate this relationship for 5V
and 3V operation, respectively. The dashed lines show the
theoretical VCM range based solely on keeping the AIN+ and
AIN– pins within the supply rails. Additional restrictions are
imposed due to the required headroom of the input circuitry,
resulting in practical limits shown by the shaded area.
FN7999.3
September 5, 2012
ISL26712, ISL26710, ISL26708
Voltage Reference Input
V
An external low-noise reference voltage must be applied to the
VREF pin to set the full-scale input range of the converter. The
reference input accepts voltages ranging from 0.1V to 2.2V for 3V
operation and 0.1V to 3.5V for 5V operation. The device is
specified with a reference voltage of 2.5V for 5V operation and
2.0V for 3V operation.
5.0
AIN–
4.0
AIN+
2.0VP-P
3.0
VCM
2.0
1.0
t
VREF = 2V
V
5.0
Figure 31 illustrates the ISL21010 voltage reference being used
with these ADCs. The ISL21010 series voltage references have
higher noise and drift than the ISL26090 devices, but they
consume very low operating current and are excellent for
battery-powered applications.
AIN–
4.0
AIN+
2.5VP-P
Figures 30 and 31 illustrate possible voltage reference options
for the ISL267440/ISL26750A or ISL267817. Figure 30 uses the
precision ISL21090 voltage reference which exhibits
exceptionally low drift and low noise. The ISL21090 must use a
power supply greater than 4.7V. The VREF input pin of the
ISL267XX devices uses very low current, so the decoupling
capacitor can be small (0.1µF).
VCM
3.0
2.0
1.0
t
VREF = 2.5V
FIGURE 27. RELATIONSHIP BETWEEN VREF AND FULL-SCALE
RANGE
VCM
5.0
4.0
4.25V
3.25V
3.0
2.0
1.75V
1.0
VREF
0.5
1.0
1.5
2.0
2.5
3.0
3.5
FIGURE 28. RELATIONSHIP BETWEEN VREF AND VCM FOR VDD = 5V
VCM
3.0
2.5
2.0V
2.0
1.5
1.0V
1.0
0.5
VREF
0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
FIGURE 29. RELATIONSHIP BETWEEN VREF AND VCM FOR VDD = 3V
14
FN7999.3
September 5, 2012
ISL26712, ISL26710, ISL26708
5V
+
BULK
0.1µF
0.1µF
1 DNC
DNC
8
2 VIN
DNC
7
3 COMP VOUT
6
4 GND
5
ISL267440
ISL267450A
VDD
VREF
2.5V
0.1µF
TRIM
ISL21090
FIGURE 30. PRECISION VOLTAGE REFERENCE FOR +5V SUPPLY
+2.7V TO +3.6V
OR +5V
VIN
VOUT
+
BULK
1
GND
3
0.1µF
2
0.1µF
VDD
ISL267817
VREF
1.25, 2.048 OR 2.5V
ISL21010
0.1µF
FIGURE 31. VOLTAGE REFERENCE FOR +2.7V TO +3.6V, OR FOR +5V SUPPLY
Converter Operation
The ISL26712, ISL26710 and ISL26708 are designed to
minimize power consumption by only powering up the SAR
comparator during conversion time. When the converter is in
track mode (its sample capacitors are tracking the input signal)
the SAR comparator is powered down. The state of the converter
is dictated by the logic state of CS. When CS is high the SAR
comparator is powered down while the sampling capacitor array
is tracking the input. When CS transitions low, the capacitor array
immediately captures the analog signal that is being tracked.
After CS is taken low, the SCLK pin is toggled 16 times. For the
first 3 clocks, the comparator is powered up and auto-zeroed,
then the SAR decision process is begun. This process uses 12
SCLK cycles for the 12-bit ISL26712. Each SAR decision is
presented to the SDATA output on the next clock cycle after the
SAR decision is performed. The SAR process (12 bits) is
completed on SCLK cycle 15. At this point in time, the SAR
comparator is powered down and the capacitor array is placed
back into Track mode. The last SAR comparator decision is
output from SDATA on the 16th SCLK cycle. When the last data
bit is output from SDATA the output switches to a logic 0 until CS
is taken high, at which time, the SDATA output enters a High-Z
state.
The ISL26710 and ISL26708 will take fewer clock cycles for their
SAR decisions and will output fewer data bits. The extra bits
following the output of the LSB will be logic zeroes.
Figures 32, 33, and 34 illustrate the system timing for the 12-,
10- and 8-bit converters respectively.
15
FN7999.3
September 5, 2012
ISL26712, ISL26710, ISL26708
FIGURE 32. ISL26712 SYSTEM TIMING
FIGURE 33. ISL26710 SYSTEM TIMING
FIGURE 34. ISL26708 SYSTEM TIMING
16
FN7999.3
September 5, 2012
ISL26712, ISL26710, ISL26708
SHORT CYCLING
In cases where a lower resolution conversion is acceptable, CS can
be pulled high before all SCLK falling edges have elapsed. This is
referred to as short cycling, and it can be used to further optimize
power consumption. In this mode a lower resolution result will be
output, but the ADC will enter static mode sooner and exhibit a
lower average power consumption than if the complete conversion
cycle were carried out. The minimum acquisition time (tACQ)
requirement of 200ns must be met for the next conversion to be
valid.
POWER-ON RESET
When power is first applied, the ISL26712/10/08 performs a
power-on reset that requires approximately 2.5ms to execute. After
this is complete, a single dummy conversion must be executed (by
taking CS low) in order to initialize the switched capacitor track and
hold. The dummy conversion cycle will take 1µs with an 18MHz
SCLK. Once the dummy cycle is complete, the ADC mode will be
determined by the state of CS. Regular conversions can be started
immediately after this dummy cycle is completed and time has
been allowed for proper acquisition.
ACQUISITION TIME
To achieve the maximum sample rate (1 MSps) in the ISL26712
device, the maximum acquisition time is 200ns. For slower
conversion rates, or for conversions performed using a slower
SCLK value than 18MHz, the minimum acquisition time is 200ns.
This same minimum applies to the ISL26710 and ISL26708. This
minimum acquisition time applies to all the devices if short
cycling is utilized.
POWER vs THROUGHPUT RATE
The ISL26712/10/08 provide reduced power consumption at
lower conversion rates by automatically switching into a
low-power mode after completing a conversion. The average
power consumption of the ADC decreases at lower throughput
rates. Figure 35 shows the typical power consumption over a
wide range of throughput rates.
100
POWER (mW)
10
The serial interface is designed around using 16 SCLK cycles to
perform an autozero on the SAR comparator and additional SCLK
cycles for SAR comparator decisions (12 SLCKs in the 12-bit
device, 10 SCLKs in the 10-bit device, and 8 SCLKs in the 8-bit
device). If short cycling is not used, all converter throughput
cycles take 16 SCLKs. The SDATA output goes low after the last
conversion decision has been presented to the SDATA output, as
shown in Figures 32, 33, and 34.
Data Format
Output data is encoded in two’s complement format as shown in
Table 1. The voltage levels in the table are idealized and don’t
account for any gain/offset errors or noise.
TABLE 1. OUTPUT CODES - DIFFERENTIAL
Input Voltage
Two’s Complement (12-bit)
>(VFS-1.5 LSB)
7FF
VFS-1.5 LSB
7FF
...
7FE
-0.5 LSB
000
…
FFF
-VFS +0.5 LSB
801
…
800
NOTE: VFS in the table above equals the voltage between AIN+ and AIN-.
Differential full scale is equal to 2* VREF.
Terminology
Signal-to-(Noise + Distortion) Ratio (SINAD)
This is the measured ratio of signal-to-(noise + distortion) at the
output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (fs/2), excluding DC. The ratio
is dependent on the number of quantization levels in the
digitization process; the more levels, the smaller the quantization
noise. The theoretical signal-to-(noise + distortion) ratio for an
ideal N-bit converter with a sine wave input is given by
Equation 1:
Signal-to-(Noise + Distortion) = ( 6.02 N + 1.76 )dB
VDD = 5V
(EQ. 1)
Thus, for a 12-bit converter this is 74dB, and for a 10-bit this is 62dB.
1
Total Harmonic Distortion
0.01
0
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the ISL26712/10/08, it is
defined as Equation 2:
VDD = 3V
0.1
50
100
150
200
250
300
350
THROUGHPUT (Ksps)
FIGURE 35. POWER CONSUMPTION vs THROUGHPUT RATE
Serial Digital Interface
Conversion data is accessed with an SPI-compatible serial
interface. The interface consists of the serial clock (SCLK), serial
data output (SDATA), and chip select (CS).
17
V 22 + V 32 + V 42 + V 52 + V 62
THD ( dB ) = 20 log ----------------------------------------------------------------------V 12
(EQ. 2)
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second to the
sixth harmonics.
Peak Harmonic or Spurious Noise (SFDR)
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding DC) to the rms value of the
FN7999.3
September 5, 2012
ISL26712, ISL26710, ISL26708
fundamental. Also referred to as Spurious Free Dynamic Range
(SFDR). Normally, the value of this specification is determined by
the largest harmonic in the spectrum, but for ADCs where the
harmonics are buried in the noise floor, it will be a noise peak.
Positive Gain Error
Intermodulation Distortion
Negative Gain Error
With inputs consisting of sine waves at two frequencies, fa and fb,
any active device with nonlinearities will create distortion products
at sum and difference frequencies of mfa ± nfb where m and n =
0, 1, 2 or 3. Intermodulation distortion terms are those for which
neither m nor n are equal to zero. For example, the second order
terms include (fa + fb) and (fa – fb), while the third order terms
include (2fa + fb), (2fa – fb), (fa + 2fb), and (fa –2fb).
This is the deviation of the first code transition (100...000 to
100...001) from the ideal AIN+ – AIN– (i.e., – REF + 1 LSB), after
the zero code error has been adjusted out.
The ISL26712/10/08 is tested using the CCIF standard, where
two input frequencies near the top end of the input bandwidth
are used. In this case, the second order terms are usually
distanced in frequency from the original sine waves, while the
third order terms are usually at a frequency close to the input
frequencies. As a result, the second and third order terms are
specified separately. The calculation of the intermodulation
distortion is as per the THD specification, where it is the ratio of
the rms sum of the individual distortion products to the rms
amplitude of the sum of the fundamentals expressed in dBs.
Aperture Delay
This is the amount of time from the leading edge of the sampling
clock until the ADC actually takes the sample.
Aperture Jitter
This is the sample-to-sample variation in the effective point in
time at which the actual sample is taken.
Full Power Bandwidth
The full power bandwidth of an ADC is that input frequency at
which the amplitude of the reconstructed fundamental is
reduced by 3dB for a full-scale input.
Common-Mode Rejection Ratio (CMRR)
The common-mode rejection ratio is defined as the ratio of the
power in the ADC output at full-scale frequency, f, to the power of
a 250mVP-P sine wave applied to the common-mode voltage of
AIN+ and AIN– of frequency fs shown in Equation 3:
CMRR ( dB ) = 10 log ( Pfl ⁄ Pfs )
(EQ. 3)
This is the deviation of the last code transition (011...110 to
011...111) from the ideal AIN+ – AIN– (i.e., +REF – 1 LSB), after
the zero code error has been adjusted out.
Track and Hold Acquisition Time
The track and hold acquisition time is the minimum time
required for the track and hold amplifier to remain in track mode
for its output to reach and settle to within 0.5 LSB of the applied
input signal.
Power Supply Rejection Ratio (PSRR)
The power supply rejection ratio is defined as the ratio of the
power in the ADC output at full-scale frequency, f, to ADC VDD
supply of frequency fS. The frequency of this input varies from
1kHz to 1MHz as shown by Equation 4.
PSRR ( dB ) = 10 log ( Pf ⁄ Pfs )
(EQ. 4)
Pf is the power at frequency f in the ADC output; Pfs is the power
at frequency fs in the ADC output.
Application Hints
Grounding and Layout
The printed circuit board that houses the ISL26712/10/08
should be designed so that the analog and digital sections are
separated and confined to certain areas of the board. This
facilitates the use of ground planes that can be easily separated.
A minimum etch technique is generally best for ground planes
since it gives the best shielding. Digital and analog ground planes
should be joined in only one place, and the connection should be
a star ground point established as close to the GND pin on the
ISL26712/10/08 as possible. Avoid running digital lines under
the device, as this will couple noise onto the die. The analog
ground plane should be allowed to run under the
ISL26712/10/08 to avoid noise coupling.
The power supply lines to the device should use as large a trace
as possible to provide low impedance paths and reduce the
effects of glitches on the power supply line.
Differential Nonlinearity (DNL)
Fast switching signals, such as clocks, should be shielded with
digital ground to avoid radiating noise to other sections of the
board, and clock signals should never run near the analog inputs.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feed-through the board. A microstrip
technique is by far the best but is not always possible with a
double-sided board.
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
In this technique, the component side of the board is dedicated
to ground planes, while signals are placed on the solder side.
Zero-Code Error
Good decoupling is also important. All analog supplies should be
decoupled with μF tantalum capacitors in parallel with 0.1μF
capacitors to GND. To achieve the best from these decoupling
components, they must be placed as close as possible to the device.
Pfl is the power at frequency f in the ADC output; Pfs is the power
at frequency fs in the ADC output.
Integral Nonlinearity (INL)
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function.
This is the deviation of the midscale code transition (111...111 to
000...000) from the ideal AIN+ – AIN– (i.e., 0 LSB).
18
FN7999.3
September 5, 2012
ISL26712, ISL26710, ISL26708
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
CHANGE
March 14, 2012
FN7999.0
Initial Release.
May 30, 2012
FN7999.1
Page 3, Ordering Information: removed “Coming Soon” from all SOT 23 parts.
June 20, 2012
FN7999.2
Updated Figure 25, “IDEAL TRANSFER CHARACTERISTICS,” on page 13.
Updated Table 1 on page 17.
August 22, 2012
FN7999.3
Bolded applicable MIN MAX specs in “Electrical Specifications” and “Timing Specifications” tables.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on
intersil.com: ISL26712,ISL26710, ISL26708
To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff
FITs are available from our website at: http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
19
FN7999.3
September 5, 2012
ISL26712, ISL26710, ISL26708
Small Outline Transistor Plastic Packages (SOT23-8)
P8.064
0.20 (0.008) M C
VIEW C
8 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
CL
8
7
INCHES
e
b
6
5
CL
CL
E
1
2
3
E1
4
e1
C
D
CL
A
A2
A1
SEATING
PLANE
-C-
0.10 (0.004)
MIN
MAX
MIN
MAX
A
0.036
0.057
0.90
1.45
-
0.000
0.0059
0.00
0.15
-
A2
0.036
0.051
0.90
1.30
-
b
0.009
0.015
0.22
0.38
-
b1
0.009
0.013
0.22
0.33
c
0.003
0.009
0.08
0.22
6
c1
0.003
0.008
0.08
0.20
6
D
0.111
0.118
2.80
3.00
3
E
0.103
0.118
2.60
3.00
-
E1
0.060
0.067
1.50
1.70
3
e
0.0256 Ref
0.65 Ref
-
e1
0.0768 Ref
1.95 Ref
-
0.014
0.022
0.35
4
0.55
L1
0.024 Ref.
0.60 Ref.
L2
0.010 Ref.
0.25 Ref.
N
8
8
5
WITH
b
R
0.004
-
0.10
PLATING
b1
R1
0.004
0.010
0.10
0.25
α
0o
8o
0o
8o
c
NOTES
A1
L
C
MILLIMETERS
SYMBOL
-
c1
Rev. 2 9/03
NOTES:
BASE METAL
1. Dimensioning and tolerance per ASME Y14.5M-1994.
2. Package conforms to EIAJ SC-74 and JEDEC MO178BA.
4X θ1
3. Dimensions D and E1 are exclusive of mold flash, protrusions, or
gate burrs.
4. Footlength L measured at reference to gauge plane.
R1
5. “N” is the number of terminal positions.
R
GAUGE PLANE
SEATING
PLANE
L
C
L1
α
6. These Dimensions apply to the flat section of the lead between
0.08mm and 0.15mm from the lead tip.
7. Controlling dimension: MILLIMETER. Converted inch dimensions
are for reference only
L2
4X θ1
VIEW C
20
FN7999.3
September 5, 2012
ISL26712, ISL26710, ISL26708
Package Outline Drawing
L8.3x3I
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 1 6/09
2X 1.950
3.00
B
0.15
8
5
3.00
(4X)
6X 0.65
A
1.64 +0.10/ - 0.15
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
1
4
4
8X 0.30
8X 0.400 ± 0.10
TOP VIEW
0.10 M C A B
2.38
+0.10/ - 0.15
BOTTOM VIEW
SEE DETAIL "X"
( 2.38 )
( 1.95)
0.10 C
Max 0.80
C
0.08 C
SIDE VIEW
( 8X 0.60)
(1.64)
( 2.80 )
PIN 1
C
0 . 2 REF
5
(6x 0.65)
0 . 00 MIN.
0 . 05 MAX.
( 8 X 0.30)
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6.
21
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN7999.3
September 5, 2012
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