DATASHEET

ISL1539A
Features
The ISL1539A provides 4 internal wideband op amps
intended to be used as two pairs of differential line
drivers. The ISL1539A’s high bandwidth, 240MHz, and
ultra low distortion, -89dBc @ 1MHz, 2VP-P, support the
demanding MTPR requirements of emerging VDSL2 line
driver designs. Less demanding requirements can be met
at very low quiescent powers using the supply current
adjustment features.
• 360mA Output Drive Capability
• 41.8VP-P Differential Output Drive into 100Ω
• -89dBc THD @ 1MHz 2VP-P
• -65dBc MTPR (VDSL 8b Profile)
• High Slew Rate of 3000V/µs Differential
• Bandwidth (240MHz @ AV-DIFF = 10)
• Supply Current Control Pins
Each of the 4 internal op amps is a wideband current
feedback amplifier offering very high slew rate intrinsic to
that design using low quiescent current levels. Each of
the two pair of amplifiers (ports) can also be power
optimized to the application using two external quiescent
control logic pins. Full power is nominally 27.2mA/port
with options of medium power cutback to 23mA/port, a
low power condition at 13.5mA/port, and an off state at
<0.5mA/port. Added quiescent power flexibility is
provided through an external IADJ pin. Grounding the pin
gives the nominal currents listed above while inserting a
resistor from this pin to ground can be used to scale each
of the settings downward.
• Port Separation
- 78dB @ 500kHz
- 70dB @ 1MHz
- 60dB @ 4MHz
High power push/pull line driver applications as
illustrated in the example below are best supported using
a low headroom, high output current device. On ±12V
supplies, the ISL1539A offers a 1.1V headroom with
>360mA peak output current. Driving differentially this
gives >41.8VP-P swing to as low as 58Ω differential load.
High SFDR operation is also supported for supplies as low
as ±7.5V. Intended to be used as differential pairs, this
two port device includes special circuitry to minimize
common mode loop peaking while also reducing the
common mode output noise spectrum. That circuitry
links the two sides of each port, precluding their
application as individual amplifiers.
• AN1325 “Choosing and Using Bypass Capacitors”
Typical Application
+12V
Rb
+
¼
ISL1539A
SOURCE
VI
-
Rb
+
• 8MHz and 17MHz VDSL2 Profiles
• ADSL2+
Related Literature
(see Device Info page)
• TB426 “Characterization of the Output Protection
Circuitry of the EL1528 DSL Driver for Lightning
Surges”
TABLE 1. ALTERNATE SOLUTIONS
PART #
NOMINAL ±VCC BANDWIDTH
(V)
(MHz)
APPLICATIONS
ISL1557
±6
200
VDSL
ISL1534
±12
40
ADSL2+
ISL1536
±12
50
ADSL2+
4MHz Harmonic Distortion
AV = +10
Ro
RF = 3.2kΩ
RL = 100Ω DIFF
1:n
VO
LOAD
Rf
3.2kΩ
¼
ISL1539A
Applications*(see page 21)
VS = ±12V
-
Rf
3.2kΩ
Ω
Rg 711
• Pb-Free (RoHS Compliant)
3rd HD
2nd HD
THD
Ro
AV-DIFF = VO/VI = 10V/V
-12V
TYPICAL DIFFERENTIAL I/O LINE DRIVER
(1 OF 2 PORTS)
September 23, 2009
FN6916.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2009. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL1539A
Dual Port VDSL2 Line Driver
ISL1539A
Pin Configurations
IADJ 4
NC 5
VINC+ 6
14 VOUTD
VS- 12
13 VS+
VS- 1
24 VS+
C0AB 2
23 VOUTA
C1AB 3
22 VINA-
VINA+ 4
21 VINB-
VINB+ 5
20 VOUTB
GND 6
THERMAL
PAD
IADJ 7
20 VOUTA
21 VS+
19 VINA-
VINB+ 2
18 VINB-
GND 3
19 NC
17 VOUTB
THERMAL
PAD
IADJ 4
18 NC
16 NC/SHIELD
NC 5
VINC+ 8
17 VOUTC
VIND+ 9
16 VINC-
C1CD 10
15 VIND-
C0CD 11
14 VOUTD
VS- 12
VINA+ 1
15 VOUTC
VINC+ 6
14 VINC-
VIND+ 7
13 VINDC1CD 8
+
C0CD 11
13 VINDVOUTD 12
VIND+ 7
15 VIND-
C1CD 10
14 VINC-
+
VS+ 11
16 VINC-
VIND+ 9
15 VOUTC
21 VS+
17 VOUTC
16 NC/SHIELD
+
-
13 VS+
THERMAL PAD CONNECTS TO GND OR -VS
VS+ 11
+
-
17 VOUTB
VOUTD 12
18 NC
18 VINB-
+
VS- 10
IADJ 7
GND 3
C0CD 9
19 NC
23 C0AB
GND 6
VINC+ 8
VINB+ 2
20 VOUTB
19 VINA-
+
-
C0CD 9
+
VINB+ 5
VINA+ 1
20 VOUTA
21 VINB-
22 VS-
VINA+ 4
VS- 10
22 VINA-
22 VS-
23 VOUTA
C1AB 3
C1CD 8
C0AB 2
24 C1AB
+
-
24 C1AB
24 VS+
VS- 1
23 C0AB
ISL1539A
(24 LD QFN)
TOP VIEW
ISL1539A
(24 LD HTSSOP)
TOP VIEW
THERMAL PAD CONNECTS TO GND OR -VS
Pin Descriptions
ISL1539AIR
(24 Ld QFN)
ISL1539AIV
(24 Ld HTSSOP)
PIN NAME
1
4
VINA+
Amplifier A non-inverting input
(Refer to Circuit 1)
2
5
VINB+
Amplifier B non-inverting input
(Refer to Circuit 1)
3
6
GND
Ground connection
4
7
IADJ
Supply current control pin for
both DSL Port #1 and #2
5
18, 19
NC
6
8
VINC+
Amplifier C non-inverting input
(Refer to Circuit 1)
7
9
VIND+
Amplifier D non-inverting input
(Refer to Circuit 1)
8
10
C1CD
DSL Port #2 current control pin (Refer to Figure 46)
9
11
C0CD
DSL Port #2 current control pin (Refer to Figure 46)
FUNCTION
(Refer to Figure 46)
Not connected
10, 22
1, 12
VS-
Negative supply
11, 21
13, 24
VS+
Positive supply
12
14
VOUTD
2
CIRCUIT
Amplifier D output
(Refer to Circuit 2)
FN6916.0
September 23, 2009
ISL1539A
Pin Descriptions (Continued)
ISL1539AIR
(24 Ld QFN)
ISL1539AIV
(24 Ld HTSSOP)
PIN NAME
13
15
VIND-
14
16
VINC-
Amplifier C Inverting Input
(Refer to Circuit 3)
15
17
VOUTC
Amplifier C output
(Refer to Circuit 2)
16
18, 19
NC/SHIELD
17
20
VOUTB
Amplifier B output
18
21
VINB-
Amplifier B Inverting Input
(Refer to Circuit 3)
19
22
VINA-
Amplifier A Inverting Input
(Refer to Circuit 3)
20
23
VOUTA
Amplifier A output
(Refer to Circuit 2)
23
2
C0AB
DSL Port #1 current control pin (Refer to Figure 46)
24
3
C1AB
DSL Port #1 current control pin (Refer to Figure 46)
-
-
THERMAL PAD
FUNCTION
CIRCUIT
Amplifier D Inverting Input
(Refer to Circuit 3)
Not Connected
(Refer to Circuit 2)
Connects to GND or -VS
VS+
VS +
VS+
VS+
VSVS-
VS -
CIRCUIT 1
CIRCUIT 2
VS -
CIRCUIT 3
Ordering Information
PART
NUMBER
PART
MARKING
OPERATING AMBIENT
TEMP RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL1539AIRZ (Note 2)
1539A IRZ
-40 to +85
24 Ld QFN
L24.4x5B
ISL1539AIRZ-T13 (Notes 1, 2)
1539A IRZ
-40 to +85
24 Ld QFN
L24.4x5B
COMING SOON
ISL1539AIVEZ (Note 2)
1539A IVEZ
-40 to +85
24 Ld HTSSOP
MDP0048
COMING SOON
ISL1539AIVEZ-T13 (Notes 1, 2) 1539A IVEZ
-40 to +85
24 Ld HTSSOP
MDP0048
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL1539A. For more information on MSL please
see techbrief TB363.
3
FN6916.0
September 23, 2009
ISL1539A
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
VS+ to VS- Supply Voltage . . . . . . . . . . . . -0.3V to +26.4V
VS+ Voltage to GND . . . . . . . . . . . . . . . . . -0.3V to +26.4V
VS- Voltage to GND . . . . . . . . . . . . . . . . . -26.4V to +0.3V
Driver VIN+ Voltage . . . . . . . . . . . . . . . . . . . . . VS- to VS+
C0, C1 Voltage to GND . . . . . . . . . . . . . . . . . .-0.3V to +6V
IADJ Voltage to GND . . . . . . . . . . . . . . . . . . . . . -1V to +4V
ESD Rating
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 200V
Human Body Model (Per MIL-STD-883 Method 3015.7). . 3kV
Charge Device Model . . . . . . . . . . . . . . . . . . . . . . 1.5kV
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
24 Ld QFN Package (Notes 4, 5) . .
39
4.5
24 Ld HTSSOP Package (Notes 4, 5)
TBD
TBD
Maximum Junction Temperature (Plastic Package). . . +150°C
Current into any Input . . . . . . . . . . . . . . . . . . . . . . . . 8mA
Continuous Output Current for Long Term Reliability . . . . 50mA
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . See Figure 42
Storage Temperature Range . . . . . . . . . . . -40°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . -40°C to +85°C
Junction Temperature Range . . . . . . . . . . . -40°C to +150°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. QFN and HTSSOP
exposed pad soldered to PCB per JESD51-5. See Tech Brief TB379 for details.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise
noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VS = ±12V, RL= 100Ω differential, IADJ = C0 = C1 = 0V, AV = 10V/V, RF = 3.2kΩ,
TA = +25°C. Amplifier pairs tested separately unless otherwise indicated.
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
BW
-3dB Small Signal Bandwidth VO < 2VP-P-DIFF, AV = 10
240
MHz
VO < 2VP-P-DIFF (Note 6)
120
MHz
100
MHz
3000
V/µs
VOUT = 10VP-P-DIFF
-93
dBc
VOUT = 10VP-P-DIFF
-90
dBc
THD
VOUT = 10VP-P-DIFF
-88
dBc
2nd Harmonic
VOUT = 2VP-P-DIFF
-91
dBc
3rd Harmonic
VOUT = 2VP-P-DIFF
-109
dBc
THD
VOUT = 2VP-P-DIFF
-91
dBc
2nd Harmonic
VOUT = 2VP-P-DIFF
-87
dBc
3rd Harmonic
VOUT = 2VP-P-DIFF
-95
dBc
THD
VOUT = 2VP-P-DIFF
-86
dBc
Multi-Tone Power Ratio
26kHz to 8MHz, 4kHz Tone Spacing,
PLINE = 19dBm, VDSL2+ 8b (Note 6)
-70
dBc
VOUT = 10VP-P-DIFF (Note 6)
-93
dBc
VOUT = 10VP-P-DIFF (Note 6)
-90
dBc
VOUT = 10VP-P-DIFF (Note 6)
-88
dBc
-3dB Large Signal Bandwidth VO = 10VP-P-DIFF
SR
20% to 80%
200kHz Harmonic 2nd Harmonic
Distortion
3rd Harmonic
1MHz Harmonic
Distortion
8MHz Harmonic
Distortion
MTPR
200kHz Harmonic 2nd Harmonic
Distortion
3rd Harmonic
THD
4
VO = 32VP-P-DIFF
2000
FN6916.0
September 23, 2009
ISL1539A
Electrical Specifications
PARAMETER
4MHz Harmonic
Distortion
8MHz Harmonic
Distortion
VS = ±12V, RL= 100Ω differential, IADJ = C0 = C1 = 0V, AV = 10V/V, RF = 3.2kΩ,
TA = +25°C. Amplifier pairs tested separately unless otherwise indicated. (Continued)
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
2nd Harmonic
VOUT = 10VP-P-DIFF
(Note 6)
-72
dBc
3rd Harmonic
VOUT = 10VP-P-DIFF
(Note 6)
-70
dBc
THD
VOUT = 10VP-P-DIFF
(Note 6)
-68
dBc
2nd Harmonic
VOUT = 2VP-P-DIFF (Note 6)
-83
dBc
3rd Harmonic
VOUT = 2VP-P-DIFF (Note 6)
-78
dBc
THD
VOUT = 2VP-P-DIFF (Note 6)
-76
dBc
eN
Non-Inverting Input Voltage f = 1MHZ
Noise at each of the 4 Inputs
4.0
nV/√Hz
+iN
Non-Inverting Input Current f = 1MHZ
Noise at each of the 4 Inputs
2.7
pA/√Hz
-iN
Inverting Input Current Noise f = 1MHZ
at each of the 4 Inputs
23
pA/√Hz
eN-CM
Common Mode Output Noise
at each Port Pair
90
nV/√Hz
f = 1MHZ
POWER CONTROL FEATURES
VIH
Logic High Voltage
C0 and C1 inputs
VIL
Logic Low Voltage
C0 and C1 inputs
IIH0 , IIH1
Logic High Current for C0, C1 C0 = 3.3V, C1 = 3.3V
IIL0, IIL1
Logic Low Current for C0 or C1 C0 = 0V, C1 = 0V
IADJ
Input Resistance
2.0
V
0.8
V
-5
1
+5
µA
-17
-13
-10
µA
500
Ω
Maximum Operating Supply
Voltage
±12.6
V
Minimum Operating Supply
Voltage
±7.5
V
SUPPLY CHARACTERISTICS
IGND
GND Pin Current per Port
All outputs at 0V (Note 7)
0.2
0.4
0.5
mA
IS+ (Full Power)
Positive Supply Current per
Port
All outputs at 0V, C0 = C1 = 0V, No
Load
21
27.2
31.5
mA
IS+ (Medium)
Positive Supply Current per
Port
All outputs at 0V, C0 = 3.3V, C1 = 0V,
No Load
17.8
23
26.7
mA
IS+ (Low)
Positive Supply Current per
Port
All outputs at 0V, C0 = 0V, C1 = 3.3V,
No Load
10.4
13.5
15.6
mA
All outputs at 0V, C0 = C1 = 3.3V, No
Load
0.2
0.4
0.5
mA
IS+ (Power-down) Positive Supply Current per
Port
OUTPUT CHARACTERISTICS
VOUT
IOL
Output Swing
RL-DIFF = No Load
±10.7
±10.9
V
Lightly Loaded Positive Swing
RL-DIFF = 100Ω
+10.3
+10.5
V
Lightly Loaded Negative Swing
RL-DIFF = 100Ω
Heavy Loaded Positive Swing
RL-DIFF = 60Ω
Heavy Loaded Negative Swing
RL-DIFF = 60Ω
Linear Output Current
RL = 25Ω, f = 100kHz, THD = -60dBc
5
-10.4
+9.4
-10.2
+9.8
-9.7
±360
V
V
-9.3
V
mA
FN6916.0
September 23, 2009
ISL1539A
Electrical Specifications
PARAMETER
IOUT
VS = ±12V, RL= 100Ω differential, IADJ = C0 = C1 = 0V, AV = 10V/V, RF = 3.2kΩ,
TA = +25°C. Amplifier pairs tested separately unless otherwise indicated. (Continued)
DESCRIPTION
Peak Output Current
CONDITIONS
MIN
VOUT = ±1V, RL = 1Ω
TYP
MAX
±600
UNIT
mA
INPUT CHARACTERISTICS
VOS
Input Offset Voltage
-8
+3.5
+8
mV
ΔVOS
Input VOS Mismatch
Between Amplifiers for Each
Port
-2
0
+2
mV
VOS, DRIFT
Input VOS Drift
IB +
Non-Inverting Input Bias
Current
-8
+8
µA
ΔIB+
Non-Inverting IB+ Mismatch
Between Amplifiers for Each
Port
-2
+2
µA
IB+, DRIFT
Non-Inverting IB+ Drift
IB -
Inverting Input Bias Current
-75
+75
µA
ΔIB-
Inverting IB- Mismatch
Between Amplifiers for Each
Port
-35
+35
µA
IB-, DRIFT
Inverting IB- Drift
CMIR
Common Mode Input Range
at each of the 4
Non-Inverting Input Pins
CMRR
Common Mode Rejections for VCM to Differential Mode Output
each Port. VCM = -5V to +5V (Input Referred)
PSRR
Power Supply Rejections for
each Port to Differential
Output (Input Referred)
Power Supply Rejections for
each Port to Common Mode
Output (Output Referred)
-25°C to +125°C TJ
±15
-25°C to +125°C TJ
-25°C to +125°C TJ
µV/°C
±12
nA/°C
±25
nA/°C
±7.5
V
80
dB
VCM to Commonl Mode Output
(Output Referred)
43
dB
+VS = +7.5V to +12V, -VS = -12V
97
dB
-VS = -7.5V to -12V, +VS = +12V
92
dB
+VS = +7.5V to +12V, -VS = -12V
51
dB
-VS = -7.5V to -12V, +VS = +12V
45
dB
NOTES:
6. Active Termination Test Circuit. Low Power Mode (see Figure 45).
7. The -VS supply current is the +VS supply current minus the ground current, except power down condition.
6
FN6916.0
September 23, 2009
ISL1539A
Typical Performance Curves
VCC = ±12V, RF = 3.2kΩ, GD = 10V/V (differential), RLOAD = 100Ω, TA ≈ +25°C, C0 = C1 = IADJ = 0V (full power),
unless otherwise noted.
NORMALIZED GAIN (dB)
9
6
3
VO = 0.5VP-P
2VP-P
5VP-P
AV = 10, RF = 3.2kΩ
AV = 20, RF = 2.5kΩ
AV = 10
AV = 40, RF = 2.4kΩ
10VP-P 0.5VP-P
0
-3
20VP-P
-6
AV = 40
-9
-12
1M
AV = 20
10M
100M
1G
FREQUENCY (Hz)
FIGURE 1. SMALL SIGNAL FREQUENCY RESPONSE vs
GAIN
FIGURE 2. LARGE SIGNAL FREQUENCY RESPONSE
3rd HD
2nd HD
2nd HD
THD
THD
3rd HD
FIGURE 3. 1MHz HARMONIC DISTORTION vs
OUTPUT SWING
20
PAR = 5.4
14.5dBm ON LINE
10
FIGURE 45 CIRCUIT
0
MTPR(dBc)
FIGURE 4. 4MHz HARMONIC DISTORTION vs
OUTPUT SWING
THD
-10
-20
-64dBc
-30
-40
-50
2nd HD
-60
3rd HD
-70
-80
7.995M
8.000M
8.005M
FREQUENCY (Hz)
FIGURE 5. 17MHz DMT PROFILE
7
FIGURE 6. 4MHz HARMONIC DISTORTION vs LOAD
FN6916.0
September 23, 2009
ISL1539A
Typical Performance Curves
VCC = ±12V, RF = 3.2kΩ, GD = 10V/V (differential), RLOAD = 100Ω, TA ≈ +25°C, C0 = 3.3V, C1 = IADJ = 0V
(medium power), unless otherwise noted.
NORMALIZED GAIN (dB)
9
VO = 0.5VP-P
6 AV = 10, RF = 3.2kΩ
5VP-P
AV = 20, RF = 2.8kΩ
3 AV = 40, R = 2.4kΩ
F
AV = 10
2VP-P
10VP-P 0.5VP-P
0
20VP-P
-3
-6
AV = 40
-9
-12
1M
AV = 20
10M
100M
1G
FREQUENCY (Hz)
FIGURE 7. SMALL SIGNAL FREQUENCY RESPONSE vs
GAIN
FIGURE 8. LARGE SIGNAL FREQUENCY RESPONSE
3rd HD
2nd HD
2nd HD
3rd HD
THD
THD
FIGURE 9. 1MHz HARMONIC DISTORTION vs
OUTPUT SWING
20
PAR = 5.4
19dBm ON LINE
FIGURE 45 CIRCUIT
0
MTPR (dBc)
FIGURE 10. 4MHz HARMONIC DISTORTION vs
OUTPUT SWING
-20
-65dBc
-40
2nd HD
-60
3rd HD
-80
THD
-100
8.395M
8.400M
8.405M
FREQUENCY (Hz)
FIGURE 11. VDSL2+ 8MHz DMT PROFILE
8
FIGURE 12. 4MHz HARMONIC DISTORTION vs LOAD
FN6916.0
September 23, 2009
ISL1539A
Typical Performance Curves
VCC = ±12V, RF = 3.2kΩ, GD = 10V/V (differential), RLOAD = 100Ω, TA ≈ +25°C, C1 = 3.3V, C0 = IADJ = 0V (low
power), unless otherwise noted.
NORMALIZED GAIN (dB)
9
VO = 0.5VP-P
6 AV = 10, RF = 3.2kΩ
AV = 20, RF = 2.8kΩ
3 AV = 40, R = 2.4kΩ
F
AV = 10
10VP-P
0.5VP-P
2VP-P
0
-3
20VP-P
-6
AV = 40
-9
-12
1M
5VP-P
AV = 20
10M
100M
1G
FREQUENCY (Hz)
FIGURE 13. SMALL SIGNAL FREQUENCY RESPONSE
vs GAIN
FIGURE 14. LARGE SIGNAL FREQUENCY RESPONSE
THD
THD
2nd HD
3rd HD
2nd HD
3rd HD
FIGURE 15. 1MHz HARMONIC DISTORTION vs
OUTPUT SWING
FIGURE 16. 4MHz HARMONIC DISTORTION vs
OUTPUT SWING
20
PAR = 5.4
19dBm ON LINE
FIGURE 45 CIRCUIT
MTPR (dBc)
0
THD
-20
-60dBc
-40
2nd HD
-60
3rd HD
-80
-100
1.995M
2.000M
2.005M
FREQUENCY (Hz)
FIGURE 17. ADSL2+ DMT
9
FIGURE 18. 4MHz HARMONIC DISTORTION vs LOAD
FN6916.0
September 23, 2009
ISL1539A
Typical Performance Curves
VCC = ±12V, RF = 3.2kΩ, GD = 10V/V (differential), RLOAD = 100Ω, TA ≈ +25°C, C0 = C1= IADJ = 0V (full power),
unless otherwise noted.
2.2kΩ
22pF
2.6kΩ
15pF
3.2kΩ
0pF
4.7pF
3.8kΩ
4.6kΩ
FIGURE 19. SMALL SIGNAL FREQUENCY RESPONSE
vs RF
FIGURE 20. SMALL SIGNAL FREQUENCY RESPONSE
vs CLOAD
-40
5VP-P-DIFF
Rs = 84.5Ω
CL = 4.7pF
Rs = 50Ω
CL = 10pF
Rs = 38.4Ω
CL = 15pF
-50
DISTORTION (dBc)
Rs = 26.7Ω
CL = 22pF
THD
-60
-70
2nd HD
-80
-90
3rd HD
-100
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 21. SMALL SIGNAL FREQUENCY RESPONSE
vs CLOAD WITH Rs
FIGURE 22. DISTORTION vs FREQUENCY
VOLTAGE NOISE NV/√Hz
CURRENT NOISE pA/√Hz
100
INVERTING CURRENT NOISE
10
VOLTAGE NOISE
NON-INVERTING CURRENT NOISE
1
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
FIGURE 23. INPUT VOLTAGE AND CURRENT NOISE DENSITY
10
FN6916.0
September 23, 2009
ISL1539A
Typical Performance Curves
VCC = ±12V, RF = 3.2kΩ, GD = 10V/V (differential), RLOAD = 100Ω, TA ≈ +25°C, C0 = 3.3V, C1 = IADJ = 0V
(medium power), unless otherwise noted.
22pF
2.2kΩ
2.6kΩ
15pF
4.7pF
3.2kΩ
0pF
3.8kΩ
4.6kΩ
FIGURE 24. SMALL SIGNAL FREQUENCY RESPONSE
vs RF
FIGURE 25. SMALL SIGNAL FREQUENCY RESPONSE
vs CLOAD
-40
5VP-P-DIFF
-50
Rs = 26.7Ω
CL = 22pF
DISTORTION (dBc)
Rs = 84.5Ω
CL = 4.7pF
Rs = 50Ω
CL = 10pF
Rs = 38.4Ω
CL = 15pF
THD
-60
-70
-80
2nd HD
-90
3rd HD
-100
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 26. SMALL SIGNAL FREQUENCY RESPONSE
vs CLOAD WITH Rs
FIGURE 27. DISTORTION vs FREQUENCY
VOLTAGE NOISE NV/√Hz
CURRENT NOISE pA/√Hz
100
INVERTING CURRENT NOISE
10
VOLTAGE NOISE
NON-INVERTING CURRENT NOISE
1
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 28. INPUT VOLTAGE AND CURRENT NOISE DENSITY
11
FN6916.0
September 23, 2009
ISL1539A
Typical Performance Curves
VCC = ±12V, RF = 3.2kΩ, GD = 10V/V (differential), RLOAD = 100Ω, TA ≈ +25°C, C1= 3.3V, C0 = IADJ = 0V (low
power), unless otherwise noted.
22pF
2.2kΩ
2.6kΩ
15pF
3.2kΩ
3.8kΩ
4.7pF
4.6kΩ
FIGURE 29. SMALL SIGNAL FREQUENCY RESPONSE
vs RF
0pF
FIGURE 30. SMALL SIGNAL FREQUENCY RESPONSE
vs CLOAD
-40
5VP-P-DIFF
-50
Rs = 26.7Ω
CL = 22pF
DISTORTION (dBc)
Rs = 38.4Ω
CL = 15pF
Rs = 84.5Ω
CL = 4.7pF
Rs = 50Ω
CL = 10pF
-60
THD
-70
2nd HD
-80
-90
3rd HD
-100
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 32. DISTORTION vs FREQUENCY
FIGURE 31. SMALL SIGNAL FREQUENCY RESPONSE
vs CLOAD WITH Rs
VOLTAGE NOISE NV/√Hz
CURRENT NOISE pA/√Hz
100
INVERTING CURRENT NOISE
10
VOLTAGE NOISE
NON-INVERTING CURRENT NOISE
1
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 33. INPUT VOLTAGE AND CURRENT NOISE DENSITY
12
FN6916.0
September 23, 2009
ISL1539A
Typical Performance Curves
VCC = ±12V, RF = 3.2kΩ, GD = 10V/V (differential), RLOAD = 100Ω, TA ≈ +25°C, C0 and C1 Parametric, unless
otherwise noted.
-20
-30
FULL POWER
OUTPUT -> OUTPUT REFERRED
PortCD=>PortAB
-40
GAIN (dB)
-50
MEDIUM POWER
-60
PortAB=>PortCD
-70
-80
LOW POWER
-90
-100
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 35. CHANNEL TO CHANNEL X-TALK
FIGURE 34. COMMON MODE SMALL SIGNAL
FREQUENCY RESPONSE
-20
26
-30
±12V
23
-40
-50
17
GAIN (dB)
GAIN (dB)
20
±10V
14
±7.5
11
8
-60
-70
-PSRR
-80
-90
-100
5
2
1M
INPUT REFERRED
+PSRR
-110
10M
100M
-120
100k
1G
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 36. SMALL SIGNAL BANDWIDTH vs SUPPLY
VOLTAGE
FIGURE 37. +PSRR TO DIFFERENTIAL OUTPUT
FULL POWER
1 PORT
MEDIUM LOW POWER
NEGATIVE
NEGATIVE
POSITIVE
LOW POWER
FIGURE 38. SUPPLY CURRENT vs RADJ
13
FN6916.0
September 23, 2009
ISL1539A
Typical Performance Curves
VCC = ±12V, RF = 3.2kΩ, GD = 10V/V (differential), RLOAD = 100Ω, TA ≈ +25°C, IADJ = 0V, C0, C1 varied, unless
otherwise noted.
C0, C1
1V/Div
1V/Div
C0, C1
VOUT
VOUT
2V/Div
2V/Div
40ns/DIV
2µs/DIV
FIGURE 39. POWER-UP TIME
FIGURE 40. POWER-DOWN TIME
0
4.0
POWER DISSIPATION (W)
ISOLATION (dB)
-20
-40
-60
-80
-100
-120
1M
10M
FREQUENCY (Hz)
FIGURE 41. OFF-ISOLATION
14
100M
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
EXPOSED DIEPAD SOLDER TO PCB PER JESD51-5
3.5
3.0
HTSSOP24 = +36°C/W
2.5
2.0
QFN24 = +39°C/W
1.5
1.0
0.5
0
0
25
50
75 85 100
125
AMBIENT TEMPERATURE (°C)
150
FIGURE 42. PACKAGE POWER DISSIPATION vs
AMBIENT TEMPERATURE
FN6916.0
September 23, 2009
ISL1539A
Test Circuit
A
R
NETWORK
ANALYZER
+12
S
DC
SPLITTER
50Ω
487Ω
DUT
180°
SPLITTER
RL
1:1
50Ω
LOAD
53Ω
487Ω
50Ω
-12
FIGURE 43. FREQUENCY RESPONSE CHARACTERIZATION CIRCUIT
15
FN6916.0
September 23, 2009
ISL1539A
Applications Information
Applying Wideband Current Feedback Op
Amps as Differential Drivers
A current feedback amplifier (CFA) like the ISL1539A is
particularly suited to the requirements of high output
power, high full power bandwidth, differential drivers.
This topology offers a very high slew rate on low
quiescent power and the ability to hold relatively
constant AC characteristics over a wide range of gains.
The AC characteristics are principally set by the feedback
resistor value in simple differential gain circuits as shown
in Figure 44.
+12V
Rb
+
¼
ISL1539A
-
SOURCE
VI
Rg 711
-
1:n
VO
Rb
+
LOAD
Rf
3.2k
¼
ISL1539A
Very low output distortion at low power can be provided
by the differential configuration. The high slew rate
intrinsic to the CFA topology also contributes to the
exceptional performance shown in Figures 22, 27 and 32.
These swept frequency distortion plots show extremely
low distortion at 200kHz holding to very low levels up
through 20MHz. At the lowest operating power
(Figure 32, which is at low power, or 6.75mA per
amplifier or 13.5mA/port) we still see < -70dBc through
5MHz for a 5VP-P differential output swing.
Advanced Configurations - Active
Termination
Where the best power efficiency is required in a full
duplex DSL line interface application, it is common to
apply the circuit shown below to reduce the power loss in
the matching element while retaining a higher
impedance for the upstream signal coming into this
output stage. This circuit acts to provide a higher
apparent output impedance (through its cross-coupled
positive feedback through the Rp resistors) while
physically taking a smaller IR drop through the Rm
resistors for the output signal..
Ro
Rf
3.2k
power for Channels A and B together and then the other
pair controls Channels C and D together.
Ro
1 PORT OF 2
DRAWN
AV-DIFF = VO/VI = 10V/V
50Ω
-12V
TYPICAL DIFFERENTIAL I/O LINE DRIVER
(1 OF 2 PORTS)
+12V
¼
ISL1539A
-
FIGURE 44. PASSIVE TERMINATION CIRCUIT
In this differential gain of 10 V/V circuit, the 3.2k
feedback resistors are setting the bandwidth while the
711 gain resistor controls the gain. The Vo/Vi gain for
this circuit is set by Equation 1:
R
Vo
3.2kΩ
= 1+ 2 f = 1+ 2
= 10
Vi
Rg
711Ω
The ISL1539A provides 4 very power efficient, high
output current, CFA's. These are intended to be
connected as two pairs of differential drivers. The pinout
diagrams of page two show that Channels A and B are
intended to operate as a pair while Channels C and D
comprise the other pair. Power control is also provided
through two pairs of control pins which separately set the
16
Vi
POWER
SPLITTER
0V
C0
3.3V
C1
Rf
Vdiff
Rm
Rp
Rg
RL 82.6Ω Vo
Rp
Rm
Rf
RL = 100Ω/(1.1)2 = 82.6
Vo/Vdiff = 9.77 V/V (19.8dB)
¼
ISL1539A
(EQ. 1)
The effect of increasing or decreasing the feedback
resistor value is shown in Figures 19, 24 and 29 (at the 3
power settings). Increasing RF will tend to roll off the
response while decreasing it will peak the frequency
response up extending the bandwidth. RG was adjusted
in each of these plots to hold a constant gain of 10 (or
20dB). This shows the flexibility offered by the CFA
topology - the frequency response can be controlled with
the value of the feedback resistor with the RG resistor
then setting the desired gain.
I = 13.5mA
+
+
50Ω
Radj
0Ω
-12V
FIGURE 45. ACTIVE TERMINATION TEST CIRCUIT
This circuit is showing one of two ports configured in an
active termination circuit used for some of the
specification and characterization tests. This is showing
the device operating in the low power mode, but data
has been shown at the other power settings as well.
The 82.6Ω differential load is intended to emulate a 100Ω
line load reflected through a 1:1.1 turns ratio
transformer (100Ω/(1.12) = 82.6Ω load). The gain and
output impedance for this circuit can be described by the
following equations.
The ideal transfer function is set by the open circuit gain
(RL = infinite) and an equivalent output impedance ZO.
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September 23, 2009
ISL1539A
Vo
RL
= Aoc
Vi
RL + Z o
(EQ. 2)
The goal of the positive feedback resistor, RP, is to
provide some “gain” in the apparent output impedance
over just the 2*RM. It also will act to increase the AOC
over the simple differential gain equation if a synthesis
factor (SF) is defined as shown in Equation 3:
1
SF =
1−
R f − Rm
(EQ. 3)
Rp
We can see this "gain" is achieved by letting RP be > RF
The closer RP is to RF-RM, the more "gain" is achieved
but at the risk of instability. With this SF defined as
shown above, the exact AOC and ZO will be as shown in
Equations 4 and 5:
Aoc = SF (1 + 2
Rf
Rg
+
R f − Rm
Rp
Z o = SF (2 Rm )
)
(EQ. 4)
(EQ. 5)
For test purposes, the circuit shown in Figure 45 was
configured to achieve the following results.
SF = 2.19
AOC = 17.7V/V
ZO = 66Ω
Putting these together into the gain to an 82.6Ω load
gives the following test condition as shown by
Equation 6.
82.6Ω
RL
Vo
⎛V ⎞
= 9.84⎜ ⎟
= Aoc
= 17.7
82.6Ω + 66Ω
RL + Z o
Vi
⎝V ⎠
(EQ. 6)
The advantage offered by this technique is that for
whatever swing we desire at the load, there is less rise
through the physical output matching resistor than if we
simply inserted two 33Ω RM resistors to achieve the 66Ω
output impedance achieved in this test circuit. Whatever
load current is required in RL will rise to the output pins
through 2*RM. The rise from the load swing to the output
pin swing is given by Equation 7:
RL + 2 Rm
RL
(EQ. 7)
This was only 1.36 for the test circuit shown above. In
differential circuits the ±VP at the output pins produces a
4VP for the differential peak-to-peak voltage. Hence a
±10V swing at each output in the above circuit will
17
produce a 40VP-P differential swing which will drop to the
load divided by 1.36 - or a 29.41VP-P differential swing.
Distortion and MTPR
The ISL1539A is intended to provide very low distortion
levels under the demanding conditions required by the
discrete multi-tone (DMT) characteristic of modern DSL
modulations. The standard test for linearity is the MultiTone Power Ratio (MTPR) test where a specified standard
is loaded up with discrete carriers over the specified
frequencies in such a way as to produce the maximum
rated line power and Peak to Average Ratio (PAR) with
some tones missing. The measure of linearity is the
separation from the active tones vs. a missing tone. To
the extent that the amplifier is slightly non-linear, it will
fold a small amount of power into the missing tones
through intermodulation products for the active tones.
Figure 17 shows the circuit operating at the low power
setting used to test ADSL2+ frequency plan and power.
For this test the carriers are spaced at 5kHz.
This -60dBc MTPR is exceptional for the very low 13.5mA
total quiescent current used in this configuration.
Operating at reduced power targets on the line will
improve MTPR as will operating the amplifiers at higher
quiescent current.
The characteristic curves show the exceptional single
tone performance available using the ISL1539A. At the
highest quiescent power, operating at a simple
differential gain of 10V/V, Figure 22 shows the 5VP-P
distortion plot.
Figure 22 shows a better than -80dBc through 8MHz for
the 2nd and 3rd harmonics. The rapid rise in the spurious
above 10MHz is coming from the onset of fine scale slew
limiting effects. By 20MHz, the output signal is requiring
a differential slew rate of 300V/µs - a significant portion
of the available 3000V/µs slew rate available at full
power.
Power Control Function
Figure 46 shows a simplified schematic for the power
control features included in the ISL1539A. Each of the 4
differential pairs shown in the drawing are used to steer
control currents (IBIAS terms) into additional current
mirrors (not shown) that control the quiescent bias
current for each of the two ports. This bias control shares
the IADJ pin. When IADJ is grounded, the typical supply
current levels shown in the “Electrical Specifications”
tables on page 5 are produced. Inserting an external
resistor to ground in the IADJ pin will scale the quiescent
currents down, as shown in Figure 38.
It is also possible to scale the IADJ currents up by tying
the IADJ pin through a resistor to a negative supply. As
long as the resulting voltage divider between this
external negative voltage and the internal +0.4V on the
other side of the 500Ω resistor stays above the
maximum rated negative voltage on the IADJ pin (-1V).
For instance, to double the typical quiescent current
levels, the current in the IADJ pin must be doubled from
its nominal 800µA level. Using a -5V supply through an
FN6916.0
September 23, 2009
ISL1539A
external 2.88kΩ resistor will double the current while
leaving the IADJ pin voltage at approximately -0.4V,
which is well within rated minimum. This approach
should be used with great caution as very high internal
power dissipations can easily be produced. However, it
can be a useful approach to extend operation,
particularly when operating on lower total supply
voltages than the rated typical of ±12V.
+VCC IBIAS IBIAS +VCC
+VCC IBIAS IBIAS +VCC
+3.3V
+3.3V
+3.3V
+3.3V
50k
50k 50k
50k
+1.4V
COAB
+1V
+1.4
V
COCD
C1AB
C1CD
with the output to isolate the phase margin effects of the
capacitor. Figure 20 on page 10 shows the effect of
capacitive load on the differential gain of 10 circuit. With
15pF on each output, we see about 5dB peaking. This will
increase quickly at higher Cloads. If this degree of
peaking is unacceptable, a small series resistor can be
used to improve the flatness as shown in Figure 21.
Output DC Error Model
Often, non-inverting bias current (ibn), inverting bias
current (ibi), and input offset voltage (Vio) are quite low
for typical op amps.
Vio, ibn, ibi can be mapped to output offset both
common and differential mode. Consider the circuit in
Figure 47.
+Vcc
± Vio
RO 500
+
IADJ
±ibn
FIGURE 46. BIAS CONTROL CIRCUIT
The current in RO divides in 1/4 levels to form the bias
current for the 4 pairs of differential switches. Each pair
of switches controls the quiescent current for one port.
For instance, C0AB and C1AB control the quiescent
current for the port constructed from amplifiers A and B.
If both control lines are unconnected externally, the
internal 50kΩ pull-up will switch the differential pairs to
divert the 100µA tail currents into the supply turning off
the amplifiers. Taking both control pins low will pass both
IBIAS lines on into scaling current sources. With IREF
grounded, this will give the typical 27.2mA total
quiescent current for a port shown in the “Electrical
Specification” tables on page 5. Taking C0 high (>2V)
while leaving C1 low (<0.8V) will reduce the current into
a port to a typical 23mA. Taking C1 high, while leaving C0
low will reduce the current in a port to a typical 13.5mA
supply current. Table 2 summarizes the operation modes
for ISL1539A for each port.
Rb
Rf
±ibi
Vcm
Rcm
Vcm ± Vocm ±
Zg
+Vcc Rf
±ibi
Rb
±Vio
+
± ibn
FIGURE 47. DC ERROR MODEL
The output common mode offset voltage (Vo-cm) is
derived from the input common mode voltage (Vi-cm),
as expressed in Equations 8 and 9:
Vicm = ± 2 × ibn × Rcm ± ibn × Rb ± Vio
(EQ. 8)
Vocm = ± Vicm ± Rf × ibi
(EQ. 9)
TABLE 2. POWER MODES OF THE ISL1539A
C1
C0
0
0
IS Full Power Mode
0
1
IS Medium Power Mode
1
0
IS Low Power Mode
1
1
Power-Down
OPERATION
Performance Considerations
Driving Capacitive Loads
All closed loop op amps are susceptible to reduced phase
margin when driving capacitive loads. This shows up as
peaking in the frequency response that can, in extreme
situations, lead to oscillations. The ISL1539A is designed
to operate successfully with small capacitive loads such
as layout parasitics. As the parasitic capacitance
increases, it is best consider a small resistor in series
18
Vodm
The output differential mode offset voltage (Vo-dm) is
derived from the input differential mode voltage (Vi-dm),
as expressed in Equations 10 and 11:
Vidm = ± Δibn × Rb ± ΔVio
(EQ. 10)
2Rf
Vodm = ± Vidm × ⎛ 1 + ----------⎞ ± Δibi × Rf
⎝
Rg ⎠
(EQ. 11)
Example:
Referring to the “Electrical Specification” tables on
page 6:
ibn = 8µA, Δibn = 2µA
ibi = 75µA, Δibi = 35µA
Vio = 8mV, ΔVio = 2mV
FN6916.0
September 23, 2009
ISL1539A
Assuming Rf = 3kΩ, Rg = 333Ω, Rb = 7.5kΩ Rcm = 5kΩ,
the total output offset voltage derived is expressed in
Equation 12:
Vcm = Vocm + 0.5 × Vodm = 434mV
+VS
(EQ. 12)
+
Given the worst case DC errors, 434mV of DC shift will
be at the output reducing the available output swing
slightly. Actual operation should never see this much
shift as the error terms are not completely
independent.
VP
+
-VS
Output Headroom Model
Driving high voltages into heavy loads will require a
careful consideration of the available output swing vs.
load. Figure 48 shows a useful model for predicting the
available output swing. If the output is modeled as ideal
NPN and PNP transistors, the output swing limits can be
described as no load headrooms (VP and VN) and an
equivalent impedance to the supplies (RP and RN)
FIGURE 49. HEADROOM MODEL
For equal bipolar supplies, the available peak output
swing will be given by Equation 13:
Vp =
+VS
+
–
+/-VO
RL
VN
2(Vs − V p − Vn )
R + Rn
1+ p
RL
+
–
Vp =
2(Vs − V p − Vn )
2(11.4 − 2.2)
=
= 15.9V p
R p + Rn
6 .7 Ω + 7 .4 Ω
1+
1+
90Ω
RL
(EQ. 14)
RN
-VS
FIGURE 48. HEADROOM MODEL
The no load headrooms can be found in the “Electrical
Specifications” table on page 5 as 12V - 10.9V = 1.1V
and they are equal to each supply.
The equivalent impedances for this model can be
extracted from the reduced swings shown in the
specification table for the heavier loads. Looking at the
typical 60Ω load swings, we see a +9.8V and -9.7V
swing. Solving for the two resistors in the Headroom
model shown in Figure 48 gives:
Rp = 6.7Ω and Rn = 7.4Ω.
For the differential configuration, Figure 49 shows the
Headroom model that can be used to predict the
maximum available swing for a given supply voltage and
load resistor, RL.
19
(EQ. 13)
For example, to worst case the typical gain of 10 design
using ±12V supplies with ±5% supply tolerance and a
minimum expected load of 90Ω, a maximum VP can be
calculated as shown in Equation 14:
RP
VP
RL
The minimum VP-P would be twice this, or 31.8VP-P.
While this extreme condition would normally not be
encountered, it does show the importance of knowing
your minimum expected load for high output swing
conditions.
Output Noise Model
The full differential output noise model for the ISL1539A
should include the 3 input noise terms for each device as
well as the noise contributions due to the external
resistors.
This necessarily becomes an involved model due to the
number of terms, but if the terms that are the same on
each side of the differential circuit can be assumed to be
equal, it will simplify considerably. The noise model
shown in Figure 50 includes all of the op amp terms and
resistor terms. This model is directed at calculating the
differential output spot noise for different values of the
resistors in the simple differential gain circuit. It is
assuming each amplifier term is independent and
uncorrelated to the other terms.
FN6916.0
September 23, 2009
ISL1539A
RS
4kTR S
Board Design Recommendations
eN
iN
RF
ii
4kTR F
4kT
RG
RG
RF
ii
RS
4kTR S
iN
The feedback resistors need to be placed as close as
possible to the output and inverting input pins to
minimize parasitic capacitance in the feedback loop. This
includes the RF and RP resistors in the active termination
configuration. Keep the gain resistor also very close to
the inverting inputs for its port and minimize parasitic
capacitances to ground or power planes as well.
+
-
eO(nV Hz )
4kTR F
+
eN
FIGURE 50. OUTPUT NOISE MODEL
In Figure 50, the circle sources are noise voltages while
the diamonds are noise currents and 4kT is 1.6E - 20J.
If the op amp terms are assumed to be equal for the two
sides of the circuit and two RF and RS resistors are also
equal, and the differential gain is defined as
Ad = 1+2RF/RG, the differential output noise expression
becomes Equation 15.
( )(
) ( ) + 2 A (4kTR )
eo = 2 Ad2 en2 + (in Rs )2 + 4kTRs + 2 ii R f
2
d
f
(EQ. 15)
Putting in numbers for the gain of 10 characterization
circuit (with RS = 50Ω) gives a differential output noise of
eo = 69nV/√Hz. Dividing this by the differential gain of 10
gives an input noise of ei = 6.9nV/√Hz which is only
slightly more than the RMS sum of the two 4nV input
voltage noise terms for the op amps themselves
(5.7nV/√Hz).
20
Close placement of the supply decoupling capacitors
will minimize parasitic inductance in the supply path.
High frequency load currents are typically pulled
through these capacitors so close placement of 0.01µF
capacitors on each of the supply pins will improve
dynamic performance. Higher valued capacitors, 6.8µF
typically, can be placed further from the package as
they are providing more of the low frequency
decoupling.
The thermal pad for the ISL1539A should be connected
to either ground or the -VS power plane. The choice of
which plane depends on which one would have the
more accessible thermal area.
While the ISL1539A is relatively robust in driving
parasitic capacitive loads, it is always preferred to get
into any series output resistor needed in the design as
physically close as possible to the output pins. Then
trace capacitance on the other side of that resistor will
have a much smaller effect on loop phase margin.
Protection devices that are intended to steer large load
transients away from the ISL1539A output stage and
into the power supplies or ground should have a short
trace from their supply connections into the nearest
supply capacitor - or should include their own supply
capacitors to provide a low impedance path under fast
transient conditions.
FN6916.0
September 23, 2009
ISL1539A
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
9/23/09
FN6916.0
CHANGE
Initial Release.
Products
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FN6916.0
September 23, 2009
ISL1539A
Package Outline Drawing
L24.4x5B
24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 10/06
4.00
PIN 1
A
2.50
24X0.40
PIN #1 INDEX AREA
CHAMFER 0.400
× X 45°
INDEX AREA
B
6
20
24
6
1
0.50
19
5.00
3.50
0.5x6=3.00 REF
7
13
12
0.10
8
0.25±0.05
4X
0.50
TOP VIEW
0.10 M C A B
0.5x4=2.00 REF
BOTTOM VIEW
SEE DETAIL X''
0.10 C
C
SEATING PLANE
0.08 C
0.90±0.10
(24x0.25)
SIDE VIEW
(4.80 TYP)
(3.50)
(20x0.50)
0 . 20 REF
5
C
(24x0.60)
(2.50)
(3.80 TYP)
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.20mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
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FN6916.0
September 23, 2009
ISL1539A
HTSSOP (Heat-Sink TSSOP) Family
0.25 M C A B
D
MDP0048
A
HTSSOP (HEAT-SINK TSSOP) FAMILY
(N/2)+1
N
MILLIMETERS
SYMBOL 14 LD 20 LD 24 LD 28 LD 38 LD
PIN #1 I.D.
E
E1
1
0.20 C B A
2X
N/2 LEAD TIPS
(N/2)
TOP VIEW
B
D1
EXPOSED
THERMAL PAD
E2
TOLERANCE
A
1.20
1.20
1.20
1.20
1.20
Max
A1
0.075
0.075
0.075
0.075
0.075
±0.075
A2
0.90
0.90
0.90
0.90
0.90
+0.15/-0.10
b
0.25
0.25
0.25
0.25
0.22
+0.05/-0.06
c
0.15
0.15
0.15
0.15
0.15
+0.05/-0.06
D
5.00
6.50
7.80
9.70
9.70
±0.10
D1
3.2
4.2
4.3
5.0
7.25
Reference
E
6.40
6.40
6.40
6.40
6.40
Basic
E1
4.40
4.40
4.40
4.40
4.40
±0.10
E2
3.0
3.0
3.0
3.0
3.0
Reference
e
0.65
0.65
0.65
0.65
0.50
Basic
L
0.60
0.60
0.60
0.60
0.60
±0.15
L1
1.00
1.00
1.00
1.00
1.00
Reference
N
14
20
24
28
38
Reference
BOTTOM VIEW
Rev. 3 2/07
NOTES:
0.05
e
C
H
1. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusions or gate burrs shall not exceed 0.15mm per
side.
2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm per side.
SEATING
PLANE
3. Dimensions “D” and “E1” are measured at Datum Plane H.
0.10 M C A B
b
0.10 C
N LEADS
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
SIDE VIEW
SEE DETAIL ‚Äö
c
END VIEW
L1
A A2
GAUGE
PLANE
0.25
L
A1
0¬¨¬
DETAIL X
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
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23
FN6916.0
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