SiHF6N40D Datasheet

SiHF6N40D
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Vishay Siliconix
D Series Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V) at TJ max.
• Optimal Design
- Low Area Specific On-Resistance
- Low Input Capacitance (Ciss)
- Reduced Capacitive Switching Losses
- High Body Diode Ruggedness
- Avalanche Energy Rated (UIS)
• Optimal Efficiency and Operation
- Low Cost
- Simple Gate Drive Circuitry
- Low Figure-of-Merit (FOM): Ron x Qg
- Fast Switching
• Compliant to RoHS Directive 2011/65/EU
450
RDS(on) max. at 25 °C ()
VGS = 10 V
1.0
Qg max. (nC)
18
Qgs (nC)
3
Qgd (nC)
4
Configuration
Single
D
TO-220 FULLPAK
Note
* Pb containing terminations are not RoHS compliant, exemptions
may apply
G
G D S
APPLICATIONS
S
• Consumer Electronics
- Displays (LCD or Plasma TV)
• Server and Telecom Power Supplies
- SMPS
• Industrial
- Welding
- Induction Heating
- Motor Drives
• Battery Chargers
N-Channel MOSFET
ORDERING INFORMATION
Package
Lead (Pb)-free
TO-220 FULLPAK
SiHF6N40D-E3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
Drain-Source Voltage
Gate-Source Voltage
LIMIT
VDS
400
VGS
Gate-Source Voltage AC (f > 1 Hz)
Continuous Drain Current (TJ = 150 °C)e
SYMBOL
VGS at 10 V
TC = 25 °C
TC = 100 °C
Pulsed Drain Currenta
ID
IDM
Linear Derating Factor
± 30
UNIT
V
30
6
4
A
13
0.24
W/°C
Single Pulse Avalanche Energyb
EAS
104
mJ
Maximum Power Dissipation
PD
30
W
TJ, Tstg
- 55 to + 150
°C
Operating Junction and Storage Temperature Range
Drain-Source Voltage Slope
TJ = 125 °C
Reverse Diode dV/dtd
Soldering Recommendations (Peak Temperature)
for 10 s
dV/dt
24
0.48
300c
V/ns
°C
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature.
b. VDD = 50 V, starting TJ = 25 °C, L = 2.3 mH, Rg = 25 , IAS = 9.5 A.
c. 1.6 mm from case.
d. ISD  ID, starting TJ = 25 °C.
e. Limited by maximum junction temperature.
S12-0687-Rev. A, 02-Apr-12
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Document Number: 91501
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHF6N40D
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Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum Junction-to-Ambient
RthJA
-
65
Maximum Junction-to-Case (Drain)
RthJC
-
4.1
UNIT
°C/W
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage (N)
VDS
VGS = 0 V, ID = 250 μA
400
-
-
V
VDS/TJ
Reference to 25 °C, ID = 250 μA
-
0.53
-
V/°C
VGS(th)
VDS = VGS, ID = 250 μA
3
-
5
V
Gate-Source Leakage
IGSS
VGS = ± 30 V
-
-
± 100
nA
Zero Gate Voltage Drain Current
IDSS
VDS = 400 V, VGS = 0 V
-
-
1
VDS = 320 V, VGS = 0 V, TJ = 125 °C
-
-
10
μA
-
0.85
1.0

gfs
VDS = 50 V, ID = 3 A
-
1.7
-
S
Input Capacitance
Ciss
311
-
Coss
-
38
-
Reverse Transfer Capacitance
Crss
VGS = 0 V,
VDS = 100 V,
f = 1 MHz
-
Output Capacitance
-
7
-
Effective output capacitance, energy
relateda
Co(er)
-
44
-
Effective output capacitance, time
relatedb
Co(tr)
-
54
-
-
9
18
-
3
-
-
4
-
Drain-Source On-State Resistance
Forward Transconductance
RDS(on)
VGS = 10 V
ID = 3 A
Dynamic
pF
VGS = 0 V,
VDS = 0 V to 320 V
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
Turn-On Delay Time
td(on)
-
12
24
tr
VDD = 400 V, ID = 3 A,
VGS = 10 V, Rg = 9.1 
-
11
22
-
14
28
-
8
16
f = 1 MHz, open drain
-
1.9
-
-
-
6
-
-
24
-
-
1.2
-
236
-
ns
-
1.1
-
μC
-
9
-
A
Rise Time
Turn-Off Delay Time
VGS = 10 V
td(off)
Fall Time
tf
Gate Input Resistance
Rg
ID = 3 A, VDS = 320 V
nC
ns

Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Current
ISM
Diode Forward Voltage
VSD
Reverse Recovery Time
trr
Reverse Recovery Charge
Qrr
Reverse Recovery Current
IRRM
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
TJ = 25 °C, IS = 3 A, VGS = 0 V
TJ = 25 °C, IF = IS = 3 A,
dI/dt = 100 A/μs, VR = 20 V
S
V
Notes
a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDS.
b. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDS.
S12-0687-Rev. A, 02-Apr-12
2
Document Number: 91501
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHF6N40D
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Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
15 V
14 V
13 V
12 V
11
11 V
V
10 V
9V
8V
7V
6V
BOTTOM 5 V
3
TOP
12
9
TJ = 25 °C
RDS(on), Drain-to-Source
On Resistance (Normalized)
ID, Drain-to-Source Current (A)
15
6
3
2.5
2
1.5
1
VGS = 10 V
0.5
0
0
5
10
15
20
25
ID = 3 A
0
- 60 - 40 - 20 0
30
VDS, Drain-to-Source Voltage (V)
Fig. 4 - Normalized On-Resistance vs. Temperature
Fig. 1 - Typical Output Characteristics
1000
10
15 V
14 V
13 V
12 V
11 V
10 V
9V
8V
7V
BOTTOM 6 V
8
6
TJ = 150 °C
ġ
Capacitance (pF)
ID, Drain-to-Source Current (A)
TOP
4
Ciss
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds Shorted
ġ
Crss = Cgd
ġ
Coss = Cds + Cgd
100
ġ
Coss
10
ġ
Crss
2
5V
0
0
5
10
15
20
1
25
0
30
VDS, Drain-to-Source Voltage (V)
50
100
150
200
250
300
350
400
VDS, Drain-to-Source Voltage (V)
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 2 - Typical Output Characteristics
24
VGS, Gate-to-Source Voltage (V)
16
ID, Drain-to-Source Current (A)
20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
12
8
TJ = 150 °C
4
TJ = 25 °C
VDS = 320 V
VDS = 200 V
VDS = 80 V
20
16
12
8
4
0
0
0
5
10
15
20
0
25
VGS, Gate-to-Source Voltage (V)
Fig. 3 - Typical Transfer Characteristics
S12-0687-Rev. A, 02-Apr-12
4
8
12
16
Qg, Total Gate Charge (nC)
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
3
Document Number: 91501
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHF6N40D
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Vishay Siliconix
6
5
TJ = 150 °C
10
ID, Drain Current (A)
ISD, Reverse Drain Current (A)
100
TJ = 25 °C
1
0.1
4
3
2
1
VGS = 0 V
0
0.01
0.2
0.4
0.6
0.8
1
1.2
1.4
25
1.6
VSD, Source-Drain Voltage (V)
75
100
125
150
TJ, Case Temperature (°C)
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 9 - Maximum Drain Current vs. Case Temperature
100
500
IDM = Limited
475
VDS, Drain-to-Source
Brakdown Voltage (V)
ID, Drain Current (A)
50
Limited by RDS(on)*
10
100 μs
Operation in this Area
Limited by RDS(on)
1
TC = 25 °C
TJ = 150 °C
Single Pulse
400
10 ms
350
- 60 - 40 - 20 0
10
100
1000
VDS, Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
Fig. 8 - Maximum Safe Operating Area
Normalized Effective Transient
Thermal Impedance
425
375
BVDSS Limited
0.1
1
1 ms
450
Fig. 10 - Temperature vs. Drain-to-Source Voltage
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.02
0.05
Single Pulse
0.01
0.0001
0.001
0.01
0.1
1
Pulse Time (s)
Fig. 11 - Normalized Thermal Transient Impedance, Junction-to-Case
S12-0687-Rev. A, 02-Apr-12
4
Document Number: 91501
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHF6N40D
www.vishay.com
Vishay Siliconix
RD
VDS
QG
10 V
VGS
D.U.T.
RG
QGS
+
- VDD
QGD
VG
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
Charge
Fig. 12 - Switching Time Test Circuit
Fig. 16 - Basic Gate Charge Waveform
Current regulator
Same type as D.U.T.
VDS
90 %
50 kΩ
12 V
0.2 µF
0.3 µF
+
10 %
VGS
D.U.T.
td(on)
td(off) tf
tr
-
VDS
VGS
3 mA
Fig. 13 - Switching Time Waveforms
IG
ID
Current sampling resistors
Fig. 17 - Gate Charge Test Circuit
L
Vary tp to obtain
required IAS
VDS
D.U.T
RG
+
-
IAS
V DD
10 V
0.01 Ω
tp
Fig. 14 - Unclamped Inductive Test Circuit
VDS
tp
VDD
VDS
IAS
Fig. 15 - Unclamped Inductive Waveforms
S12-0687-Rev. A, 02-Apr-12
5
Document Number: 91501
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHF6N40D
www.vishay.com
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
•
•
•
•
+
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
ISD
Ripple ≤ 5 %
Note
a. VGS = 5 V for logic level devices
Fig. 18 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91501.
S12-0687-Rev. A, 02-Apr-12
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Document Number: 91501
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
Vishay Siliconix
TO-220 FULLPAK (HIGH VOLTAGE)
A
E
A1
ØP
n
d1
d3
D
u
L1
V
L
b3
A2
b2
c
b
e
MILLIMETERS
DIM.
A
A1
A2
b
b2
b3
c
D
d1
d3
E
e
L
L1
n
ØP
u
v
ECN: X09-0126-Rev. B, 26-Oct-09
DWG: 5972
MIN.
4.570
2.570
2.510
0.622
1.229
1.229
0.440
8.650
15.88
12.300
10.360
INCHES
MAX.
4.830
2.830
2.850
0.890
1.400
1.400
0.629
9.800
16.120
12.920
10.630
MIN.
0.180
0.101
0.099
0.024
0.048
0.048
0.017
0.341
0.622
0.484
0.408
13.730
3.500
6.150
3.450
2.500
0.500
0.520
0.122
0.238
0.120
0.094
0.016
2.54 BSC
13.200
3.100
6.050
3.050
2.400
0.400
MAX.
0.190
0.111
0.112
0.035
0.055
0.055
0.025
0.386
0.635
0.509
0.419
0.100 BSC
0.541
0.138
0.242
0.136
0.098
0.020
Notes
1. To be used only for process drawing.
2. These dimensions apply to all TO-220, FULLPAK leadframe versions 3 leads.
3. All critical dimensions should C meet Cpk > 1.33.
4. All dimensions include burrs and plating thickness.
5. No chipping or package damage.
Document Number: 91359
Revision: 26-Oct-09
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definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council
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requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference
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Revision: 02-Oct-12
1
Document Number: 91000