DATASHEET

ACTS161MS
Radiation Hardened
4-Bit Synchronous Counter
January 1996
Features
Pinouts
• Devices QML Qualified in Accordance with MIL-PRF-38535
• Detailed Electrical and Screening Requirements are Contained in
SMD# 5962-96716 and Intersil’s QM Plan
16 PIN CERAMIC DUAL-IN-LINE
MIL-STD-1835, DESIGNATOR CDIP2-T16,
LEAD FINISH C
TOP VIEW
• 1.25 Micron Radiation Hardened SOS CMOS
MR 1
16 VCC
• Single Event Upset (SEU) Immunity: <1 x 10-10 Errors/Bit/Day
(Typ)
CP 2
15 TC
P0 3
14 Q0
• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm2/mg
P1 4
13 Q1
• Dose Rate Upset . . . . . . . . . . . . . . . . >1011 RAD (Si)/s, 20ns Pulse
P2 5
12 Q2
P3 6
11 Q3
PE 7
10 TE
• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)
• Dose Rate Survivability . . . . . . . . . . . >1012 RAD (Si)/s, 20ns Pulse
• Latch-Up Free Under Any Conditions
9 SPE
GND 8
• Military Temperature Range . . . . . . . . . . . . . . . . . . -55oC to +125oC
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
16 PIN CERAMIC FLATPACK
MIL-STD-1835, DESIGNATOR CDFP4-F16,
LEAD FINISH C
TOP VIEW
• Input Logic Levels
- VIL = 0.8V Max
- VIH = VCC/2 Min
• Input Current ≤ 1µA at VOL, VOH
MR
1
16
VCC
CP
2
15
TC
Description
P0
3
14
Q0
P1
4
13
Q1
The Intersil ACTS161MS is a Radiation Hardened 4-Bit Binary Synchronous
Counter, featuring asynchronous reset and load ahead carry logic. The MR is
an active low master reset. SPE is an active low Synchronous Parallel Enable
which disables counting and allows data at the preset inputs (P0 - P3) to load
the counter. CP is the positive edge clock. TC is the terminal count or carry
output. Both TE and PE must be high for counting to occur, but are irrelevant
to loading. TE low will keep TC low.
P2
5
12
Q2
P3
6
11
Q3
PE
7
10
TE
GND
8
9
• Fast Propagation Delay . . . . . . . . . . . . . . . . 25ns (Max), 16ns (Typ)
SPE
The ACTS161MS utilizes advanced CMOS/SOS technology to achieve
high-speed operation. This device is a member of a radiation hardened,
high-speed, CMOS/SOS Logic family.
The ACTS161MS is supplied in a 16 lead Ceramic Flatpack (K suffix) or
a Ceramic Dual-In-Line Package (D suffix).
Ordering Information
PART NUMBER
TEMPERATURE RANGE
SCREENING LEVEL
PACKAGE
5962F9671601VEC
-55oC to +125oC
MIL-PRF-38535 Class V
16 Lead SBDIP
5962F9671601VXC
-55oC to +125oC
MIL-PRF-38535 Class V
16 Lead Ceramic Flatpack
ACTS161D/Sample
25oC
Sample
16 Lead SBDIP
ACTS161K/Sample
25oC
Sample
16 Lead Ceramic Flatpack
ACTS161HMSR
25oC
Die
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
1
518893
File Number 4095
Spec Number
ACTS161MS
Functional Diagram
P0
P1
3
P2
4
P3
5
6
Q0 Q1
Q2 Q3
7
PE
10
TE
TE
TE
9
SPE
1
MR
P
T0
D0 Q0
P
T1
MR
GND
D1 Q1
P
T2
MR
CP
D2 Q2
P
T3
MR
CP
D3 Q3
MR
CP
CP
2
CP
14
13
Q0
12
Q1
11
Q2
15
Q3
TC
TRUTH TABLE
INPUTS
OPERATING MODE
OUTPUTS
MR
CP
PE
TE
SPE
PN
QN
TC
Reset (Clear)
L
X
X
X
X
X
L
L
Parallel Load
H
X
X
I
I
L
L
H
X
X
I
h
H
(Note 1)
Count
H
h
h
h (Note 3)
X
count
(Note 1)
Inhibit
H
X
I (Note 2)
X
h (Note 3)
X
qN
(Note 1)
H
X
X
I (Note 2)
h (Note 3)
X
qN
L
H = High Steady State, L = Low Steady State, h = High voltage level one setup time prior to the Low-to-High clock transition, I = Low voltage level one setup time prior to the Low-to-High clock transition, X = Don’t Care,q = Lower case letters indicate the state of the referenced
output prior to the Low-to-High clock transition,
= Low-to-High Transition.
NOTES:
1. The TC output is High when TE is High and the counter is at Terminal Count (HHHH).
2. The High-to-Low transition of PE or TE should only occur while CP is High for conventional operation.
3. The Low-to-High transition of SPE should only occur while CP is High for conventional operation.
Spec Number
2
518893
ACTS161MS
Die Characteristics
DIE DIMENSIONS:
88 mils x 88 mils
2240mm x 2240mm
METALLIZATION:
Type: AlSi
Metal 1 Thickness: 7.125kÅ ±1.125kÅ
Metal 2 Thickness: 9kÅ ±1kÅ
GLASSIVATION:
Type: SiO2
Thickness: 8kÅ ±1kÅ
WORST CASE CURRENT DENSITY:
< 2.0 x 105A/cm2
BOND PAD SIZE:
110µm x 110µm
4.3 mils x 4.3 mils
Metallization Mask Layout
ACTS161MS
CP
(2)
MR
(1)
VCC
(16)
TC
(15)
P0 (3)
(14) Q0
P1 (4)
(13) Q1
P2 (5)
(12) Q2
P3 (6)
(11) Q3
(7)
PE
(8)
GND
(9)
SPE
(10)
TE
Spec Number
3
518893
ACTS161MS
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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FAX: (886) 2 2715 3029
Spec Number
4
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