dm00071167

AN4213
Application note
High-frequency ballast 2x58 W (T8 fluorescent tubes)
based on a PowerFLAT™ 5x6 package
By Santina Leo
Introduction
Fluorescent lamps are increasingly driven by electronic rather than electromagnetic ballasts
mainly because fluorescent lamps can produce around 20% more light for the same input
power when driven above 20 kHz instead of 50/60 Hz. Operation at high frequency also
eliminates both light flickering and audible noise.
This application note describes the design calculations and test results of the STEVALILB010V1demonstration board able to drive 2x58 W linear T8 fluorescent tubes. The
electronic ballast consists of two sections: a power factor correction pre-regulator (PFC),
using the L6562A, and the lamp ballast stage with the L6569. The main purpose of this
application note is to evaluate the electrical features of the new PowerFLAT™ 5x6 package
and to compare its thermal results with that of the DPAK package. The PowerFLAT™5x6
package is used in the STEVAL-ILB010V1 demonstration board shown below.
Figure 1. STEVAL-ILB010V1
AM17315v1
May 2014
DocID023984 Rev 2
1/42
www.st.com
Contents
AN4213
Contents
1
System description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
PFC section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
Designing a TM PFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1
Input specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.3
Power section design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.4
4
5
3.3.1
Bridge rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3.2
Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3.3
Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3.4
Boost inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3.5
Power MOSFET selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3.6
Boost diode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
L6562A biasing circuitry (pin by pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DC/AC converter and lamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.1
Bootstrap circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.2
Lamp requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.2.1
Output inductor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.2.2
Lamp preheating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Driving optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.1
Power MOSFET circuit optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6
DC/AC converter waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7
Experimental results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Appendix A Board description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Appendix B Bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2/42
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AN4213
Contents
Appendix C Layout layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
DocID023984 Rev 2
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List of figures
AN4213
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
4/42
STEVAL-ILB010V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Boost converter circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Inductor current waveform and Power MOSFET timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
PFC electrical schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Pin 1, 2: Feedback network implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Sense resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Multiplier setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
ZCD resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Optimum Power MOSFET turn-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Boost PFC section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DC/AC converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Preheating circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Lamp output voltage timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Lamp output voltage during preheating phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Lamp output voltage during ignition phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Lamp output voltage during run-mode phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Driving network optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Turn-off detail with Rg=220 Ω, speed off diode and Csn= 47 pF @ 230 VAC . . . . . . . . . . . . . . . 29
Turn-off detail with Rg=220 Ω, speed off diode and Csn=100 pF @ 230 VAC . . . . . . . . . . . . . . 29
Turn-on detail with Rg= 220 Ω, speed off diode and Csn = 47 pF @ 230 VAC. . . . . . . . . . . . . . 29
Turn-on detail with Rg= 220 Ω, speed off diode and Csn= 100 pF @ 230 VAC . . . . . . . . . . . . . 29
Turn-off detail with Rg =47 Ω, no speed off diode and Csn = 47 pF @ 230 VAC . . . . . . . . . . . . 30
Turn-off detail with Rg = 47 Ω, no speed off diode and Csn = 100 pF @ 230 VAC . . . . . . . . . . 30
Turn-on detail with Rg = 47 Ω, no speed off diode and Csn = 47 pF @ 230 VAC . . . . . . . . . . . 30
Turn-on detail with Rg = 47 Ω, no speed off diode and Csn = 100 pF @ 230 VAC . . . . . . . . . . 30
STL13N60M2 during steady-state operation in half-bridge section @ 230 VAC . . . . . . . . . 32
STL13N60M2 during turn-off in half-bridge section @230VAC (detail) . . . . . . . . . . . . . . . . 32
STL13N60M2 during turn-on in half-bridge section @230VAC (detail) . . . . . . . . . . . . . . . . 33
Electrical schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Bottom layout layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Top layout layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Silkscreen top . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Silkscreen bottom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
DocID023984 Rev 2
AN4213
System description
Figure 2. Block diagram
Cin
PFC
AC
Co
Load
400Vdc
Converter
DC/AC
EMI
Filter
1
System description
AM17316v1
The electronic ballast consists of two sections: a power factor correction pre-regulator
(PFC), using the L6562A, and the lamp ballast stage with the L6569.
The power factor correction section is based on the L6562A. This is a current-mode PFC
controller operating in transition mode (TM). It is especially designed for electronic lamp
ballast applications (to better understand the L6562A characteristics, refer to AN2761).
The lamp ballast stage is based on the L6569 which is a high-voltage half-bridge driver with
a built-in oscillator. The load consists of an L-C series resonant circuit with the lamps
connected across the capacitors. This topology allows operating in zero-voltage switching,
to reduce the transistor switching losses and the electromagnetic interference generated by
the output wiring of the lamp.
DocID023984 Rev 2
5/42
PFC section
2
AN4213
PFC section
The power factor correction circuit reshapes the distorted input current waveform to
approximate a sinusoidal current that is in phase with the input voltage. It is an index which
measures the efficiency of the energy transfer from an AC source to a generic load.
The input power factor (PF) is defined as the ratio of the real power (transferred to the
output) over apparent power (see Equation 1).
Equation 1
PF =
I V cos φ I rms1
Re alPower
= rms rms
*
= K d cos φ
ApparentPower
I rmsV rms
I rmsT
where:
Kd =
I rms1
I rms
is a distortion factor and cos∅ is the phase angle between input ac voltage and the
fundamental current.
Two typical techniques used to achieve a sinusoidal input current waveform with low
distortion are passive correction and active correction. Passive PFC techniques shape the
input current waveform by using a passive input filter consisting of inductors and capacitors.
Because it operates at the line frequency, 50 or 60 Hz passive filters require relatively large
fixed-value inductors and capacitors to reduce the low-frequency harmonic currents. It is
difficult to achieve near unity power factor with passive filters. Also, very large currents may
circulate in the filter. However the passive filter is an effective PFC solution where the line
frequency line voltage and load are relatively constant.
An active PFC performs very well and is significantly smaller and lighter than the passive
PFC circuit. The active PFC circuits operate at a higher switching frequency than the line
frequency to allow a large reduction in the size and cost of passive filter elements.
A typical active PFC circuit using switching techniques, located between the rectifier bridge
and the filter capacitor, allows drawing a quasi-sinusoidal current from the mains, in phase
with the line voltage.
The boost circuit-based PFC topology is the most popular. The boost PFC circuit is a cheap
solution to comply with the regulations. It can be implemented with a boost inductor, a
controlled power switch, a catch diode, an output capacitor and, obviously, a control
circuitry. (See Figure 3).
The boost inductor in the boost PFC circuit is in series with the AC power line. Therefore the
input current does not pulsate, minimizing conducted EMI at the line. This allows the size of
the EMI filter and the conductors in the input circuit to be reduced. This topology accepts a
wide input voltage range without an input voltage selector switch.
The output voltage of a boost PFC circuit should be higher than the peak value of the
maximum input voltage.
6/42
DocID023984 Rev 2
AN4213
PFC section
Figure 3. Boost converter circuit
L
Io
ID
IL
IQ
Ic
Q
Co
Cin
Load
Controller
AC
AM17317v1
The boost converter can operate in two modes: discontinuous conduction mode (DCM) and
continuous conduction mode (CCM).
Discontinuous conduction mode is when the Power MOSFET of the boost converter is
turned on when the inductor current reaches zero after a dead time and turned off when the
inductor current meets the input reference voltage. In this way, the input current waveform
follows the input voltage one, therefore obtaining a power factor close to 1. DCM is suitable
for power levels of 300 W or less. DCM uses larger cores and has higher I²R and skin-effect
losses due to the larger inductor current swing. With the increased swing a larger input filter
is also required. On the positive side, since in the discontinuous mode the Power MOSFET
switches on when the inductor current is at zero, there is no reverse-recovery current (IRR)
specification required on the boost diode. This means that less expensive diodes can be
used.
Continuous conduction mode (CCM) is when the current in the energy transfer inductor
never reaches zero during the switching cycle. The Power MOSFET starts conducting when
the current through itself is not zero. Continuous conduction mode (CCM) is suitable for high
power ratings (>300 W). The voltage swing is less than in DCM resulting in lower I²R losses
and the lower ripple current results in lower inductor core losses. Less voltage swing also
reduces EMI and allows for a smaller input filter to be used. Unfortunately, since the Power
MOSFET is not being turned on when the current of the inductor is at zero, a very fast
reverse-recovery diode is required to keep losses to a minimum.
Transition conduction mode which is typically used in lighting applications represents a good
cost-benefit compromise. In the transition mode approach, the switch-on time is held
constant during the line cycle and the switch is turned on when the inductor current falls to
zero, so that the converter operates at the boundary between continuous and discontinuous
conduction mode. In this way, the freewheeling diode is turned off softly (no recovery losses)
and the switch is turned on at zero current, so the commutation losses are reduced. Besides
the simplicity and the few external parts required, this system minimizes the inductor size
due to the low inductance value needed. On the other hand, the high current ripple on the
inductor involves high RMS current and high noise on the rectified main bus, which needs a
heavier EMI filter to be rejected. These drawbacks limit the use of the TM PFC in a lower
power range (typically below 200 W).
DocID023984 Rev 2
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PFC section
AN4213
The principle scheme is shown in Figure 4. The instantaneous input current is constituted by
a sequence of triangles whose peaks are proportional to the line voltage. Thus, the average
input current becomes proportional to the line voltage without duty-cycle modulation during
the line cycle.
In this application note boost topology working in transition mode is considered.
Figure 4. Inductor current waveform and Power MOSFET timing
ILpk
I SW
IL
ID
IAC
ON
MOSFET
OFF
AM17318v1
8/42
DocID023984 Rev 2
AN4213
Designing a TM PFC
3
Designing a TM PFC
3.1
Input specification
The first consideration for designing a new boost PFC converter is a detailed specification of
the operating conditions of the circuit that is needed for the calculation.
In this example a 116 W, single-input range mains PFC circuit has been considered.
Table 1. Specified parameters
Converter specification data and fixed parameters
Symbol
Description
Values
185 VAC
VAC(min)
Mains voltage range
VAC(max)
fl
265 VAC
Minimum mains frequency
47 Hz
POUT
Rated output power
116 W
VOUT
Regulated DC output voltage
400 V
η=POUT/PIN
PF
Expected efficiency
90%
Expected power factor
0.99
The L6562A integrates an OVP in order to prevent excessive output voltage that can
overstress the output components and the load.
•
Maximum output overvoltage:
ΔVOVP = 40V
The PFC minimum switching frequency is one of the main parameters used to dimension
the boost inductor. The switching frequency at low mains on the top of the sinusoid and at
full load conditions has been considered. It must be higher than the audio bandwidth in
order to avoid audible noise and it must not interfere with the L6562A minimum internal
starter period. On the other hand, if the minimum frequency is set too high, the circuit shows
excessive losses at a higher input voltage. The typical minimum frequency range is 20 - 50
kHz.
•
Minimum switching frequency (kHz):
f SW min = 35kHz
In order to properly select the power components of the PFC, the maximum operating
ambient temperature around the PFC circuitry must be known. The designer must take into
consideration that it is the temperature at which the PFC components are working and not
the maximum external operating temperature of the entire equipment.
•
Maximum ambient temperature (°C):
Tambx = 50°C
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9/42
Designing a TM PFC
3.2
AN4213
Operating conditions
The first step is to define the main parameters of the circuit as follows:
•
Rated DC output current:
Equation 2
POUT 116
=
= 0.29 A
VOUT 400
I OUT =
•
Maximum input power:
Equation 3
PIN =
•
POUT
η
=
116
= 129W
0. 9
RMS input current:
Equation 4
I IN =
•
PIN
129
=
= 0 .7 A
V AC min ∗ PF 185 ∗ 0 .99
Peak inductor current:
Equation 5
I Lpk = 2 2 ∗ I IN = 1.97 A
•
RMS inductor current:
Equation 6
2
I LRMS =
•
3
∗ I IN = 0.8 A
AC inductor current:
Equation 7
I LAC =
2
2
I LRMS
− I IN
= 0.38 A
The current flowing into the inductor can be divided in two parts depending on the instant of
conduction. During the on time, it increases from zero up to its peak value and flows in the
switch, otherwise during the off time the current decreases from its peak down to zero and it
flows into the diode. Therefore, in order to calculate the losses of these two elements, it is
useful to know the RMS current which flows into the switch and into the diode.
•
RMS switch current:
Equation 8
I SWRMS = I Lpk
10/42
1 4 2 V AC min
−
*
= 0.51A
6 9π
VOUT
DocID023984 Rev 2
AN4213
Designing a TM PFC
•
RMS diode current:
Equation 9
4 2 V AC min
*
= 0.59 A
9π
VOUT
I DRMS = I Lpk
3.3
Power section design
3.3.1
Bridge rectifier
The input rectifier bridge can use standard, slow-recovery, low-cost devices. Typically a
600 V device is selected in order to have a good margin against mains surges.
Equation 10
I INRMS =
2 * I IN
= 0.49 A
2
Equation 11
I IN − avg =
2 * I IN
π
= 0.31 A
The power dissipated on the bridge is calculated using Equation 12:
Equation 12
2
PBRIDGE = 4 * RDIODE * I INRMS
+ 4 * VTH * I IN − avg
where RDIODE and Vth are given in the technical datasheet.
3.3.2
Input capacitor
The input capacitor has to attenuate the switching noise due to the high-frequency inductor
current ripple. The worst condition happens on the peak of the minimum rated input voltage
(VINmin=185 V).
The maximum high-frequency voltage ripple across CIN is usually imposed between 5% and
20% of the minimum rated input voltage.
This is expressed by a coefficient r (from 0.05 to 0.2) as an input design parameter.
•
Ripple voltage coefficient (%):
r = 0.2
Taking into account a minimum half-bridge switching frequency of 35 kHz and an output
power of 116 W, the input capacitor can be determined by the following equation.
Equation 13
C IN =
I IN
2π * f SW min * r * V AC min
C IN =
0.7
= 0.086 μF
2 * 3 .14 * 35 * 0.2 * 185
DocID023984 Rev 2
11/42
Designing a TM PFC
AN4213
CIN has been selected equal to 150 nF.
Of course a bigger capacitor provides a benefit in terms of EMI, but on the other hand
worsens the THD, mainly at high mains voltage. For this reason the right trade-off is needed
in order to have the best performance. A good quality film capacitor must be selected in
order to provide good filtering effectiveness.
3.3.3
Output capacitor
The selection of the output bulk capacitor COUT depends on the DC output voltage, the
allowable overvoltage and the converter output power. With these values, the output
capacitor can be calculated using the following equation:
Equation 14
COUT ≥
4πf main
POUT
116
=
≥ 49 μF
* VOUT * ΔVOUT 4π * 47 * 400 * 10
To obtain the smallest possible ripple and good reliability, a commercial capacitor of 56μF,
450 V has been selected.
3.3.4
Boost inductor
In the transition mode control, the inductor value needs to be calculated to start the next
switching cycle at zero current. The boost inductor determines the operating frequency of
the converter. First, the inductance value must be defined. The inductance (L) is usually
determined so that the minimum switching frequency is greater than the maximum
frequency of the L6562A internal starter, in order to ensure correct TM operation.
Assuming unity PF, it is possible to write:
Equation 15
t on (V AC ,ϑ ) =
L * I Lpk * sin ϑ
2 * V AC * sin ϑ
=
L * I Lpk
2 * VAC
Equation 16
t off (V AC ,ϑ ) =
L * I Lpk * sin ϑ
VOUT − 2 * VAC * sin ϑ
Ton and Toff are, respectively, the ON-time and the OFF-time of the Power MOSFET, ILpk is
the maximum peak inductor current in a line cycle and θ is the instantaneous line phase in
the interval (0, π).
The instantaneous switching frequency in a line cycle is given by Equation 17:
Equation 17
(
2
V AC
* VOUT − 2 * VAC * sin ϑ
1
1
f SW (V AC , ϑ ) =
=
*
t on + t off
VOUT
2 L * PIN
12/42
DocID023984 Rev 2
)
AN4213
Designing a TM PFC
The switching frequency is minimum at the top of the sinusoid
π


ϑ =  sin ϑ = 1
2


and it is maximum at the zero-crossing of the line voltage (ϑ=0,π = sinϑ=0) where
toff = 0 μs.
The absolute minimum frequency fSWmin can occur at either the maximum VACmax or the
minimum mains voltage VACmin, so the inductor value is calculated by the formula:
Equation 18
L (V AC ) =
(
2
V AC
* VOUT − 2 * V AC
2
)
where VAC can be either VACmin or VACmax, whichever gives the lower value for L.
The values of the inductor at low mains and at high mains, respectively L(VACmax) and
L(VACmin) are given by following equations:
Equation 19
L(V AC max ) =
Equation 20
L (V AC min ) =
(
)
(
)
(
)
(
)
2
V AC
2 * V AC min
185 2 * 400 − 2 * 185
min * VOUT −
 L(V AC max ) =
= 1.36mH
2 * f SW min * PIN * VOUT
2 * 35 * 10 3 * 129 * 400
2
VAC
2 * VAC max
265 2 * 400 − 2 * 265
max * VOUT −
 L (V AC max ) =
= 0 .51mH
2 * f SW min * PIN * VOUT
2 * 35 * 10 3 * 129 * 400
At this point the minimum value has to be taken into account. It becomes the maximum
inductance value for PFC dimensioning.
For this application a 0.5 mH boost inductance has been selected.
3.3.5
Power MOSFET selection
The main switch selection is driven by the amount of allowable power dissipation. It is
important to choose a device that minimizes gate charge and capacitance and minimizes
the sum of switching and conduction losses at a given frequency.
The breakdown voltage is fixed just by the output voltage, plus the allowable overvoltage
and a safety margin.
The conduction losses are given by:
Equation 21
PCOND = RDSon * ( I SWrms (VAC )) 2
DocID023984 Rev 2
13/42
Designing a TM PFC
AN4213
where, as given in Equation 8:
1 4 2 V AC min
−
*
6 9π
VOUT
I SWrms = I Lpk
The switching losses in the Power MOSFET occur only at turn-off because of TM operation
and can be expressed by:
Equation 22
Pswitch (V AC ) =
Q gd * VOUT * I Lrms
2I g
f SW (I Lrms )
This equation represents the crossing between the Power MOSFET current that decreases
linearly during the fall time and the voltage on the Power MOSFET drain that increases. In
fact during the fall time the current of the boost inductor flows into the parasitic capacitance
of the Power MOSFET, charging it. For this reason switching losses depend on the total
drain capacitance.
At turn-on the losses are due to the discharge of the total drain capacitance inside the
Power MOSFET itself.
The capacitive losses are given by:
Equation 23
PCAP (V AC ) =
1
2
C d * VMOS
* f SW (V AC )
2
Where Cd is the total drain capacitance and VMOS is the drain voltage at Power MOSFET
turn-on.
Based on the above considerations, the Power MOSFET device selected is the
STL13N60M2. This device is an N-channel Power MOSFET developed using a new
generation of MDmesh II PlusTM low Qg. This revolutionary Power MOSFET associates a
vertical structure to the company's strip layout to yield one of the world's lowest onresistance and gate charge. This choice is confirmed by the good electrical performance
and thermal behavior.
3.3.6
Boost diode selection
A fast-recovery boost diode is used. The value of its DC and RMS current (see Equation 9),
useful for the calculation of the losses, are both:
Equation 24
I D = I OUT = 0.29 A
The conduction losses can be estimated as follows:
Equation 25
2
PDON = Vth * I D + Rd * I DRMS
Where, Vth (threshold voltage) and Rd (differential resistance) are parameters of the diode.
14/42
DocID023984 Rev 2
AN4213
Designing a TM PFC
The breakdown voltage is fixed by the same criterion as the Power MOSFET. A minimum
breakdown voltage of 1.2*(VOUT - ΔVOVP) and a current rating higher than 3*IOUT, can be
chosen for a rough initial selection of the rectifier.
In this 116 W application an STTH1L06 (600 V, 1 A) has been selected.
From the STTH1L06 datasheet, Vth is 0.89V and Rd is 0.165 Ω, therefore substituting these
values in Equation 25, we have:
PDON = 0.89V * 0.29 A + 0.165Ω * (0.59 A)2 = 0.315W
3.4
L6562A biasing circuitry (pin by pin)
This section explains the dimensioning of the biasing circuitry pin-by-pin.
For reference, the relevant components have been highlighted in the figure below.
Figure 5. PFC electrical schematic
Vin(Vac)
400Vdc
NTC
Rzcd
Rmulth
Rm
Routh
+
AC
Ccomp
Cc
1
INV
ZCD
COMP
GND
MULT
GD
6
2
3
ultl
Rmultl
4
5
CS
V CC
7
8
Routll
Rsense
AM17319v1
DocID023984 Rev 2
15/42
Designing a TM PFC
AN4213
Pin 1, 2: feedback network implementation
Figure 6. Pin 1, 2: Feedback network implementation
HV
ROUTH
1
2
3
INV
ZCD
COMP
GND
ROUTL
6
L6562A
MULT
5
GD
4
7
8
CS
V CC
AM17320v1
Pin 1 (INV): Inverting input of the error amplifier. The information on the output voltage of
the PFC pre-regulator is fed into this pin through a resistor divider (ROUTH and ROUTL). The
internal reference on the non-inverting input is 2.5 V (typ), while the DIS intervention
threshold is 27 μA. ROUTH and ROUTL are then selected as follows:
Equation 26
R OUTH =
ΔV OVP
= 1480kΩ
27 μA
Equation 27
ROUTH VOUT
R
=
− 1 = 159  ROUTL = OUTH = 9.3kΩ
ROUTL 2.5V
159
The commercial selected values are two resistors in series each 680 kΩ for ROUTH and
ROUTL equal to 8.2 kΩ.
Pin 2 (COMP): Output of the error amplifier. A compensation network is placed between this
pin and INV (pin 1) in order to achieve stability of the voltage control loop and ensure high
power factor and low THD. It has to be designed with a narrow bandwidth in order to avoid
that the system rejects the output voltage ripple that would bring high distortion of the input
current waveform. Setting a bandwidth (BW) from 20 to 30 Hz, CCOMP (as shown in
Figure 6) can be calculated as follows:
Equation 28
CCOMP =
16/42
1
≅ 1μF
2π (R OUTH IIROUTL ) ∗ BW
DocID023984 Rev 2
AN4213
Designing a TM PFC
Pin 4 (CS): input to the PWM comparator
Figure 7. Sense resistor
HV
1
5
INV
2
COMP
GND
L6562A
3
MULT
4
ZCD
CS
6
7
GD
V CC
8
Rsense
AM17321v1
The current flowing in the Power MOSFET is sensed through a resistor, the resulting voltage
is applied to this pin and compared with an internal sinusoidal-shaped reference, generated
by the multiplier, to determine Power MOSFET turn-off. The Power MOSFET stays in the
OFF-state until the PWM latch is reset by the ZCD signal.
The sense resistor value can be calculated as follows:
Equation 29
RS ≤
VCS min
≤ 0.502Ω
I Lpk
Where:
•
•
ILpk is the maximum peak current in the inductor, equal to 1.99 A
VCSmin = 1 V is the minimum voltage allowed on the L6562A current sense (given in the
datasheet).
For this project the selected commercial value for RS is 0.47Ω.
Using this value and considering the maximum voltage VCSmax = 1.16 V allowed on the
L6562A (as given in the datasheet), the maximum peak of the inductor current can be
calculated as follows:
Equation 30
I Lpkx =
VCS max
= 2.5 A
RS
The calculated ILpkx is the saturation inductor current and it is used for calculating the
winding number of the inductor and its air gap.
DocID023984 Rev 2
17/42
Designing a TM PFC
AN4213
Pin 3 (MULT): main input to the multiplier.
Figure 8. Multiplier setting
Vin(Vac)
RMULTH
1
5
ZCD
INV
2
COMP
GND
L6562A
3
MULT
6
7
GD
4
8
CS
V CC
RMULTL
AM17322v1
This pin is connected to the rectified mains voltage via a resistor divider and provides the
sinusoidal reference to the current loop.
The multiplier can be described by the relationship:
Equation 31
VCS = K (VCOMP − 2.5V ) ∗ VMULT
Where:
•
VCS (multiplier output) is the reference for the current sense
•
K = 0.38 (typ) is the multiplier gain
•
VCOMP is the voltage on pin 2
•
VMULT is the voltage on pin 3
First, the maximum peak value for VMULTmax is selected. This value has to be selected in
the range from 0 up to 3 V. Typically, it should be less than 3 V in case of single mains
Equation 32
VMULTpk max =
I Lpk ∗ RS
1.1
∗
V AC max 1.99 ∗ 0.47 265
=
∗
= 1.21V
V AC min
1.1
185
where 1.1 V is the multiplier maximum slope which is given in the datasheet.
18/42
DocID023984 Rev 2
AN4213
Designing a TM PFC
In this way, the resistor divider will be such that
Equation 33
kp =
RMULTL
V
1.21
= MULT max =
= 3.24 ∗ 10 −3
RMULTL + RMULTH
2V AC max 1.41 ∗ 265
supposing a 200 μA current flowing into the multiplier divider, RMULTL is calculated as
follows:
Equation 34
R MULTL =
V MULT
1.21
=
= 6.2 kΩ
200 μA 200 ∗ 10 − 6
Taking into account this value and from Equation 33:
Equation 35
RMULTH =
1− KP
RMULTL = 1.9 MΩ
KP
The selected values are RMULTL = 8.2 kΩ and RMULTH = 2 MΩ
Pin 5 (ZCD): zero-current detection
Figure 9. ZCD resistor
Vin(Vac)
RMULTH
1
5
ZCD
INV
2
GND
COMP
L6562A
3
MULT
6
7
GD
4
8
CS
V CC
RMULTL
AM17323v1
The zero-current detection (ZCD) block switches the external Power MOSFET on as the
voltage across the boost inductor reverses, just after the current through the boost inductor
has gone to zero. This feature allows transition mode operation. The ZCD pin is connected
to the auxiliary winding of the inductor boost through a limiting resistor.
DocID023984 Rev 2
19/42
Designing a TM PFC
AN4213
The maximum main-auxiliary winding turn ratio, nmax, has to ensure that the voltage
delivered to the pin during the OFF-time of the Power MOSFET is sufficient to arm the ZCD
circuit.
Equation 36
n≤
n primary
nsec ondary
≤
VOUT − 2V AC max
 n ≤ 15.7
1.4 ∗ 1.15
The minimum value of the limiting resistor can be found assuming 0.8 mA current through
the pin and considering the maximum voltage across the auxiliary winding with a selected
turn ratio n = 10. The actual value can be fine-tuned in order to make the turn-on of the
Power MOSFET occur exactly on the valley of the drain voltage oscillation (the boost
inductor, completely discharged, is ringing with the drain capacitance, as shown in the figure
below). This will minimize the power dissipation at turn-on.
Figure 10. Optimum Power MOSFET turn-on
Vdrain
Vout
Vipk
Vzcd
t
5.7
1.4
0.7
t
AM17324v1
Equation 37
Vout
400
− VZCDH
− 5. 7
R1 = n
= 10
= 42.9kΩ
0.8mA
0.8mA
Equation 38
R2 =
20/42
2V AC max
− VZCDL
n
=
0.8mA
2 ∗ 265
−0
10
= 46.8kΩ
0.8mA
DocID023984 Rev 2
AN4213
Designing a TM PFC
where VZCDH = 5.7 V (typ) and VZCDL = 0 (typ) are given in the datasheet. We consider the
highest value, for this reason the selected limiting resistor is RZCD = 47 kΩ. The complete
boost PFC schematic is given in the following figure.
Figure 11. Boost PFC section
R17
R18
D5
400Vdc
L2
D1
Fuse
AC
C1
L1
C20
NTC
D2
R25
R20
R16
R26
C3
D12
1
INV
ZCD
COMP
GND
MULT
GD
2
3
R2
D3
C6
C7
R27
C19
4
5
R5
+
R7
6
CS
V CC
7
C23
R4
8
R22
C24
D4
C25
R9
+
AM17325v1
DocID023984 Rev 2
21/42
DC/AC converter and lamp
4
AN4213
DC/AC converter and lamp
The DC/AC converter uses a half-bridge voltage-fed topology with two Power MOSFETs
driven by the L6569 driver. It is a high-voltage half-bridge driver with an oscillator inside.
Here below is the complete electrical schematic of DC/AC inverter in half-bridge topology:
Figure 12. DC/AC converter
+ 400Vdc
Cboot
PTC
Csn
1
2
RF
3
4
Vs
BOOT
RF
HVG
L6569
CF
OUT
GND
LVG
8
LAMP
6
5
LAMP
CF
DC
L3
7
L4
+
PTC
AM17326v1
Voltage-fed series resonant half-bridge inverters are currently used for fluorescent lamps.
This topology makes easy to operate in zero-voltage switching (ZVS) resonant mode,
dramatically reducing transistor switching losses and the electromagnetic interference. This
type of inverter can operate up to 150 kHz in ZVS mode. For this project, the frequency has
been selected between 50 and 100 kHz, specifically ƒrun ≈ 57 kHz.
The frequency of the internal oscillator can be programmed using an external circuitry
composed of a resistor RF and a capacitor CF. The nominal oscillator frequency can be
calculated using the following Equation 39:
Equation 39
fOSC =
1
1
=
= 57kHz
2 ∗ RF ∗ CF ln 2 1.3863 ∗ RF ∗ CF
From the above equation, imposing CF=560 pF, RF will be equal to 22 kΩ.
4.1
Bootstrap circuit
The bootstrap block is needed to supply the high-voltage section. This function is normally
accomplished by a high-voltage fast-recovery diode. The L6569 has an internal bootstrap
circuit that replaces the external diode. The bootstrap capacitor (CBOOT) is charged every
time the low-side driver is on and the output pin is below the supply voltage (VDD) of the
gate driver. The bootstrap capacitor is discharged only when the high-side switch is turned
on. This bootstrap capacitor is the supply voltage (VBS) for the high circuit section.
22/42
DocID023984 Rev 2
AN4213
DC/AC converter and lamp
The first parameter to take into account is the maximum voltage drop that we have to
guarantee when the high-side switch is in the on state. The maximum allowable voltage
drop (VBOOT) depends on the minimum gate drive voltage (for the high-side switch) to
maintain. If VGSMIN is the minimum gate-source voltage, the capacitor drop must be:
Equation 40
ΔVBOOT = VDD − VF − VGSMIN
where:
•
VDD is supply voltage of the gate driver [V];
•
VF is the bootstrap diode forward-voltage drop [V].
The value of the bootstrap capacitor is calculated by:
Equation 41
CBOOT =
QTOTAL
Δ VBOOT
Where, QTOTAL is the total amount of the charge supplied by the capacitor. The total charge
supplied by the bootstrap capacitor is calculated using Equation 42:
Equation 42
QTOTAL = QGATE + (I LKCAP + I LKGS + I QBS + I LK + I LKDIODE ) ∗ tON + QLS
Where:
•
QGATE is the total gate charge
•
ILKCAP is the bootstrap capacitor leakage current
•
ILKGS is the switch gate-source leakage current
•
IQBS is the bootstrap circuit quiescent current
•
ILK is the bootstrap circuit leakage current
•
ILKDIODE is the bootstrap diode leakage current
•
TON is the high-side switch-on time
•
QLS is the charge required by the internal level shifter, which is set to 3 nC for all HV
gate drivers.
The capacitor leakage current is important only if an electrolytic capacitor is used, otherwise
this can be neglected. Recommended values for the bootstrap capacitor are within the
range of 100 nF~570 nF, but the right value must be selected according to the application in
which the device is used. When the capacitor value is too large, the bootstrap charging time
slows and the low-side on-time might be not long enough to reach the bootstrap voltage. For
this project the selected value is 100 nF/400 V. The output drivers drive an external Nchannel Power MOSFET. The internal logic ensures a deadtime (typ 1.25 μs) to avoid crossconduction of the power devices. The selected power device is STL13N60M2.
DocID023984 Rev 2
23/42
DC/AC converter and lamp
AN4213
4.2
Lamp requirements
4.2.1
Output inductor design
The output inductor should be designed to allow a sufficient peak ignition current without
saturating. This is important as the ballast will be unable to ignite if it cannot deliver sufficient
voltage to the lamp.
The ignition current depends on the type of the lamp being used and must be kept to a
minimum by ensuring that the cathodes are sufficiently preheated. To minimize eddy current
losses in the inductor, multi-stranded wire for the windings should be used. It is important to
have a large enough air gap to produce the highest available peak current before allowing
the inductor to saturate. When the cores are hot, the saturation point and hence the peak
current for the inductor will be lower, therefore a poorly designed inductor may result in the
ballast failing to ignite the lamp during an attempted hot re-strike. The value of the output
inductor is given by following equation:
Equation 43
L=
4.2.2
Vin2η
f run 2π 2 Prun
Lamp preheating
It is essential that the lamp be sufficiently preheated before ignited. In order to achieve the
maximum possible lamp life, it is necessary to heat the cathodes to the correct temperature
before ignition. Accelerated deterioration occurs if lamps are ignited when the cathodes are
either not sufficiently heated or overheated. The preheating of the cathodes allows an easy
strike of the lamp, reducing ignition voltage. During preheating time the lamp is
characterized by high impedance and the current flows through the filament. Its resistance
value is strictly dependent on the lamp model. Typically these filaments show an initially low
value (a few ohms) that will increase by 5 times during the preheating. One method to obtain
the preheating cathodes is to adopt a PTC resistor. Figure 13 shows its typical connection.
Figure 13. Preheating circuit
C’’res
C’res
PTC
Lres
Cres
AM17327v1
24/42
DocID023984 Rev 2
AN4213
DC/AC converter and lamp
At startup when the PTC is cold, it can be considered as a short-circuit, the circuit operating
frequency is determined by C’res and Lres (we can neglect Cres). During the preheating the
current flows through the PTC and C’res heats both the cathodes and the PTC at the same
time. The value of C’res must be chosen in order to avoid high voltage on the lamp and
consequent switch-on. When the PTC is hot (end of preheating) its resistance increases
until it can be considered as an open circuit. In this case the current flows through the series
formed by C’’res and C’res. Therefore the equivalent capacitance across the lamp becomes
lower than the initial value, increasing the capacitive reactance and allowing the tube
ignition. We can summarize the turn-on sequence in three phases: preheating, ignition and
normal lamp operation. The preheating of the lamp filaments is achieved by a high switching
frequency fPRE, to ensure that a current flows in the filaments without lamp ignition. In fact
the initial voltage applied across the lamp is below the strike potential. The duration of the
preheating period tPRE is set by the capacitor C’res together with Lres. The choice of this
time is strictly dependent on the lamp type. The ignition sequence begins after tPRE. During
the ignition phase, the frequency shifts from fMAX to fMIN (that is the normal operation
frequency) in a period TSH. The voltage across the lamp increases causing the ignition. At
the end of the ignition time the frequency reaches the normal operation value, fMIN, and the
lamp is in run mode (as shown in Figure 14).
Figure 14. Lamp output voltage timing diagram
Frequency
Tpre
Tsh
Trun
Normal Operation
Ignition Phase
fmax
fmin
fmin
Ignition Ramp
Vign
Vph
Vrun
Vlamp
time
Preheat
Ignition
Run
AM17328v1
The following figures indicate the preheating, ignition and run mode phases, respectively.
DocID023984 Rev 2
25/42
DC/AC converter and lamp
AN4213
Figure 15. Lamp output voltage during preheating phase
Preheating phase
Ilamp
Vlamp
Vlamp
AM17329v1
Figure 16. Lamp output voltage during ignition phase
Ignition phase
Ilamp
Vlamp
Vlamp
Ilamp
AM17330v1
26/42
DocID023984 Rev 2
AN4213
DC/AC converter and lamp
Figure 17. Lamp output voltage during run-mode phase
Run mode phase
Ilamp
Vlamp
Ilamp
Vlamp
AM17331v1
DocID023984 Rev 2
27/42
Driving optimization
5
AN4213
Driving optimization
A driving network optimization has been performed with the main purpose to have thermal
and dynamic behavior of the devices compliant to the features of the system.
5.1
Power MOSFET circuit optimization
Here below is the electrical schematic concerning the driving circuit of the Power MOSFET.
Figure 18. Driving network optimization
HV
R
D
Rg
Csn
Rsense
AM17332v1
An RC snubber network, R = 180 Ω and Csn=47 pF, has been inserted in order to avoid a
voltage spike and voltage oscillation across the Power MOSFET during its turn-off.
Furthermore, limiting the rise slope of the Power MOSFET voltage, ΔVDS/ΔT, the cross
between voltage and current is also reduced resulting in less switching losses during turnoff. On the other hand, a too high value involves a peak on the current during turn-on. So a
right trade-off has to be found in order to balance the switching losses during turn-off and
turn-on and to have the best performance of the device.
28/42
DocID023984 Rev 2
AN4213
Driving optimization
The driving circuit, Rg = 220 Ω and the diode D, allows the Power MOSFET to not have turnon too quickly, reducing the discharge of snubber capacitor and consequently guaranteeing
negligible switch-on losses and thanks to the diode, it allows the fastest discharge of
parasitic capacitance of the Power MOSFET and therefore speeds up the switch-off.
A comparison has been performed between two different driving networks in order to find
the best solution. The following figures show the waveforms of various conditions.
Figure 19. Turn-off detail with Rg=220 Ω, speed Figure 20. Turn-off detail with Rg=220 Ω, speed
off diode and Csn= 47 pF @ 230 VAC
off diode and Csn=100 pF @ 230 VAC
Vgs
Vgs
Vds
Id
Id
Vds
Eoff
Eoff
AM17333v1
AM17334v1
Figure 21. Turn-on detail with Rg= 220 Ω, speed Figure 22. Turn-on detail with Rg= 220 Ω, speed
off diode and Csn = 47 pF @ 230 VAC
off diode and Csn= 100 pF @ 230 VAC
Vgs
Vgs
Vds
Vds
Eon
Id
Eon
AM17335v1
DocID023984 Rev 2
Id
AM17336v1
29/42
Driving optimization
AN4213
Figure 23. Turn-off detail with Rg =47 Ω, no
speed off diode and Csn = 47 pF @ 230 VAC
Figure 24. Turn-off detail with Rg = 47 Ω, no
speed off diode and Csn = 100 pF @ 230 VAC
Vgs
Vgs
V ds
Id
Vds
Id
Eoff
Eoff
AM17337v1
Figure 25. Turn-on detail with Rg = 47 Ω, no
speed off diode and Csn = 47 pF @ 230 VAC
AM17338v1
Figure 26. Turn-on detail with Rg = 47 Ω, no
speed off diode and Csn = 100 pF @ 230 VAC
Vgs
Vgs
Vds
Vds
Id
Eon
Eon
AM17339v1
30/42
DocID023984 Rev 2
Id
AM17340v1
AN4213
Driving optimization
Here below is the summary table, in terms of dissipated energy during both turn-on and
turn-off detail.
Table 2. Summary table of dissipation energy
Driving conditions
Eon (µJ)
Eoff (µJ)
Etot (µJ)
Rg=220 Ω, speed off diode, Csn= 47 pF
1.27
6.39
7.66
Rg=220 Ω, speed off diode, Csn= 100 pF
2.05
6.22
8.72
Rg=220 Ω, no speed off diode, Csn= 47 pF
1.25
12.46
13.71
Rg=220 Ω, no speed off diode, Csn= 100 pF
1.66
10.56
12.22
As Table 2 shows, the best compromise in terms of switching losses, is to have a smaller
snubber capacitor, Csn = 47 pF, in order to reduce the peak on the drain current during turnon (as shown in Figure 21) and Rg = 220 Ω with speed off diode in order to speed up the
device turn-off (as shown in Figure 19.). In fact a greater Rg provides a slower switch-on of
the Power MOSFET, reduces the snubber capacitor discharge, guaranteeing negligible
power losses during turn-on.
DocID023984 Rev 2
31/42
DC/AC converter waveforms
6
AN4213
DC/AC converter waveforms
The figures below depict the waveforms during steady-state operation and turn-off and turnon detail related to the DC/AC converter stage which adopts a half-bridge voltage-fed
topology. The device is STL13N60M2 which works at ~57 kHz.
Figure 27. STL13N60M2 during steady-state operation in half-bridge section
@ 230 VAC
Vgs
Vds
Id
AM17341v1
Figure 28. STL13N60M2 during turn-off in half-bridge section @230VAC (detail)
Vgs
Vds
Id
AM17342v1
32/42
DocID023984 Rev 2
AN4213
DC/AC converter waveforms
Figure 29. STL13N60M2 during turn-on in half-bridge section @230VAC (detail)
Vgs
Vds
Id
AM17343v1
It’s clear that the device has good performance in the half-bridge section. In fact, the cross
during turn-off (see Figure 28) is very low, resulting in low power dissipation.
DocID023984 Rev 2
33/42
Experimental results
7
AN4213
Experimental results
The experimental results have been measured with different input voltages and leaving the
board exposed to room temperature (25 °C). The devices have been kept soldered on the
PCB. Temperature has been detected using an infrared thermal camera pointed on the
package of the devices. The test equipment used is provided below as well as the test
conditions:
•
Input voltage: 185 VAC - 230 VAC - 265 VAC
•
Test equipment:
•
–
Agilent AC power source/analyzer 6813B
–
Flir system thermal camera
–
LeCroy 64Xi-A oscilloscope
–
LeCroy active current probe CP030
–
LeCroy active differential voltage probe ADP305
Ambient temperature: 25°C.
The table below shows electrical and thermal results obtained with both packages, DPAK
and PowerFLAT™ 5x6, at different input voltages.
Table 3. Main electrical and thermal results @ 25 °C ambient temperature
lin(A)
Power
factor
THD (%)
Pin (W)
THB (°C)
TPFC
(°C)
0.576
0.997
∼ 7.5
106
70
64.2
STL13N60M2
(PowerFLAT™ 5x6)
0.569
0.997
∼ 7.2
104.9
71.9
67
STD13N60M2
(DPAK)
0.465
0.995
∼ 8.1
106.4
71
66.5
0.456
0.994
∼8
104.4
72
69
0.404
0.991
∼9
106.3
71.8
70.4
0.395
0.99
∼ 8.5
103.9
72.2
73
Device
VIN(V)
STD13N60M2
(DPAK)
185
230
STL13N60M2
(PowerFLAT™ 5x6)
STD13N60M2
(DPAK)
265
STL13N60M2
(PowerFLAT™ 5x6)
Changing input voltage, the main electrical parameters of the PFC and THD suggest that
the application performances are very good. The temperatures of the two packages are not
so different and the devices work within safety conditions.
34/42
DocID023984 Rev 2
AN4213
8
Conclusion
Conclusion
The proposed design of the electronic ballast has shown the capability of the demonstration
board to drive 2x58 W fluorescent lamps with very good electrical and thermal performance.
The choice of components and the optimization of the power devices guarantee the highest
PF and lowest THD.
The main purpose of this exercise was to evaluate the electrical and thermal features of the
PowerFLAT™ 5x6 compared to the DPAK package. The PowerFLAT™ 5x6 package
showed comparable thermal results. For both package options the temperature is fully
compliant with the absolute maximum rating limit in the datasheet specification.
DocID023984 Rev 2
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AC
L1
C20
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D3
D4
C3
D2
R2
DocID023984 Rev 2
C19
C6
R26
R25
L2
4
3
2
1
CS
MULT
COMP
INV
R20
L6562A
U3
R24
R18
8
7
6
5
+
C25
C24
V CC
GD
GND
ZCD
R5
D12
R4
R9
Q1
D13
C23
R27
NTC
R7
R22
C7
R16
+
C22
C13 +
D7
D6
C8
R11
R10
4
3
2
1
GND
CF
RF
Vs
C11
L6569
U4
LVG
OUT
HVG
BOOT
5
6
7
8
R13
R19
C19
Q4
Q3
C21
L4
L3
C14
C11
LAMP
LAMP
PTC
C15
C12
PTC
R14
R15
C16
Appendix A
C1
Fuse
D1
R17
Board description
AN4213
Board description
Figure 30. Electrical schematic
AM17344v1
AN4213
Bill of material
Appendix B
Bill of material
Table 4. Board bill of material
Reference
Qty
Value/part number
Description
R2/R22
2
8.2 kΩ/0.25 W
RC07
R4
1
56 kΩ
SMD 1206
R20
1
47 kΩ/0.25 W
RC07
R5
1
220 kΩ
SMD 1206
R7/R16
2
680 kΩ/0.25 W
RC07
R9
1
0.47 kΩ/0.5 W
RC07
R10
1
22 kΩ/0.25 W
RC07
R11/R28
2
100 kΩ/2 W
RC07
R13/R19
2
47 kΩ
SMD 1206
R17/R18
2
270 kΩ/0.25 W
RC07
R24
1
10 kΩ/0.25 W
RC07
R25/R26
2
1 MΩ/0.5 W
RC07
R27
1
180 kΩ/0.25 W
RC07
C1/C20
2
220 nF/305 VAC
X2 Metallized polypropylene capacitor
C3
1
150 nF/630 VDC
Plastic capacitor
C6
1
10 nF/100 VDC
Metallized polyester capacitor
C7
1
56 μF/450 V
Electrolytic capacitor
C8
1
560 pF/50 V
Ceramic capacitor
C9
1
100 nF/400 VDC
Polyester capacitor
C16
1
100 nF/630 VDC
Polyester capacitor
C10
1
560 pF/500 VDC
Ceramic capacitor
C11/C14
2
15 nF/630 VDC
Metallized polypropylene capacitor
C12/C15
2
22 nF/630 VDC
PHE450 film capacitor
C13
1
22 μF/50 V
Electrolytic capacitor
C19
1
1 μF/100 V
Polyester capacitor
C21
1
2.2 nF/1000 V
Ceramic capacitor
C22
1
100 nF/100 VDC
Polyester capacitor
C23
1
47 nF/500 VDC
Ceramic capacitor
C24
1
220 nF/100 V
Metallized polyester capacitor
C25
1
10 μF/>25 V
Electrolytic capacitor
D1/D2/D3/D4
4
1N4007
DO-41
D13
1
SWTTH1RL06
ST DO-41
DocID023984 Rev 2
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Bill of material
AN4213
Table 4. Board bill of material (continued)
38/42
Reference
Qty
Value/part number
Description
D6
1
1N4148
DO-35
D8/D9
2
Omitted
D12
1
LL4148
SMD 1406
D7
1
Zener 16 V
DO-41
PTC
2
600 Ω/120 °C
TDK/EPC B59884C0120A070
NTC
1
2.5 Ω
TDK/EPC B57236S0259M0
FUSE
1
1.6 A/250 V
Serie TR5
L1
1
2x10mH/1A
Magnetica: common mode inductor
code: 02106 class code:1045.0017
L2
1
500 μH/0.81A
Magnetica: PFC inductor
code: 06535 class code:2216.0001
L3/L4
2
1.5 mH/0.6A/2A pk
Magnetica: Ballast inductor
code: 07056 class code:1956.0007
Q1/Q2/Q3
3
STL13N60M2
N-channel 600 V, 0.39 Ω typ., 7 A MDmesh II
Plus™ low Qg Power MOSFET in a
PowerFLAT™ 5x6 HV package
U3
1
L6562A
ST PFC driver SO-8
U4
1
L6569
ST HB driver SO-8
DocID023984 Rev 2
AN4213
Appendix C
Layout layers
Layout layers
Figure 31. Bottom layout layer
AM17345v1
Figure 32. Top layout layer
AM17346v1
Figure 33. Silkscreen top
AM17347v1
Figure 34. Silkscreen bottom
AM17348v1
DocID023984 Rev 2
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Reference
9
AN4213
Reference
1.
40/42
AN2761 application note
DocID023984 Rev 2
AN4213
10
Revision history
Revision history
Table 5. Document revision history
Date
Revision
31-Jul-2013
1
Initial release.
2
–
–
–
–
12-May-2014
Changes
Updated: Section 6
Updated: Figure 27, 28, 29 and Table 3
Updated: Table 4
Minor text changes
DocID023984 Rev 2
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AN4213
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