dm00047102

AN4043
Application note
SLLIMM™-nano
small low-loss intelligent molded module
By Carmelo Parisi and Giovanni Tomasello
Introduction
In recent years the variable speed motor control market has required high performance
solutions able to satisfy the increasing energy saving requirements, compactness, reliability,
and system costs in home appliances, such as dish washers, refrigerator compressors, air
conditioning fans, draining and recirculation pumps, and in low power industrial applications,
such as small fans, pumps and tools, etc. To meet these market needs, STMicroelectronics
has developed a new family of very compact, high efficiency, dual-in-line intelligent power
modules, with optional extra features, called small low-loss intelligent molded module nano
(SLLIMM™-nano).
The SLLIMM-nano product family combines optimized silicon chips, integrated in three main
inverter blocks:
●
●
●
power stage
–
six very fast IGBTs
–
six freewheeling diodes
driving network
–
three high voltage gate drivers
–
three gate resistors
–
three bootstrap diodes
protection and optional features
–
op amp for advanced current sensing
–
comparator for fault protection against overcurrent and short-circuit
–
smart shutdown function
–
dead time, interlocking function and undervoltage lockout.
Thanks to its very good compactness, the fully isolated SLLIMM-nano package (NDIP) is
the ideal solution for applications requiring reduced assembly space, without sacrificing
thermal performance and reliability.
Compared to discrete-based inverters, including power devices, and driver and protection
circuits, the SLLIMM-nano family provides a high integrated level that means simplified
circuit design, reduced component count, lower weight, and high reliability.
The aim of this application note is to provide a detailed description of SLLIMM-nano
products, providing guidelines to motor drive designers for an efficient, reliable, and fast
design when using the new ST SLLIMM-nano family.
September 2012
Doc ID 022726 Rev 2
1/60
www.st.com
Contents
AN4043
Contents
1
2
3
4
2/60
Inverter design concept and SLLIMM-nano solution . . . . . . . . . . . . . . . 5
1.1
Product synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2
Product line-up and nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3
Internal circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.4
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Electrical characteristics and functions . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1
IGBTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2
Freewheeling diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3
High voltage gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.1
Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.2
High voltage level shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.3
Undervoltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.4
Dead time and interlocking function management . . . . . . . . . . . . . . . . . 19
2.3.5
Comparators for fault sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3.6
Short-circuit protection and smart shutdown function . . . . . . . . . . . . . . 22
2.3.7
Timing chart of short-circuit protection and smart shutdown function . . 23
2.3.8
Current sensing shunt resistor selection . . . . . . . . . . . . . . . . . . . . . . . . 24
2.3.9
RC filter network selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.3.10
Op amps for advanced current sensing . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.3.11
Bootstrap circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.3.12
Bootstrap capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.3.13
Initial bootstrap capacitor charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.1
Package structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.2
Package outline and dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.3
Input and output pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Power losses and dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.1
Conduction power losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.2
Switching power losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.3
Thermal impedance overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Doc ID 022726 Rev 2
AN4043
Contents
4.4
5
Power loss calculation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Design and mounting guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.1
Layout suggestions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.1.1
5.2
6
General suggestions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Mounting instructions and cooling techniques . . . . . . . . . . . . . . . . . . . . . 53
General handling precaution and storage notices . . . . . . . . . . . . . . . . 56
6.1
Packaging specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
7
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
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List of tables
AN4043
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
4/60
SLLIMM-nano line-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Inverter part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Control part of the STGIPN3H60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Supply voltage and operation behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Total system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Integrated pull-up/down resistor values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Interlocking function truth table of the STGIPN3H60A . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Interlocking function truth table of the STGIPN3H60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Outline drawing of NDIP-26L package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Input and output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Cauer and Foster RC thermal network elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
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AN4043
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Inverter motor drive block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Discrete-based inverter vs. SLLIMM-nano solution comparison. . . . . . . . . . . . . . . . . . . . . . 7
SLLIMM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SLLIMM-nano nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Internal circuit of the STGIPN3H60A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Internal circuit of the STGIPN3H60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Stray inductance components of output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
High voltage gate drive die image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
High voltage gate driver block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Logic input configuration for the STGIPN3H60A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Logic input configuration for the STGIPN3H60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Timing chart of undervoltage lockout function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Timing chart of dead time function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Smart shutdown equivalent circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Timing chart of smart shutdown function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Examples of SC protection circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Example of SC event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3-phase system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
General advanced current sense scheme and waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 29
Bootstrap circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Bootstrap capacitor vs. switching frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Initial bootstrap charging time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Images and internal view of NDIP-26L package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Outline drawing of NDIP-26L package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Typical IGBT power losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
IGBT and diode approximation of the output characteristics . . . . . . . . . . . . . . . . . . . . . . . 43
Typical switching waveforms of the STGIPN3H60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Rth(j-a) equivalent thermal circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Thermal impedance Zth(j-a) curve for a single IGBT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Cauer RC equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Foster RC equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Maximum IC(RMS) current vs. fsw simulated curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
General suggestions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Example 1 on a possible wrong layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Example 2 on a possible wrong layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Cooling technique: copper plate on the PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Cooling technique: heatsink bonded on the package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Cooling technique: heatsink bonded on the PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Packaging specifications of NDIP-26L package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
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Inverter design concept and SLLIMM-nano solution
1
AN4043
Inverter design concept and SLLIMM-nano solution
Motor drive applications, ranging from a few tens of watts to mega watts, are mainly based
on the inverter concept thanks to the fact that this solution can meet efficiency, reliability,
size, and cost constraints required in a number of markets.
As shown in Figure 1, an inverter for motor drive applications is basically composed of a
power stage, mainly based on IGBTs and freewheeling diodes; a driving stage, based on
high voltage gate drivers; a control unit, based on microcontrollers or DSPs; some optional
sensors for protection and feedback signals for controls.
The approach of this solution with discrete devices produces high manufacturing costs
associated with high reliability risks, bigger size and higher weight, a considerable number
of components and the significant stray inductances and dispersions in the board layout.
Figure 1.
Inverter motor drive block diagram
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In recent years, the use of intelligent power modules has rapidly increased thanks to the
benefits of greater integration levels. The new ST SLLIMM-nano family is able to replace
more than 20 discrete devices in a single package. Figure 2 shows a comparison between a
discrete-based inverter and the SLLIMM-nano solution, the advantages of SLLIMM-nano
can be easily understood and can be summarized in a significantly improved design time,
reduced manufacturing efforts, higher flexibility in a wide range of applications, and
increased reliability and quality level.
In addition, the optimized silicon chips in both control and power stages and the optimized
board layout provide maximized efficiency, reduced EMI and noise generation, higher levels
of protection, and lower propagation delay time.
6/60
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AN4043
Figure 2.
Inverter design concept and SLLIMM-nano solution
Discrete-based inverter vs. SLLIMM-nano solution comparison
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1.1
Product synopsis
The SLLIMM-nano family has been designed to satisfy the requirements of a wide range of
final applications up to 100 W (in free air), such as:
●
dish washers
●
refrigerator compressors
●
air conditioning fans
●
draining and recirculation pumps
●
low power industrial applications
●
small fans, pumps and tools.
The main features and integrated functions can be summarized as follows:
●
600 V, 3 A ratings
●
3-phase IGBT inverter bridge including:
●
–
six low-loss IGBTs
–
six low forward voltage drop and soft recovery freewheeling diodes
three control ICs for gate driving and protection including:
–
smart shutdown function
–
comparator for fault protection against overcurrent and short-circuit
–
op amp for advanced current sensing
–
three integrated bootstrap diodes
–
interlocking function
–
undervoltage lockout
●
open emitter configuration for individual phase current sensing
●
very compact and fully isolated package
●
integrated gate resistors for IGBT switching speed optimum setting
●
gate driver proper biasing.
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Inverter design concept and SLLIMM-nano solution
AN4043
Figure 3 shows the block diagram of the SLLIMM-nano included in the inverter solution.
Figure 3.
SLLIMM block diagram
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The power devices (IGBTs and freewheeling diodes), incorporated in the half bridge block,
are tailored for a motor drive application delivering the greatest overall efficiency, thanks to
the optimized trade-off between conduction and switching power losses and very low EMI
generation, as a result of reduced dV/dt and di/dt.
The IC gate drivers have been selected in order to meet two levels of functionality, giving
users more freedom to choose: a basic version which includes the essential features for a
cost-effective solution and a fully featured version which provides advanced options for a
sophisticated control method.
The fully isolated NDIP package offers a high compactness level, very useful in those
applications with reduced space, ensuring at the same time, high thermal performance and
reliability levels.
8/60
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Inverter design concept and SLLIMM-nano solution
1.2
Product line-up and nomenclature
Table 1.
SLLIMM-nano line-up
Basic version
Fully featured version
STGIPN3H60A
STGIPN3H60
600
600
Current @ TC = 25 °C (A)
3
3
RthJA max. (°C/W)
50
50
NDIP-26L
NDIP-26L
Package size (mm) X, Y, Z
29.5x12.5x3.1
29.5x12.5x3.1
Integrated bootstrap diode
Yes
Yes
SD function
No
Yes
Comparator for fault protection
No
Yes (1 pin)
Smart shutdown function
No
Yes
Op amps for advanced current sensing
No
Yes
Interlocking function
Yes
Yes
Undervoltage lockout
Yes
Yes
Yes (3 pins)
Yes (3 pins)
Yes
Yes
High-side IGBT input signal
Active high
Active high
Low-side IGBT input signal
Active high
Active low
Features
Voltage (V)
Package type
Open emitter configuration
3.3 / 5 V input interface compatibility
Figure 4.
SLLIMM-nano nomenclature
67
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Inverter design concept and SLLIMM-nano solution
1.3
Internal circuit
Figure 5.
Internal circuit of the STGIPN3H60A
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Inverter design concept and SLLIMM-nano solution
Figure 6.
Internal circuit of the STGIPN3H60
1.4
Absolute maximum ratings
The absolute maximum ratings represent the extreme capability of the device and they can
be normally used as a worst limit design condition. It is important to note that the absolute
maximum value is given according to a set of testing conditions such us temperature,
frequency, voltage, and so on. Device performance can change according to the applied
condition.
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The SLLIMM-nano specifications are described below using the STGIPN3H60 datasheet as
an example. Please refer to the respective product datasheets for a detailed description of
all possible types.
Table 2.
Inverter part
Symbol
Parameter
(1)
= 0)
Value
Unit
600
V
VCES
Collector emitter voltage (VIN
±IC(2)
Each IGBT continuous collector current at TC = 25 °C
3
A
±IC(3)
Each IGBT pulsed collector current
18
A
PTOT
Each IGBT total dissipation at TC = 25 °C
8
W
1. Applied between HINU, HINV, HINW; LINU, LINV, LINW and GND.
2. Calculated according to the iterative Equation 1.
3. Pulse width limited by max. junction temperature.
Equation 1
IC (TC ) =
●
Tjmax − TC
Rth (j−c ) ⋅ VCE(sat)(max)(@Tj max,IC( TC ))
VCES: collector emitter voltage
The power stage of the SLLIMM-nano is based on IGBTs (and freewheeling diodes) having
600 V VCES rating. Generally, considering the intelligent power module internal stray
inductances during the commutations, which can generate some surge voltages, the
maximum surge voltage between P-N (VPN(surge)) allowed is lower than VCES, as shown in
Figure 7. At the same time, considering also the surge voltage generated by the stray
inductance between the device and the DC-link capacitor, the maximum supply voltage (in
steady-state) applied between P-N (VPN) must be even lower than VPN(surge). Thanks to the
small package size and the lower working current, this phenomenon is less marked in the
SLLIMM-nano than in a big intelligent power module.
12/60
Doc ID 022726 Rev 2
AN4043
Figure 7.
Inverter design concept and SLLIMM-nano solution
Stray inductance components of output stage
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±IC: each IGBT continuous collector current
The allowable DC current continuously flowing at the collector electrode (TC = 25 °C). The IC
parameter is calculated according to Equation 1.
Table 3.
Control part of the STGIPN3H60
Symbol
Parameter
Value
Unit
VOUT
Output voltage applied between OUTU, OUTV, OUTW, and
GND (VCC =15 V)
Vboot -21 to Vboot +0.3
V
VCC
Low voltage power supply
-0.3 to 21
V
VCIN
Comparator input voltage
-0.3 to VCC +0.3
V
VOP+
Op amp non-inverting input
-0.3 to VCC +0.3
V
VOP
Op amp inverting input
-0.3 to VCC +0.3
V
Vboot
Bootstrap voltage
-0.3 to 620
V
VIN
Logic input voltage applied between HIN, LIN and GND
-0.3 to 15
V
VSD/OD
Open drain voltage
-0.3 to 15
V
dVOUT/dt
Allowed output slew rate
50
V/ns
●
VCC: low voltage power supply
Doc ID 022726 Rev 2
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Inverter design concept and SLLIMM-nano solution
AN4043
VCC represents the supply voltage of the control part. A local filtering is recommended to
enhance the SLLIMM-nano noise immunity. Generally, the use of one electrolytic capacitor
(with greater value but not negligible ESR) and one smaller ceramic capacitor (hundreds of
nF), faster than the electrolytic one to provide current, is suggested.
Please refer to Table 4 in order to properly drive the SLLIMM-nano.
Table 4.
Supply voltage and operation behavior
VCC voltage (typ. value)
Operating behavior
STGIPN3H60A
STGIPN3H60
< 10 V
< 12 V
As the voltage is lower than the UVLO threshold the control circuit is not fully
turned on. A perfect functionality cannot be guaranteed.
12 V – 17 V
13.5 V – 18 V
Typical operating conditions
> 18 V
> 21 V
Control circuit is destroyed
Table 5.
Total system
Symbol
Parameter
Value
Unit
TJ
Operating junction temperature
-40 to 150
°C
TC
Module case operation temperature
-40 to 125
°C
14/60
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AN4043
2
Electrical characteristics and functions
Electrical characteristics and functions
In this section the main electrical characteristics of the power stage are discussed, together
with a detailed description of all the SLLIMM-nano functions.
2.1
IGBTs
The SLLIMM-nano achieves power savings in the inverter stage thanks to the use of IGBTs
manufactured with the proprietary advanced PowerMESH™ process.
These power devices, optimized for the typical motor control switching frequency, offer an
excellent trade-off between voltage drop (VCE(sat)) and switching speed (tfall), and therefore
minimize the two major sources of energy loss, conduction and switching, reducing the
environmental impact of daily-use equipment. A full analysis on the power losses of the
complete system in reported in Section 4: Power losses and dissipation.
2.2
Freewheeling diodes
Turbo 2 ultrafast high voltage diodes have been adequately selected for the SLLIMM-nano
family and carefully tuned to achieve the best trr/VF trade-off and softness as freewheeling
diodes in order to further improve the total performance of the inverter and significantly
reduce the electromagnetic interference (EMI) in the motor control applications which are
quite sensitive to this phenomena.
2.3
High voltage gate drivers
The SLLIMM-nano is equipped with a versatile high voltage gate driver IC (HVIC), designed
using BCD offline (Bipolar, CMOS, and DMOS) technology (see Figure 8) and particularly
suited to field oriented control (FOC) motor driving applications, able to provide all the
functions and current capability necessary for high-side and low-side IGBT driving. This
driver can be used in all applications where high voltage shifted control is necessary and it
includes a patented internal circuitry which replaces the external bootstrap diode.
Doc ID 022726 Rev 2
15/60
Electrical characteristics and functions
Figure 8.
AN4043
High voltage gate drive die image
Each high voltage gate driver chip controls two IGBTs in half bridge topology, offering basic
functions such as dead time, interlocking, integrated bootstrap diode, and also advanced
features such as smart shutdown (patented), fault comparator, and a dedicated high
performance op amp for advanced current sensing. A schematic summary of the features by
device are listed in Table 1.
In this application note the main characteristics of a high voltage gate drive related to the
SLLIMM-nano are discussed. For a greater understanding, please refer to the AN2738
application note.
16/60
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AN4043
Electrical characteristics and functions
Figure 9.
High voltage gate driver block diagram
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2.3.1
Logic inputs
The high voltage gate driver IC has two logic inputs, HIN and LIN, to separately control the
high-side and low-side outputs, HVG and LVG. Please refer to Table 1 for the input signal
logics by device.
In order to prevent any cross conduction between high-side and low-side IGBT, a safety time
(dead time) is introduced (see Section 2.3.4: Dead time and interlocking function
management for further details).
All the logic inputs are provided with hysteresis (~1 V) for low noise sensitivity and are
TTL/CMOS 3.3 V compatible. Thanks to this low voltage interface logic compatibility, the
SLLIMM-nano can be used with any kind of high performance controller, such as
microcontrollers, DSPs or FPGAs.
As shown in the block diagrams of Figure 10 and Figure 11, the logic inputs have internal
pull-down (or pull-up) resistors in order to set a proper logic level in the case of interruption
in the logic lines. If logic inputs are left floating, the gate driver outputs LVG and HVG are set
to low level. This simplifies the interface circuit by eliminating the six external resistors,
therefore, saving cost, board space and number of components.
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Electrical characteristics and functions
AN4043
Figure 10. Logic input configuration for the STGIPN3H60A
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Figure 11. Logic input configuration for the STGIPN3H60
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The typical values of the integrated pull-up/down resistors are shown in Table 6:
18/60
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Table 6.
Electrical characteristics and functions
Integrated pull-up/down resistor values
Input pin
PN
Input pin logic
High-side gate driving
HINU, HINV, HINW
STGIPN3H60A
Active high
500 kΩ
Low-side gate driving
LINU, LINV, LINW
STGIPN3H60A
Active high
500 kΩ
High-side gate driving
HINU, HINV, HINW
STGIPN3H60
Active high
85 kΩ
Low-side gate driving
LINU, LINV, LINW
STGIPN3H60
Active low
SD / OD shutdown
STGIPN3H60
Active low
2.3.2
Internal pull-up
Internal pull-down
720 kΩ
125 kΩ
High voltage level shift
The built-in high voltage level shift allows direct connection between the low voltage control
inputs and the high voltage power half bridge in any power application up to 600 V. It is
obtained thanks to the BCD offline technology which integrates, in the same die bipolar
devices, low and medium voltage CMOS for analog and logic circuitry and high voltage
DMOS transistors with a breakdown voltage in excess of 600 V. This key feature eliminates
the need for external optocouplers, resulting in significant savings regarding component
count and power losses. Other advantages are high-frequency operation and short input-tooutput delays.
2.3.3
Undervoltage lockout
The SLLIMM-nano supply voltage VCC is continuously monitored by an undervoltage
lockout (UVLO) circuitry which turns off the gate driver outputs when the supply voltage
goes below the VCC_thOFF threshold specified on the datasheet, and turns on the IC when
the supply voltage goes above the VCC_thON voltage. A hysteresis of about 1.5 V is provided
for noise rejection purposes. The high voltage floating supply Vboot is also provided with a
similar undervoltage lockout circuitry. When the driver is in UVLO condition, both gate driver
outputs are set to low level, setting the half bridge power stage output to high impedance.
The timing chart of undervoltage lockout, plotted in Figure 12, is based on the following
steps:
●
t1: when the VCC supply voltage raises the VCC_thON threshold, the gate driver starts to
work after the next input signal HIN/LIN is on. The circuit state becomes RESET
●
t2: input signal HIN/LIN is on and the IGBT is turned on
●
t3: when the VCC supply voltage goes below the VCC_thOFF threshold, the UVLO event
is detected. The IGBT is turned off in spite of input signal HIN/LIN. The state of the
circuit is now SET
●
t4: the gate driver re-starts once the VCC supply voltage again raises the VCC_thON
threshold
●
t5: input signal HIN/LIN is on and the IGBT is turned on again.
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Electrical characteristics and functions
AN4043
Figure 12. Timing chart of undervoltage lockout function
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2.3.4
Dead time and interlocking function management
In order to prevent any possible cross-conduction between high-side and low-side IGBTs,
the SLLIMM-nano provides both the dead time and the interlocking function. The
interlocking function is a logic operation which sets both the outputs to low level when the
inputs are simultaneously active. The dead time function is a safety time introduced by the
device between the falling edge transition of one driver output and the rising edge of the
other output. If the rising edge set externally by the user occurs before the end of this dead
time, it is ignored and results as delayed until the end of the dead time.
Table 7.
Interlocking function truth table of the STGIPN3H60A
Logic input (VI)
Outputs
Condition
LIN
HIN
LVG
HVG
Interlocking
half bridge tri-state
H
H
L
L
0 “logic state”
half bridge tri-state
L
L
L
L
1 “logic state”
low-side direct driving
H
L
H
L
1 “logic state”
high-side direct driving
L
H
L
H
The dead time is internally set at 320 ns as the typical value of the STGIPN3H60A.
20/60
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AN4043
Electrical characteristics and functions
Table 8.
Interlocking function truth table of the STGIPN3H60
Logic input (VI)
Outputs
Condition
Note:
SD
LIN
HIN
LVG
HVG
Shutdown enable
half bridge tri-state
L
X
X
L
L
Interlocking
half bridge tri-state
H
L
H
L
L
0 “logic state”
half bridge tri-state
H
H
L
L
L
1 “logic state”
low-side direct driving
H
L
L
H
L
1 “logic state”
high-side direct driving
H
H
H
L
H
X: not important.
The dead time is internally set at 180 ns as typical value. In Figure 13 the details of dead
time and interlocking function management of the STGIPN3H60 is described.
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Electrical characteristics and functions
AN4043
Figure 13. Timing chart of dead time function
G
HIN
INTE
RLO
CKIN
CONTROL SIGNAL EDGES
OVERLAPPED:
INTERLOCKING + DEAD TIME
INTE
RLO
CKIN
G
LIN
LVG
DTHL
DTLH
HVG
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
LIN
CONTROL SIGNALS EDGES
SYNCHRONOUS (*):
DEAD TIME
HIN
LVG
DTLH
DTHL
HVG
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
LIN
CONTROL SIGNALS EDGES
NOT OVERLAPPED,
BUT INSIDE THE DEAD TIME:
DEAD TIME
HIN
LVG
DTLH
DTHL
HVG
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
LIN
CONTROL SIGNALS EDGES
NOT OVERLAPPED,
OUTSIDE THE DEAD TIME:
DIRECT DRIVING
HIN
LVG
DTLH
DTHL
HVG
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
(*) HIN and LIN can be connected together and driven by just one control signal
2.3.5
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
AM10496v1
Comparators for fault sensing
The SLLIMM-nano STGIPN3H60 integrates one comparator intended for advanced fault
protection, such as overcurrent, overtemperature or any other type of fault measurable via a
voltage signal. The comparator has an internal reference voltage VREF, specified in the
datasheet, on its inverting input (see Figure 9), while the non-inverting input is available on
the CIN pin. The comparator input can be connected to an external shunt resistor, in order to
implement a simple overcurrent or short-circuit detection function, as discussed in detail in
Section 2.3.6: Short-circuit protection and smart shutdown function.
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2.3.6
Electrical characteristics and functions
Short-circuit protection and smart shutdown function
The fully featured version of the SLLIMM-nano (STGIPN3H60) is able to monitor the output
current and provide protection against overcurrent and short-circuit conditions in a very
short time (comparator triggering to high/low-side driver turn-off propagation delay tisd =
200 ns), thanks to the smart shutdown function. This feature is based on an innovative
patented circuitry which provides an intelligent fault management operation and greatly
reduces the protection intervention delay independently on the protection time duration
which can be set as desired by the device user.
As already mentioned in Section 2.3.5: Comparators for fault sensing and as shown in
Figure 9, the comparator input can be connected to an external shunt resistor, RSHUNT, in
order to implement a simple overcurrent detection function. An RC filter network (RSF and
CSF) is necessary to prevent erroneous operation of the protection. The output signal of the
comparator is fed to an integrated MOSFET with the open drain available on the SD / OD
pin, shared with the SD input. When the comparator triggers, the device is set in shutdown
state and all its outputs are set to low level, leaving the half bridge in tri-state. In common
overcurrent protection architectures, the comparator output is usually connected to the SD
input and an external RC network (RSD and CSD) is connected to this SD / OD line in order
to provide a mono-stable circuit which implements a protection time when a fault condition
occurs.
Contrary to common fault detection systems, the new smart shutdown structure allows an
immediate turn-off of the output gate driver in the case of fault, without waiting for the
external capacitor to be discharged. This strategy minimizes the propagation delay between
the fault detection event and the actual outputs switch-off. In fact, the time delay between the
fault and outputs disabling is not dependent on the RC value of the external SD circuitry but,
thanks to the new architecture, has a preferential path internally in the driver. Then the
device immediately turns off the driver outputs and latches the turn-on of the open drain
switch, until the SD signal has reached its lower threshold. After the SD signal goes below
the lower threshold, the open drain is switched off (see Figure 15).
The smart shutdown system provides the possibility to increase the value of the external RC
network across the SD pin (sized to fix the disable time generated after the fault event) as
much as desired by the user without compromising the intervention time delay of the
SLLIMM-nano protection.
A block diagram of the smart shutdown architecture is depicted in Figure 14.
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Electrical characteristics and functions
AN4043
Figure 14. Smart shutdown equivalent circuitry
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In normal operation the outputs follow the commands received from the respective input
signals.
When a fault detection event occurs, the fault signal (FSD) is set to HIGH by the fault
detection circuit output and the FF receives a SET input signal. Consequently, the FF
outputs set the SLLIMM-nano output signals to low level and, at the same time, turn on the
open drain MOSFET which works as active pull-down for the SD signal. Note that the gate
driver outputs stay at low level until the SD pin has experienced both a falling edge and a
rising edge, although the fault signal may be returned to low level immediately after the fault
sensing. In fact, even if the FF is reset by the falling edge of the SD input, the SD signal also
works as enable for the outputs, thanks to the two AND ports. Moreover, once the internal
open drain transistor has been activated, due to the latch, it cannot be turned off until the SD
pin voltage reaches the low logic level. Note that, since the FF is SET dominant, oscillations
of the SD pin are avoided if the fault signal remains steady at a high level.
2.3.7
Timing chart of short-circuit protection and smart shutdown function
With reference to Figure 15, the short-circuit protection is based on the following steps:
24/60
●
t1: when the output current is lower than the max. allowed level, the SLLIMM-nano is
working in normal operation
●
t2: when the output current reaches the max. allowed level (ISC), the overcurrent/shortcircuit event is detected and the protection is activated.
The voltage across the shunt resistor, and then on the CIN pin, exceeds the VREF value,
the comparator triggers, setting the device in shutdown state and both its outputs are
set to low level leading the half bridge in tri-state.
The smart shutdown switches off the IGBT gate (HVG, LVG) through a preferential path
(200 ns as typical internal delay time) and, at the same time, it switches on the M1
internal MOSFET. The SD signal starts the discharge phase and its value drops with a
time constant τA. The time constant τA value is given by:
Doc ID 022726 Rev 2
AN4043
Electrical characteristics and functions
Equation 2
(
)
τ A = RON _ OD // RSD ⋅ CSD
●
t3: the SD signal reaches the lower threshold Vsd_L_THR and the control unit switches
off the input HIN and LIN. The smart shutdown is disabled (M1 off) and SD can rise up
with a time constant τB, given by:
Equation 3
τB = RSD ⋅ CSD
●
t4: when the SD signal reaches the upper threshold Vsd_H_THR, the system is reenabled.
Figure 15. Timing chart of smart shutdown function
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Current sensing shunt resistor selection
As previously discussed, the shunt resistors RSHUNT externally connected between the N
pin and ground (see Figure 9) are used to realize the overcurrent detection.
When the output current exceeds the short-circuit reference level (ISC), the CIN signal
overtakes the VREF value and the short-circuit protection is active. For a reliable and stable
operation the current sensing resistor should be a high quality, low tolerance non-inductive
type. In fact, stray inductance in the circuit, which includes the layout, the RC filter, and also
the shunt resistor, must be minimized in order to avoid undesired short-circuit detection.
For these reasons, the shunt resistor and the filtering components must be placed as close
as possible to the SLLIMM-nano pins, for additional suggestions refer to Section 5.1: Layout
suggestions.
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Electrical characteristics and functions
AN4043
The value of the current sense resistor can be calculated by following different guidelines,
functions of the design specifications, or requirements. A common criterion is presented
here based on the following steps:
●
Defining of the overcurrent threshold value (IOC_th). For example, it can be fixed
considering the IGBT typical working current in the application and adding 20-30% as
overcurrent.
●
Calculation of the shunt resistor value according to the conditioning network. An
example of the conditioning network is shown in Figure 19. Further details can be
found in the user manuals listed (see References 5 and References 6).
●
Selection of the closest shunt resistor commercial value.
●
Calculation of the power rating of the shunt resistor, taking into account that this
parameter is strongly temperature dependent. Therefore, the power derating ratio of
the shunt resistor, ΔP(T)%, shown in the manufacturer's datasheet, must be considered
in the calculation as follows:
Equation 4
PSHUNT( T ) =
RSHUNT ⋅ I2RMS
ΔP(T )%
where IRMS is the IGBT RMS working current.
For a proper selection of the shunt resistor, a safety margin of at least 30% is recommended
on the calculated power rating.
2.3.9
RC filter network selection
Two options of shunt (1- or 3-shunt) resistor circuit can be adopted in order to implement
different control techniques and short-circuit protection, as shown in Figure 16.
Figure 16. Examples of SC protection circuit
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An RC filter network is required to prevent undesired short-circuit operation due to the noise
on the shunt resistor.
26/60
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AN4043
Electrical characteristics and functions
Both solutions allow to detect the total current in all three phases of the inverter. The filter is
based on the RSF and CSF network and its time constant is given by:
Equation 5
tSF = RSF ⋅ CSF
In addition to the RC time constant, the turn-off propagation delay of the gate driver, tisd
(specified in the datasheet) and the IGBT turn-off time (in the range of tens of ns), must be
considered in the total delay time (tTotal), which is the time necessary to completely switch
off the IGBT once the short-circuit event is detected. Therefore, the tTotal is calculated as
follows:
Equation 6
t Total = tSF + tisd + toff
and the tSF is recommended to be set in the range of 1~2 µs.
In the case of a 3-shunt resistor circuit, a specific control technique can be implemented by
using the three shunt resistors (RSHUNT_U, RSHUNT_V and RSHUNT_W) able to monitor each
phase current.
An example of a short-circuit event is shown in Figure 17, where it is possible to note the
very fast protection, thanks to the smart shutdown function, against fault events. The main
steps are:
●
t1: collector current IC starts to rise. SC event is not detected yet due to the RC
network on the CIN pin.
●
t2: voltage on VCIN reaches the VREF. SC event is detected and the smart shutdown
starts to turn off the SLLIMM-nano.
●
t3: the SD in activated.
●
t4: the SLLIMM-nano is definitively turned off in 580 ns (including the td(off) time of
IGBT) from SC detection.
Finally, the total disable time is t4-t2 and the total SC action time is t4-t1.
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Electrical characteristics and functions
AN4043
Figure 17. Example of SC event
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2.3.10
Op amps for advanced current sensing
The fully featured version of the SLLIMM-nano (STGIPN3H60) integrates also one
operational amplifier optimized for field oriented control (FOC) applications. In a typical FOC
application the currents in the three half bridges are sensed using a shunt resistor. The
analog current information is transformed into a discontinuous sense voltage signal, having
the same frequency as the PWM signal driving the bridge. The sense voltage is a bipolar
analog signal, whose sign depends on the direction of the current (see Figure 18):
28/60
Doc ID 022726 Rev 2
AN4043
Electrical characteristics and functions
Figure 18. 3-phase system
3-phase driver
Sinusoidal Vector Control
Sensing:
Discontinuous Voltage at fPWM frequency
96
96
96
Power
stage
IPHASE
SKDVH
PRWRU
AM09338v1
The sense voltage signals must be provided to an A-D converter. They are usually shifted
and amplified by dedicated op amps in order to exploit the full range of the A-D converter.
The typical scheme and principle waveforms are shown in Figure 19:
Figure 19. General advanced current sense scheme and waveforms
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6HQVHYROWDJHVLJQDO
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6KLIWHGDQGFHQWHUHG
VLJQDO
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5
5
5287
23 2SDPS
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5
&
5
WR$'&
9ROWDJHJDLQ
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Doc ID 022726 Rev 2
&287
UHTXLUHGE\WKH$'&
IRUVDPSOLQJSXUSRVH
!-V
29/60
Electrical characteristics and functions
AN4043
ADCs used in vector control applications have a typical full scale range (FSR) of about
3.3 V. The sense signals must be shifted and centered on FSR/2 voltage (about 1.65 V) and
amplified with a gain which provides the matching between the maximum value of the
sensed signal and the FSR of the ADC. Some typical examples of sense network sizing can
be found in the user manuals listed (see References 5 and References 6).
2.3.11
Bootstrap circuit
In the 3-phase inverter the emitters of the low-side IGBTs are connected to the negative DC
bus (VDC-) as common reference ground, which allows all low-side gate drivers to share the
same power supply, while, the emitter of high-side IGBTs is alternately connected to the
positive (VDC+) and negative (VDC-) DC bus during the running conditions.
A bootstrap method is a simple and cheap solution to supply the high voltage section. This
function is normally accomplished by a high voltage fast recovery diode. The SLLIMM-nano
family includes a patented integrated structure that replaces the external diode. It is realized
with a high voltage DMOS driven synchronously with the low-side driver (LVG) and a diode
in series. An internal charge pump provides the DMOS driving voltage.
The operation of the bootstrap circuit is shown in Figure 20. The floating supply capacitor
CBOOT is charged, from the VCC supply, when the VOUT voltage is lower than the VCC
voltage (e.g. low-side IGBT is on), through the bootstrap diode and the DMOS path with
reference to the “bootstrap charge current path”. During the high-side IGBT ON phase, the
bootstrap circuit provides the right gate voltage to properly drive the IGBT (see “bootstrap
discharge current path”). This circuit is iterated for all the three half bridges.
Figure 20. Bootstrap circuit
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FKDUJH
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/9*
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The value of the CBOOT capacitor should be calculated according to the application
condition and must take the following into account:
●
30/60
voltage across CBOOT must be maintained at a value higher than the undervoltage
lockout level for the IC driver. This enables the high-side IGBT to work with a correct
gate voltage (lower dissipation and better overall performances). Please consider that if
Doc ID 022726 Rev 2
AN4043
Electrical characteristics and functions
a voltage below the UVLO threshold is applied on the bootstrap channel, the IC
disables itself (no output) without any fault signal.
2.3.12
●
the voltage across CBOOT is affected by different components such as drop across the
integrated bootstrap structure, drop across the low-side IGBT, and others.
●
when the high-side IGBT is on, the CBOOT capacitor discharges mainly to provide the
right IGBT gate charge but other phenomena must be considered such as leakage
currents, quiescent current, etc.
Bootstrap capacitor selection
A simple method to properly size the bootstrap capacitor considers only the amount of
charge that is needed when the high voltage side of the driver is floating and the IGBT gate
is driven once. This approach does not take into account either the duty cycle of the PWM,
or the fundamental frequency of the current. Observations on PWM duty cycle, the kind of
modulation (6-step, 12-step and sine-wave) must be considered with their own peculiarity to
achieve the best bootstrap circuit sizing.
During the bootstrap capacitor charging phase, the low-side IGBT is on and the voltage
across CBOOT (VCBOOT) can be calculated as follows:
Equation 7
VCBOOT = VCC − VF − VRDS(on) − VCE(sat) max
where:
VCC: supply voltage of gate driver.
VF: bootstrap diode forward voltage drop.
VCE(sat)max: maximum emitter collector voltage drop of low-side IGBT.
VRDS(on): DMOS voltage drop.
The dimension of the bootstrap capacitance CBOOT value is based on the minimum voltage
drop (ΔVCBOOT) to guarantee when the high-side IGBT is on, and must be:
Equation 8
ΔVCBOOT = VCC − VF − VRDS(on) − VGE(min) − VCE(sat) max
under the condition:
Equation 9
VCBOOT(min) > VBS _ thON
where:
VGE(min): minimum gate emitter voltage of high-side IGBT.
VBS_thON: bootstrap turn-on undervoltage threshold (maximum value, see datasheet).
Considering the factors contributing to VCBOOT decreasing, the total charge supplied by the
bootstrap capacitor (during high-side ON phase) is:
Doc ID 022726 Rev 2
31/60
Electrical characteristics and functions
AN4043
Equation 10
(
)
Q TOT = Q GA TE + ILKGE + IQBO + ILK + ILKDiode + ILKCap ⋅ tHon + Q LS
where:
QGATE: total IGBT gate charge.
ILKGE: IGBT gate emitter leakage current.
IQBO: bootstrap circuit quiescent current.
ILK: bootstrap circuit leakage current.
ILKDiode: bootstrap diode leakage current.
ILKCap: bootstrap capacitor leakage current (relevant when using an electrolytic capacitor
but can be ignored if other types of capacitors are used).
tHon: high-side ON time.
QLS: charge required by the internal level shifters.
Finally, the minimum size of the bootstrap capacitor is:
Equation 11
CBOOT =
QTOT
ΔVCBOOT
For an easier selection of bootstrap capacitor, Figure 21 shows the behavior of CBOOT
(calculated) versus switching frequency (fsw), with different values of ΔVCBOOT,
corresponding toEquation 11 Equation 11 for a continuous sinusoidal modulation and a duty
cycle δ = 50%.
Figure 21. Bootstrap capacitor vs. switching frequency
AM11814v1
5
STGIPN3H60A
STGIPN3H60
δ = 50%
C BOOT Calculated (µF)
4
3
ΔVCBOOT =0.1V
2
ΔVCBOOT =0.3V
ΔVCBOOT =0.5V
1
0
0
5
10
f sw (kHz)
32/60
Doc ID 022726 Rev 2
15
20
AN4043
Electrical characteristics and functions
Considering the limit cases during the PWM control and further leakages and dispersions in
the board layout, the capacitance value to use in the bootstrap circuit must be selected two
or three times higher than the CBOOT calculated in the graph of Figure 21. The bootstrap
capacitor should be with a low ESR value for a good local decoupling, therefore, in case an
electrolytic capacitor is used, one parallel ceramic capacitor placed directly on the SLLIMMnano pins is strictly recommended.
2.3.13
Initial bootstrap capacitor charging
During the startup phase, the bootstrap capacitor must be charged for a suitable time to
complete the initial charging time (tCHARGE), which is, at least, the time VCBOOT needs to
exceed the turn-on undervoltage threshold VBS_thON, as already stated in Equation
9Equation 9. For a normal operation, the voltage across the bootstrap capacitor must never
drop down to the turn-off undervoltage threshold VBS_thOFF throughout the working
conditions. For the period of startup, only the low-side IGBT is switched on and, just after
this phase, the PWM is run, as shown in the following steps of Figure 22:
●
t1: the bootstrap capacitor starts to charge through the low-side IGBT (LVG)
●
t2: the voltage across the bootstrap capacitor (VCBOOT) reaches its turn-on
undervoltage threshold VBS_thON
●
t3: the bootstrap capacitor is fully charged; this enables the high-side IGBT and the
CBOOT capacitor starts to discharge in order to provide the right IGBT gate charge. The
bootstrap capacitor recharges during the on-state of the low-side IGBT (LVG).
Figure 22. Initial bootstrap charging time
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The initial charging time is given byEquation 12 Equation 12 and must be, for safety
reasons, at least three times longer than the calculated value.
Doc ID 022726 Rev 2
33/60
Electrical characteristics and functions
AN4043
Equation 12
tCHARGE ≥
CBOOT ⋅ RDS(on)
δ
⎛ VCC
⎞
⎟
* ln⎜
⎜ ΔV
⎟
⎝ CBOOT ⎠
where δ is the duty cycle of the PWM signal and RDS(on) is 120 Ω typical value, as shown in
the datasheet.
A practical example can be done by considering a motor drive application where the PWM
switching frequency is 16 kHz, with a duty cycle of 50%, and ΔVCBOOT = 0.1 V (that means,
a gate driver supply voltage VCC = 17.5 V). From the graph in Figure 21 the bootstrap
capacitance is 1.0 µF, therefore the CBOOT can be selected by using a value between 2.0
and 3.0 µF. According to the commercial value the bootstrap capacitor can be 2.2 µF. From
Equation 12Equation 12, the initial charging time is:
Equation 13
t CHARGE ≥
−6
2.2 ⋅ 10 ⋅ 120 ⎛ 17.5 ⎞
⋅ ln⎜⎜
⎟⎟ = 2.7ms
0. 5
⎝ 0.1 ⎠
For safety reasons, the initial charging time must be at least 8.1 ms.
34/60
Doc ID 022726 Rev 2
AN4043
3
Package
Package
The NDIP is a dual-in-line transfer mold package available in 26-lead version (NDIP-26L)
able to meet demanding cost and size requirements of consumer appliance inverters. It
consists of a copper lead frame with power stage and control stage soldered on it and
housed using the transfer molding process. The excellent thermal properties of the copper
allows good heat spread and heat transfer, furthermore, the thickness and the layout of the
lead frames has been optimized in order to further reduce the thermal resistance.
The package pinout has been designed in order to maximize the distance between the high
voltage and low voltage pins, by placing the relevant pins on the opposite side of the
package. This is mainly useful to keep a safe distance between high voltage and low voltage
pins and for an easy PCB layout.
Finally, thanks to the transfer molding technology and design optimization, the SLLIMMnano offers a high power density level in a very compact package while providing good
thermal propriety, electrical isolation and overall reliable performance.
3.1
Package structure
Figure 23 contains the images and an internal structure illustration of the NDIP-26L
package.
Figure 23. Images and internal view of NDIP-26L package
nano
MM SLLI
Top view
Bottom view
SLLIMM-nano
NDIP-26L
HVIC
IGBT
FWD
z
x
y
Main dimensions
Internal view
x = 29.5 mm
y1 = 12.5 mm (body only)
y2 = 22 mm (including leads)
z1 = 3.1 mm (body only)
z2 = 7 mm (including leads)
Doc ID 022726 Rev 2
35/60
Package
3.2
AN4043
Package outline and dimensions
Figure 24. Outline drawing of NDIP-26L package
D3
b,b2
A2
b
D1
A3
A1
A4
c
c1
A
0.075
b1,b3
e
E
eB2
eB1
0.075
L
D
D2
b2
8278949_A
36/60
e1
AM11815v1
Doc ID 022726 Rev 2
AN4043
Package
Table 9.
Outline drawing of NDIP-26L package
(mm)
Dimension
Min.
Typ.
A
4.4
A1
0.8
1
1.2
A2
3
3.1
3.2
A3
1.7
1.8
1.9
A4
5.7
5.9
6.1
b
0.53
b1
0.52
b2
0.83
b3
0.82
c
0.46
c1
0.45
0.5
0.55
D
29.05
29.15
29.25
D1
0.5
D2
0.35
0.72
0.6
0.68
1.02
0.9
0.98
0.59
D3
3.3
Max.
29.55
E
12.35
12.45
12.55
e
1.7
1.8
1.9
e1
2.4
2.5
2.6
eB1
16.1
16.4
16.7
eB2
21.18
21.48
21.78
L
1.24
1.39
1.54
Input and output pins description
This paragraph defines the input and output pins of the SLLIMM-nano. For a more accurate
description and layout suggestions, please consult the relevant sections.
Doc ID 022726 Rev 2
37/60
Package
AN4043
Figure 25. Pinout (top view)
Table 10.
Input and output pins
Name
Description
Pin #
STGIPN3H60A
1
2
STGIPN3H60
STGIPN3H60A
GND
NC
STGIPN3H60
Ground
SD / OD
Not connected
Shutdown logic input (active low) /
open drain (comparator output)
3
VCC W
Low voltage power supply W phase
4
HINW
High-side logic input for W phase
5
LINW
LINW
Low-side logic input for W
phase (active high)
Low-side logic input for W phase
(active low)
6
NC
OP+
Not connected
Op amp non inverting input
7
NC
OPOUT
Not connected
Op amp output
8
NC
OP-
Not connected
Op amp inverting input
9
VCC V
Low voltage power supply V phase
10
HINV
High-side logic input for V phase
11
LINV
LINV
Low-side logic input for V
phase (active high)
Low-side logic input for V phase
(active low)
12
NC
CIN
Not connected
Comparator input
13
VCC U
Low voltage power supply U phase
14
HINU
High-side logic input for U phase
15
NC
SD / OD
Not connected
Shutdown logic input (active low) /
open drain (comparator output)
16
LINU
LINU
Low-side logic input for U
phase (active high)
Low-side logic input for U phase
(active low)
17
38/60
VbootU
Bootstrap voltage for U phase
Doc ID 022726 Rev 2
AN4043
Table 10.
Package
Input and output pins (continued)
Name
Description
Pin #
STGIPN3H60A
STGIPN3H60
STGIPN3H60A
STGIPN3H60
18
P
Positive DC input
19
U
U phase output
20
NU
Negative DC input for U phase
21
VbootV
Bootstrap voltage for V phase
22
V
V phase output
23
NV
Negative DC input for V phase
24
VbootW
Bootstrap voltage for W phase
25
W
W phase output
26
NW
Negative DC input for W phase
High-side bias voltage pins /high-side bias voltage reference
Pins: VbootU-U, VbootV-V, VbootW-W
●
The bootstrap section is designed to realize a simple and efficient floating power
supply, in order to provide the gate voltage signal to the high-side IGBTs
●
The SLLIMM-nano family integrates the bootstrap diodes. This helps users to save
costs, board space, and number of components
●
The advantage of the ability to bootstrap the circuit scheme is that no external power
supplies are required for the high-side IGBTs
●
Each bootstrap capacitor is charged from the VCC supply during the on-state of the
corresponding low-side IGBT
●
To prevent malfunction caused by noise and ripple in supply voltage, a good quality
(low ESR, low ESL) filter capacitor should be mounted close to these pins
●
The value of bootstrap capacitors is strictly related to the application conditions. Please
consult Section 2.3.11: Bootstrap circuit for more information.
Gate driver bias voltage
Pins: VCC U, VCC V, VCC W
●
Control supply pins for the built-in ICs
●
To prevent malfunction caused by noise and ripple in the supply voltage, a good quality
(low ESR, low ESL) filter capacitor should be mounted close to these pins.
Gate drive supply ground
Pin: GND
●
Ground reference pin for the built-in ICs
●
To avoid noise influence, the main power circuit current should not be allowed to flow
through this pin (see Section 5.1: Layout suggestions).
Doc ID 022726 Rev 2
39/60
Package
AN4043
Signal input
Pins: HINU, HINV, HINW; LINU, LINV, LINW; LINU, LINV, LINW
●
These pins control the operation of the built-in IGBTs.
●
The signal logic of HINU, HINV, HINW, LINU, LINV, and LINW pins is active high. The
IGBT associated with each of these pins is turned on when a sufficient logic (higher
than a specific threshold) voltage is applied to these pins.
●
The signal logic of LINU, LINV, LINW pins is active low. The IGBT associated with each
of these pins is turned on when a logic voltage (lower than a specific threshold voltage)
is applied to these pins.
●
The wiring of each input should be as short as possible to protect the SLLIMM-nano
against noise influence. RC coupling circuits should be adopted for the prevention of
input signal oscillation. Suggested values are R=100Ω and C=1nF.
Internal comparator non-inverting (only for the STGIPN3H60)
Pin: CIN
●
The current sensing shunt resistor, connected on each phase leg, may be used by the
internal comparator (pin CIN) to detect short-circuit current
●
The shunt resistor should be selected to meet the detection levels matched for the
specific application
●
An RC filter (typically ~1 µs) should be connected to the CIN pin to eliminate noise
●
The connection length between the shunt resistor and CIN pin should be minimized
●
If a voltage signal, higher than the specified VREF (see datasheet), is applied to this pin,
the SLLIMM-nano automatically shuts down and the SD / OD pin is pulled down (to
inform the microcontroller).
Shutdown / open drain (only for the STGIPN3H60)
Pins: SD / OD
●
There are two available pins of SD / OD which are exactly the same. They are placed
on the opposite ends of the package in order to offer higher flexibility to the PCB layout.
It is sufficient to use only one of the two pins for the proper functioning of the device.
●
The SD / OD pins work as enable/disable pins.
●
The signal logic of SD / OD pins are active low. The SLLIMM-nano shuts down if a
voltage lower than a specific threshold is applied to these pins, leading each half bridge
in tri-state.
●
The SD / OD status is connected also to the internal comparator status (Section 2.3.6:
Short-circuit protection and smart shutdown function). When the comparator triggers,
the SD / OD pin is pulled down acting as a FAULT pin.
The SD / OD, when pulled down by the comparator, are open drain configured. The SD
/ OD voltage should be pulled up to the 3.3 V or 5 V logic power supply through a pullup resistor.
●
Integrated operational amplifier (only for the STGIPN3H60)
Pins: OP+, OP-, OPOUT
40/60
●
The op amp is completely uncommitted
●
The op amp performance is optimized for advanced control technique (FOC)
●
Thanks to the integrated op amp, it is possible to realize a compact and efficient board
layout, minimizing the required BOM list.
Doc ID 022726 Rev 2
AN4043
Package
Positive DC-link
Pin: P
●
This is a DC-link positive power supply pin of the inverter and it is internally connected
to the collectors of the high-side IGBTs
●
To suppress the surge voltage caused by the DC-link wiring or PCB pattern inductance,
connect a smoothing filter capacitor close to the P pin. Generally a 0.1 or 0.22 µF high
frequency, high voltage non-inductive capacitor is recommended.
Negative DC-link
Pins: NU, NV, NW
●
These are the DC-link negative power supply pins (power ground) of the inverter
●
These pins are connected to the low-side IGBT emitters of each phase
●
The power ground of the application should be separated from the logic ground of the
system and they should be reconnected at one specific point (star connection).
Inverter power output
Pins: U, V, W
●
Inverter output pins for connecting to the inverter load (e.g. motor).
Doc ID 022726 Rev 2
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Power losses and dissipation
4
AN4043
Power losses and dissipation
The total power losses in an inverter are comprised of conduction losses, switching losses,
and off-state losses and they are essentially generated by the power devices of the inverter
stage, such as the IGBTs and the freewheeling diodes. The conduction losses (PCOND) are
the on-state losses during the conduction phase. The switching losses (PSW) are the
dynamic losses encountered during turn-on and turn-off. The off-state losses, due to the
blocking voltage and leakage current, can be neglected.
Finally, the total power losses are given by:
Equation 14
Ptot ≈ Pcond + Psw
Figure 26 shows a typical waveform of an inductive hard switching application such as a
motor drive, where the major sources of power losses are specified.
Figure 26. Typical IGBT power losses
VCE
IC
10% VCE
10% IC
VCE(sat)
10% IC
Esw(off)
Esw(on)
tc(on)
10% VCE
conduction
tc(off)
AM09357v1
4.1
Conduction power losses
The conduction losses are caused by IGBT and freewheeling diode forward voltage drop at
rated current. They can be calculated using a linear approximation of the forward
characteristics for both the IGBT and diode, having a series connection of DC voltage
source representing the threshold voltage, VTO for IGBT, (and VFO for diode) and a collector
emitter on-state resistance, RCE, (and anode cathode on-state resistance, RAK), as shown
in Figure 27.
42/60
Doc ID 022726 Rev 2
AN4043
Power losses and dissipation
Figure 27. IGBT and diode approximation of the output characteristics
AM09345v1
RAK = ΔVFM / ΔIFM
ΔIFM
RCE = ΔVCE / ΔIC
ΔIC
ΔVFM
ΔVCE
VTO
VFO
Both forward characteristics are temperature dependent, and so must be considered under
a specified temperature.
The linear approximations can be translated for IGBT in the following equation:
Equation 15
v ce(ic ) = VTO + RCE ⋅ ic
and, for freewheeling diode:
Equation 16
v fm (ifm ) = VFO + RAK ⋅ ifm
The conduction losses of IGBT and diode can be derived as the time integral of the product
of conduction current and voltage across the devices, as follows:
Equation 17
Pcond_IGBT =
1 T
∫
T 0
vce ⋅ ic (t)dt =
1 T⎛
2
⎜ VTO ⋅ ic (t) + R ce ⋅ ic (t) ⎞⎟dt
⎠
T 0⎝
∫
Equation 18
Pcond_Diode =
1 T
1 T⎛
v f ⋅ if (t)dt =
⎜ V ⋅ i (t) + R AK ⋅ i2f (t) ⎞⎟ dt
⎠
T 0
T 0 ⎝ FO f
∫
∫
where T is the fundamental period.
The different utilization mode of the SLLIMM-nano, modulation technique, and working
conditions make the power losses very difficult to estimate, it is therefore necessary to fix
some starting points.
Doc ID 022726 Rev 2
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Power losses and dissipation
AN4043
Assuming that:
1.
The application is a variable voltage variable frequency (VVVF) inverter based on
sinusoidal PWM technique.
2.
The switching frequency is high and therefore the output currents are sinusoidal.
3.
The load is ideal inductive.
Under these conditions, the output inverter current is given by:
Equation 19
i = Î cos(θ- φ )
where Î is the current peak, θ stands for ωt and φ is the phase angle between output voltage
and current.
The conduction power losses can be obtained as:
Equation 20
V ⋅ Î
Pcond_IGBT = TO
2π
∫
π
+φ
2
π
− +φ
2
R
⋅ Î 2
ξ cos(θ - φ)d θ + CE
2π
∫
π
+φ
2
ξ cos2 (θ - φ )d θ
π
− +φ
2
Equation 21
V Î
Pcond_Diode = FO
2π
∫
π
+φ
2
(1 − ξ) cos(θ - φ)dθ + RAK
Î2
2π
π
− +φ
2
∫
π
+φ
2
(1− ξ) cos2(θ - φ)dθ
π
− +φ
2
where ξ is the duty cycle for this PWM technique and is given by:
Equation 22
ξ=
1+ ma ⋅ cos θ
2
and ma is the PWM amplitude modulation index.
Finally, solving Equation 20Equation 20 and Equation 21Equation 21, we have:
Equation 23
⎛ 1 ma ⋅ cos φ ⎞ RCE ⋅ Î 2
⎟⎟ +
+
Pcond_IGBT = VTO ⋅ Î ⎜⎜
8
2π
⎠
⎝ 2π
⎛ 1 ma ⋅ cos φ ⎞
⎟⎟
⎜⎜ +
3π
⎠
⎝8
Equation 24
⎛ 1 ma ⋅ cos φ ⎞ RAK ⋅ Î 2 ⎛ 1 ma ⋅ cos φ ⎞
Pcond_Diode = VFO ⋅ Î ⎜⎜
−
⎟⎟ +
⎜ −
⎟⎟
8
2π ⎜⎝ 8
3π
⎝ 2π
⎠
⎠
44/60
Doc ID 022726 Rev 2
AN4043
Power losses and dissipation
and therefore, the conduction power losses of one device (IGBT and diode) are:
Equation 25
Pcond = Pcond_IGBT + Pcond_Diode
Of course, the total conduction losses per inverter are six times this value.
4.2
Switching power losses
The switching loss is the power consumption during the turn-on and turn-off transients. As
already shown in Figure 26, it is given by the pulse of power dissipated during the turn-on
(ton) and turn-off (toff). Experimentally, it can be calculated by the time integral of product of
the collector current and collector-emitter voltage for the switching period. However, the
dynamic performance is strictly related to many parameters such as voltage, current and
temperature, so it is necessary to use the same assumptions of conduction power losses
(Section 4.1: Conduction power losses) to simplify the calculations.
Under these conditions, the switching energy losses are given by:
Equation 26
Eon(θ) = Êon cos(θ- φ )
Equation 27
Eoff (θ) = Ê off cos(θ- φ)
where Êon and Êoff are the maximum values taken at Tjmax and Îc, θ stands for ωt and φ is
the phase angle between output voltage and current.
Finally, the switching power losses per device depend on the switching frequency (fsw) and
they are calculated as follows:
Equation 28
Psw =
1
2π
∫
π
+φ
2
(EIGBT + EDiode) ⋅ fswdθ =
π
- +φ
2
(EIGBT + EDiode) ⋅ fsw
π
where EIGBT and EDiode are the total switching energy for the IGBT and the freewheeling
diode, respectively. Also in this case, the total switching losses per inverter are six times this
value.
Figure 28 shows the real turn-on and turn-off waveforms of the STGIPN3H60 under the
following conditions:
●
VPN = 300 V, IC = 0.5 A, Tj = 100 °C with inductive load on full bridge topology, taken on
the low-side IGBT.
The green plots represent instantaneous power as a result of IC (in red) and VCE (in yellow)
waveforms multiplication, during the switching transitions. The areas under these plots are
the switching energies computed by graphic integration thanks to the digital oscilloscope.
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Power losses and dissipation
AN4043
Figure 28. Typical switching waveforms of the STGIPN3H60
Turn on
ton = 270ns
toff = 905ns
STGIPN3H60
Low side
Tj=100°C
VLIN
VLIN
VCE
VCE
IC
IC
Eoff=5.1μJ(*)
Eon=23.5μJ(*)
VLIN = 2V/Div
VCE = 100V/Div IC = 500mA/Div
(*) Eon and Eoff are the areas under the red plots
4.3
Turn off
STGIPN3H60
Low side
Tj=100°C
t = 100ns/Div
VLIN = 2V/Div
VCE = 100V/Div IC = 200mA/Div
E = ∫ (VCE · IC) dt
t = 200ns/Div
AM11816v1
Thermal impedance overview
During operation, power losses generate heat which elevates the temperature in the
semiconductor junctions contained in the SLLIMM-nano, limiting its performance and
lifetime. To ensure safe and reliable operation, the junction temperature of power devices
must be kept below the limits defined in the datasheet, therefore, the generated heat must
be conducted away from the power chips and into the environment using an adequate
cooling system.
The SLLIMM-nano was designed to drive electric motors up to 100 W without any heatsink.
Therefore, the thermal aspect of the system is one of the key factors in designing high
efficiency and high reliability equipment. In this environment the package and its thermal
resistance play a fundamental role.
Thermal resistance quantifies the capability of a given thermal path to transfer heat in
steady-state and it is generically given as the ratio between the temperature increase above
the reference and the relevant power flow:
Equation 29
Rth =
ΔT
ΔP
The thermal resistance specified in the datasheet is the junction-ambient Rth(j-a) which is
commonly used with natural and forced convection air cooled systems and it is defined as
the difference in temperature between junction and ambient reference divided by the power
dissipation per device:
Equation 30
Rth(j-a) =
46/60
Tj − Tamb
PD
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Power losses and dissipation
Figure 29 shows an equivalent circuit of the thermal resistance between junction and
ambient Rth(j-a).
Figure 29. Rth(j-a) equivalent thermal circuit
AM11817v1
As the power loss Ptot is cyclic, also the transient thermal impedance must be considered. It
is defined as the ratio between the time dependent temperature increase above the
reference, ΔT(t), and the relevant heat flow:
Equation 31
Zth(t) =
ΔT(t )
ΔP
Contrary to that already seen regarding the thermal resistance, the thermal impedance is
typically represented by an RC equivalent circuit. For pulsed power loss, the thermal
capacitance effect delays the rise in junction temperature and therefore the advantage of
this behavior is the short-term overload capability of the SLLIMM-nano.
For example, Figure 30 shows thermal impedance from a junction to ambient curve for a
single IGBT of the SLLIMM-nano.
Figure 30. Thermal impedance Zth(j-a) curve for a single IGBT
SLLIMM-nano Z th(j-a)
AM11818v1
60
Z th(j-a) (°C/W)
50
40
30
20
10
0
1.E-05
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
time (sec)
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Power losses and dissipation
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More generally, in the case of the device, power is time dependent too. The device
temperature can be calculated by using the convolution integral method applied to Equation
31Equation 31, as follows:
Equation 32
Δ T( t) =
t
∫Z
0
th (t − τ) ⋅ P( τ)dτ
An alternative method, very useful for the simulator tools, is the transient thermal impedance
model, which provides a simple method to estimate the junction temperature rise under a
transient condition.
By using the thermo-electrical analogy, the transient thermal impedance Zth(t) can be
transformed into an electrical equivalent RC network. The number of RC sections increases
the model details, therefore a twelfth order model, for Zth(j-a), based on the Cauer and Foster
networks, has been used in order to improve the accuracy of both models.
Figure 31 and Figure 32 show the general Cauer and Foster RC equivalent circuit used for
the thermal impedance model.
Figure 31. Cauer RC equivalent circuit
7M
3WRWW
R1
=WKW
R3
R2
C1
C2
Rn
C3
Cn
7DPE
AM11819v1
Figure 32. Foster RC equivalent circuit
7M
3WRWW
R1
R2
R3
Rn
=WKW
7DPE
C1
C2
C3
Cn
AM11820v1
Temperatures inside the electrical RC network represent voltages, power flows represent
currents, electrical resistances and capacitances represent thermal resistances and
capacitances respectively. The case temperature is represented with a DC voltage source
and it can be interpreted as the initial junction temperature.
Transient thermal impedance models are derived by curve fitting an equation to the
measured data. Values for the individual resistors and capacitors are the variables from that
equation and are defined in Table 11, for both Zth(j-a) Cauer and Foster thermal impedance
models.
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Power losses and dissipation
Table 11.
4.4
Cauer and Foster RC thermal network elements
Element
Zth(j-a) Cauer Network
Zth(j-a) Foster Network
R1 (°C/W)
8.96E-01
1.81E-01
R2 (°C/W)
9.37E-01
1.71E-01
R3 (°C/W)
5.92E-01
8.12E-02
R4 (°C/W)
1.37E-02
5.11E-02
R5 (°C/W)
2.11E-02
1.86E-01
R6 (°C/W)
2.84E+00
6.58E-01
R7 (°C/W)
1.26E-01
5.00E-04
R8 (°C/W)
4.48E-02
6.95E-02
R9 (°C/W)
4.06E-01
5.14E-01
R10 (°C/W)
4.93E+00
4.43E+00
R11 (°C/W)
9.38E+00
7.90E+00
R12 (°C/W)
2.99E+01
3.58E+01
C1 (W·sec/°C)
6.25E-04
1.55E-01
C2 (W·sec/°C)
3.81E-03
1.67E-01
C3 (W·sec/°C)
4.69E-03
1.19E+00
C4 (W·sec/°C)
2.41E-03
9.09E-01
C5 (W·sec/°C)
4.39E-03
1.84E-02
C6 (W·sec/°C)
3.27E-03
1.07E-03
C7 (W·sec/°C)
1.82E-02
1.77E-03
C8 (W·sec/°C)
1.32E-02
8.80E-02
C9 (W·sec/°C)
3.63E-03
1.19E-02
C10 (W·sec/°C)
6.72E-02
4.74E-02
C11 (W·sec/°C)
2.75E-02
2.35E-01
C12 (W·sec/°C)
2.22E+00
1.75E+00
Power loss calculation example
As a result of power loss calculation and thermal aspects, fully treated in the previous
sections, it is possible to simulate the maximum IC(RMS) current versus switching frequency
curves for a VVVF inverter using a 3-phase sinusoidal PWM and a six-step 120° switching
modulation to synthesize sinusoidal output currents.
The curves graphed in Figure 33 represent the maximum current managed by the SLLIMMnano in safety conditions, when the junction temperature rises to the maximum junction
temperature of 150 °C for three ambient temperatures (25, 50 and 75 °C), which is a typical
operating condition to guarantee the reliability of the system. These curves, functions of the
motor drive typology and control scheme, are simulated under the following conditions:
●
VPN = 300 V, ma = 0.8, cos = 0.6, Tj = 150 °C, Tc = 100 °C, fSINE = 60 Hz, max. value of
Rth(j-c), typical VCE(sat) and Etot values.
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Power losses and dissipation
AN4043
Figure 33. Maximum IC(RMS) current vs. fsw simulated curves
3-phase sinusoidal PWM
AM11821v1
0.9
VPN = 300 V, Modulation Index = 0.8,
PF = 0.6, Tj = 150 °C, f sine = 60 Hz
0.8
IC(RMS) (A)
0.7
0.6
0.5
Ta = 25°C
Ta = 50°C
Ta = 75°C
0.4
0.3
0.2
0
4
8
12
16
20
24
fsw (kHz)
Six-step 120 ° switching
AM11822v1
1.5
VPN = 300 V, Modulation Index = 0.8,
PF = 0.6, Tj = 150 °C, f sine = 60 Hz,
duty-cycle=60%
1.4
1.3
IC(RMS) (A)
1.2
1.1
Ta = 25°C
1
Ta = 50°C
Ta = 75°C
0.9
0.8
0.7
0.6
0
4
8
12
fsw (kHz)
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20
24
AN4043
5
Design and mounting guidelines
Design and mounting guidelines
This section introduces the main layout suggestions for an optimized design and major
mounting recommendations, to appropriately handle and assemble the SLLIMM-nano
family.
5.1
Layout suggestions
Optimization of PCB layout for high voltage and high switching frequency applications is a
critical point. PCB layout is a complex matter as it includes several aspects, such as length
and width of track and circuit areas, but also the proper routing of the traces and the
optimized reciprocal arrangement of the various system elements in the PCB area.
A good layout can help the application to properly function and achieve the expected
performance. On the other hand, a PCB without a careful layout can generate EMI issues
(both induced and perceived by the application), can provide overvoltage spikes due to
parasitic inductances along the PCB traces, and can produce higher power loss and even
malfunction in the control and sensing stages.
The compactness of the SLLIMM-nano solution, which offers an optimized gate driving
network and reduced parasitic elements, allows users to focus only on certain issues, such
as the ground issue or noise filter. Therefore, in order to avoid all the aforementioned
conditions, the following general guidelines and suggestions must be followed in PCB layout
for 3-phase applications.
5.1.1
General suggestions
●
PCB traces should be designed to be as short as possible and the area of the circuit
(power or signal) should be minimized to avoid the sensitivity of such structures to
surrounding noise.
●
Ensure a good distance between switching lines with high voltage transitions and the
signal line sensitive to electrical noise. Specifically, the tracks of each OUT phase,
bringing significant currents and high voltages, should be separated from the logic lines
and analog sensing circuit of the op amp and comparator.
●
Place the RSENSE resistors as close as possible to the low-side pins of the SLLIMMnano (NU, NV and NW). Parasitic inductance can be minimized by connecting the
ground line (also called driver ground) of the SLLIMM-nano directly to the cold terminal
of sense resistors. Use of a low inductance type resistor, such as an SMD resistor
instead of long-lead type resistors, can help to further decrease the parasitic
inductance.
●
Avoid any ground loop. Only a single path must connect two different ground nodes.
●
Place each RC filter as close as possible to the SLLIMM-nano pins in order to increase
their efficiency.
●
In order to prevent surge destruction, the wiring between the smoothing capacitor and
the P and N pins should be as short as possible. The use of a high frequency, high
voltage non-inductive capacitor about 0.1 or 0.22 µF between the P and N pins is
recommended.
●
Fixed voltage tracks, such as GND or HV lines, can be used to shield the logic and
analog lines from the electrical noise produced by the switching lines (e.g. U, V and W).
●
Generally it is recommended to connect each half bridge ground in a star configuration
and the three RSENSE very close to each other and to the power ground.
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Design and mounting guidelines
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In Figure 34, general suggestions for all SLLIMM-nano products are summarized.
Figure 34. General suggestions
S ignal ground and power ground mus t be connected at only one point
(star connections), avoiding long connections.
P le as e ens ure a s afety dis tances between ground tracks and noisy tracks
(high voltage or high frequency s ignals tracks)
Use of low inductance type res is tor,
s uch as S MD one, can help to
further decreas e the paras itic
inductance
S hunt res is tor
G ND
S D/OD
VCC W
VIN(WL) to
VIN(WH) MCU
V
V B OOT V
NU
U
P
S D/OD
L IN U
VIN(UH)
B us
c apac itor
to motor
VIN(UL)
to VDD
S hut down
Dec oupling
c apac itor
NV
OP VCC V
HIN V
L IN V
C IN
VCC U
HIN U
to
VIN(VL)
VIN(VH) MCU
P la ce an R C
filter directly
acros s S D pin
W
V B OOT W
HIN W
L IN W
OP +
OP OUT
P hase current
Layer 1
NW
+
+15V from
power
G ND s ource
P ower G ND (N)
V B OOT U
Layer 2
P la ce an R C filter directly acros s
the C IN (for each phase) pin to
avoid false s hort-circuit trigger
Boots trap capacitor s hould be
located as close as pos s ible
to the SLLIMM-nano pins
R educe all dis tances
between s hunt res is tors and
SLLIMM-nano power G ND
AM11823v1
Special attention must be paid to wrong layouts. In Figure 35 and Figure 36 some common
PCB mistakes are shown.
Figure 35. Example 1 on a possible wrong layout
W RONG !
S tub connections and vias produce
reflections , especially on critical s ignal
tracks. P refer s tar connections and
reduce number of vias
W RONG !
Decoupling capacitor is too far from
SLLIMM-nano.
C onnect it as close as pos s ible to the
P pin
S hunt res is tor
VIN(WL) to
VIN(WH) MCU
OP VCC V
HIN V
L IN V
C IN
VCC U
HIN U
P hase current
VIN(VL) to
VIN(VH) MCU
VIN(UL)
to VDD
S hut down
S D/OD
L IN U
VIN(UH)
Layer 1
W
V B OOT W
NV
to motor
HIN W
L IN W
OP +
OP OUT
Dec oupling
c apac itor
NW
V
V B OOT V
-
G ND
S D/OD
VCC W
+15V from
power
G ND s ource
P ower G ND (N)
+
W RONG !
R ight-angled track turns
produce a field concentration
at the inner edge.
P refer 45 angled tracks
B us
c apac itor
NU
U
P
V B OOT U
C IN
filter
Layer 2
W RONG !
Long dis tance between C IN filter and
SLLIMM-nano C IN pin. It is important to
minimize this dis tance in order to reduce
the noise impact
W RONG !
C IN filter ground is not the
s ame as per SLLIMM-nano
ground.
T his may cause noise
W RONG !
C IN filter is close to high voltage
s witching track (VB OOT).
Noise will influence comparator
performances
AM11824v1
52/60
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AN4043
Design and mounting guidelines
Figure 36. Example 2 on a possible wrong layout
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5.2
Mounting instructions and cooling techniques
The SLLIMM-nano is a very compact intelligent power module able to drive electric motors
up to 100 W without any heatsink or cooling system installed on the board. The NDIP is a
transfer mold package with no screw holes, therefore some dedicated cooling techniques
must be adopted if a higher power level is targeted.
One of the easiest methods is based on a natural cooling system and a proper design of the
PCB layout. In this case, the PCB, along with the pads, acts as a heatsink providing paths
for individual packages to effectively transfer heat to the board and the adjacent
environment. Therefore, maximizing the area of the metal traces where the power and
ground pins of the package are located is a valuable method for reducing the thermal
resistance and for leading to an improved power performance.
The pins mainly involved in this phenomenon are the positive DC pin (P) and the phase
output pins (U, V, W), since they are directly connected to the copper lead frame where the
power devices are mounted and IGBTs and diodes are the major source of heat, as already
treated in Section 4: Power losses and dissipation. Several aspects impact on the total
thermal performance, such as the area of metal traces, the thickness of the copper plate,
their placement on the board and the distance between the SLLIMM-nano and other heat
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Design and mounting guidelines
AN4043
sources. Both sides of the PCB can be used and thermally connected through direct copper
connections or thermal vias in order to increase the heat dissipation and reduce the layout
complexity.
Figure 37 shows an example of a metal trace layout used to dissipate heat on the PCB.
Figure 37. Cooling technique: copper plate on the PCB
AM11826v1
Higher thermal performance can be achieved by using a large and compact external
heatsink, in close contact with the SLLIMM-nano.
The heatsink can be directly fixed on the package thanks to thermal conductive glue or
adhesive foil between the heatsink and the backside of the package, as shown in Figure 38.
Figure 38. Cooling technique: heatsink bonded on the package
AM11827v1
An alternative method provides a heatsink (or plate) bonded on the package and fixed on
the PCB through a mounting screw, giving higher mechanical stability, as shown in
Figure 39. This heatsink installation method requires a uniform layer of thermal grease or
thermal rubber layer and needs a safety distance between the heatsink and the lateral side
of the SLLIMM-nano, where some cut pins appear.
54/60
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Design and mounting guidelines
Figure 39. Cooling technique: heatsink bonded on the PCB
AM11828v1
Finally, a large variety of solutions may exist which take advantage of the metal box in which
the board can eventually be housed.
Nevertheless, whatever the heatsink installation method may be, some precautions should
be observed to maximize the effect of the heatsink. Smoothen the surface by removing burrs
and protrusions; it is essential to ensure an optimal contact between the SLLIMM-nano and
the heatsink. Apply a uniform layer of silicon grease (or thermal conductive glue), from 100
µm up to 200 µm of thickness, between the device and the heatsink to reduce the contact
thermal resistance. Be sure to apply the coating thinly and evenly, taking care to not have
any voids remaining on the contact surface between the SLLIMM-nano and the heatsink.
We recommend using high quality grease with stable performance within the operating
temperature range of the SLLIMM-nano.
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General handling precaution and storage notices
6
AN4043
General handling precaution and storage notices
The incidence of thermal and/or mechanical stress to the semiconductor devices due to
improper handling may result in significant deterioration of their electrical characteristics
and/or reliability.
The SLLIMM-nano is an ESD sensitive device and it may be damaged in the case of ESD
shocks. All equipment used to handle power modules must comply with ESD standards
including transportation, storage, and assembly.
Transportation
Be careful when handling the SLLIMM-nano and packaging material. Ensure that the
module is not subjected to mechanical vibration or shock during transport. Do not throw or
drop in order to ensure that the SLLIMM-nano is correctly functioning before boarding. Wet
conditions are dangerous and moisture can also adversely affect the packaging. Hold the
package in such a way as to avoid touching the leads during mounting. Putting package
boxes upside down, leaning them at an angle, or giving them uneven stress may cause the
terminals to be deformed or the resin to be damaged.
Throwing or dropping the packaging boxes may cause the modules to be damaged. Wetting
the packaging boxes may cause the malfunction of modules when operating. Pay attention
when transporting in wet conditions.
Storage
●
Do not force or load external pressure on the modules while they are in storage
●
Humidity should be kept within the range of 40% to 75%, the temperature should not go
over 35 °C or below 5 °C
●
Lead solder ability is degraded by lead oxidation or corrosion. So using storage areas
where there is minimal temperature fluctuation is highly recommended
●
The presence of harmful gases or dusty conditions is not acceptable for storage
●
Use antistatic containers.
Electrical shock and thermal injury
●
56/60
Do not touch either module or heatsink when the SLLIMM-nano is operating to avoid
sustaining an electrical shock and/or a burn injury.
Doc ID 022726 Rev 2
AN4043
Packaging specifications
S
03 P VC
8313150_A
AM10474v1
Figure 40. Packaging specifications of NDIP-26L package
AN T IS T AT IC
6.1
General handling precaution and storage notices
Doc ID 022726 Rev 2
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References
7
Note:
58/60
AN4043
References
1.
AN3338 application note
2.
STGIPN3H60A datasheet
3.
STGIPN3H60 datasheet
4.
AN2738 application note
5.
UM1483 user manual
6.
UM1517 user manual
7.
Minimum-Loss Strategy for Three-Phase PWM Rectifier, IEEE, JUNE 1999
SLLIMM™ and PowerMESH™ are trademarks of STMicroelectronics.
Doc ID 022726 Rev 2
AN4043
8
Revision history
Revision history
Table 12.
Document revision history
Date
Revision
Changes
05-Apr-2012
1
Initial release.
17-Sep-2012
2
Updated: Figure 4 on page 9, Figure 17 on page 28, Figure 34 and
Figure 35 on page 52.
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AN4043
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