Data Sheet

PTN36241B
SuperSpeed USB 3.0 redriver
Rev. 4 — 22 May 2014
Product data sheet
1. General description
PTN36241B is a SuperSpeed USB 3.0 redriver IC that enhances signal quality by
performing receive equalization on the deteriorated input signal followed by transmit
de-emphasis maximizing system link performance. With its superior differential signal
conditioning and enhancement capability, the device delivers significant flexibility and
performance scaling for various systems with different PCB trace and cable channel
conditions and still benefit from optimum power consumption.
PTN36241B is a dual-channel device that supports data signaling rate of 5 Gbit/s through
each channel. PTN36241B has two channels: one channel is facing the USB host, and
another channel is facing the USB peripheral or device. Each channel consists of a
high-speed Transmit (Tx) differential lane and a high-speed Receive (Rx) differential lane.
PTN36241B has independent 5-level configuration pins for each channel to select receive
equalization, transmit de-emphasis and output swing and these pins can be easily
configured by board-strapping (for example, short, open, resistor). To support applications
that require greater level of configurability, PTN36241B delivers intelligent multiplexing of
I2C-bus interface onto 5-level configuration pins. By default, the device is configured with
the board-strapped levels of configuration pins. When I2C-bus reads/writes are performed
over these multiplexed pins, the device decodes I2C transactions and configures its
internal functions appropriately.
PTN36241B has built-in advanced power management capability that enables significant
power savings under various different USB 3.0 Low-power modes (U2/U3). It can detect
LFPS signaling and link electrical conditions and can dynamically activate/de-activate
internal circuitry and logic. The device performs these actions without host software
intervention and conserves power.
PTN36241B goes through the compliance testing controlled by the internal state machine.
No compliance pin is required.
PTN36241B is powered from 3.3 V supply and is available in HVQFN24 4 mm  4 mm
package with 0.5 mm pitch.
2. Features and benefits
2.1 High-speed channel processing
 Supports USB 3.0 specification (SuperSpeed only)
 Support of 2 channels
 Selectable receive equalization on each channel to recover from InterSymbol
Interference (ISI) and high-frequency losses, with provision to choose from five
Equalization gain settings per channel
PTN36241B
NXP Semiconductors
SuperSpeed USB 3.0 redriver
 Selectable transmit de-emphasis and output swing on each channel delivers
pre-compensation suited to channel conditions
 Supports pin and I2C-bus programmable Input Signal Threshold setting to work
reliably under different noise environments accommodating sensitivity needs
 Integrated termination resistors provide impedance matching on both transmit and
receive sides
 Programmable termination resistor for receiver side
 Automatic receiver termination indication and detection
 Low active power: 330 mW/100 mA (typical), VDD = 3.3 V
 Power-saving states:
 53 mW/16 mA (typical) when in U2/U3 states
 20 mW/6 mA (typical) when no connection detected
 Excellent differential and common return loss performance
 14 dB differential and 15 dB common-mode return loss for 10 MHz to 1250 MHz
 Flow-through pinout to ease PCB layout and minimize crosstalk effects
 Hot Plug capable
 Supports EasyCom that goes through the compliance testing controlled by the internal
state machine
 Power supply: VDD = 3.3 V  10 %
 HVQFN24 4 mm  4 mm package, 0.5 mm pitch; exposed center pad for thermal relief
and electrical ground
 ESD: 5 kV HBM, 1250 V CDM
 Operating temperature range 0 C to 85 C
2.2 Enhancements
 Intelligent I2C-bus multiplexing and 5-level logic configuration options (with
patent-pending quinary pins) delivering ultimate flexibility
 I2C-bus interface:
 Standard-mode (100 kbit/s) or Fast-mode (400 kbit/s)
 3.3 V tolerant
3. Applications






PTN36241B
Product data sheet
Notebook/netbook/nettop platforms
Docking stations
Desktop and AIO platforms
Active cables
Server and storage platforms
USB 3.0 peripherals like consumer/storage devices, printers or USB 3.0 capable
hubs/repeaters
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4. System context diagrams
Figure 1 illustrates PTN36241B usage.
AOUT+
AIN-
AOUT-
CPU/CHIP SET/
USB HOST
CONTROLLER
PTN36241B
Rx
BOUT-
BIN-
BOUT+
BIN+
USB cable
CONNECTOR
AIN+
USB
PERIPHERAL
CONNECTOR
Tx
CONNECTOR
MOTHERBOARD
USB
PERIPHERAL
MOTHERBOARD
Tx
CPU/CHIP SET/
USB HOST
CONTROLLER
DOCKING
STATION
AIN+
AOUT+
AIN-
AOUT-
CONNECTOR
Rx
PTN36241B
BOUT-
BIN-
BOUT+
BIN+
USB cable
USB cable
CONNECTOR
COMPUTER
PLATFORM
WITH
USB 3.0 HOST
CONTROLLER
CONNECTOR
USB 3.0 PERIPHERAL/DEVICE
AIN+
AOUT+
AIN-
AOUT-
PTN36241B
BOUT-
BIN-
BOUT+
BIN+
FUNCTION
WITH USB 3.0
DEVICE
CONTROLLER
002aag030
Fig 1.
PTN36241B context diagrams
PTN36241B
Product data sheet
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5. Ordering information
Table 1.
Ordering information
Type number
PTN36241BBS
[1]
Topside
marking
Package
Name
Description
Version
241B
HVQFN24
plastic thermal enhanced very thin quad flat package; no leads;
24 terminals; body 4  4  0.85 mm[1]
SOT616-3
Maximum package height is 1 mm.
5.1 Ordering options
Table 2.
Ordering options
Type number
Orderable
part number
Package
Packing method[1]
Minimum
order
quantity
Temperature
PTN36241BBS
PTN36241BBS,115
HVQFN24
Reel 7” Q1/T1
*Standard mark SMD
1500
Tamb = 0 C to 85 C
PTN36241BBS,118
HVQFN24
Reel 13” Q1/T1
*Standard mark SMD
6000
Tamb = 0 C to 85 C
PTN36241BBS,128
HVQFN24
Reel 13” Q2/T3
*Standard mark SMD
6000
Tamb = 0 C to 85 C
[1]
Refer to Figure 13 “Product orientation in carrier tape” for pin 1 location.
6. Block diagram
VDD = 3.3 V
PTN36241B
line
driver
equalizer
AIN+
AIN−
AOUT+
AOUT−
EMPHASIS
FILTER
SQUELCH
AND LFPS
DETECTION
RX
TERMINATION
DETECTION
line
driver
equalizer
BOUT+
BOUT−
BIN+
BIN−
EMPHASIS
FILTER
RX
TERMINATION
DETECTION
SQUELCH
AND LFPS
DETECTION
DEVICE CONTROL AND MANAGEMENT
002aaf796
AEQ
CEN
Fig 2.
PTN36241B
Product data sheet
AOS
BEQ/SDA
ADE/ADD
BOS
SQTH
BDE/SCL
Block diagram of PTN36241B
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SuperSpeed USB 3.0 redriver
7. Pinning information
19 BIN+
20 BIN−
21 GND
22 AOUT+
terminal 1
index area
23 AOUT−
24 n.c.
7.1 Pinning
VDD(3V3)
1
18 GND
AEQ
2
17 BEQ/SDA
ADE/ADD
3
AOS
4
CEN
5
GND
6
16 BDE/SCL
PTN36241BBS
15 BOS
14 RES
GND
BOUT+ 12
9
AIN+
BOUT− 11
8
AIN−
GND 10
7
SQTH
13 VDD(3V3)
002aaf799
Transparent top view
Fig 3.
Pin configuration for HVQFN24
7.2 Pin description
Table 3.
Pin description
Symbol
Pin
Type
Description
High-speed differential signals
PTN36241B
Product data sheet
AIN+
9
self-biasing
differential input
Differential signal from SuperSpeed USB 3.0 transmitter.
AIN+ makes a differential pair with AIN. The input to this
pin must be AC-coupled externally.
AIN
8
self-biasing
differential input
Differential signal from SuperSpeed USB 3.0 transmitter.
AIN makes a differential pair with AIN+. The input to this
pin must be AC-coupled externally.
BOUT+
12
self-biasing
Differential signal to SuperSpeed USB 3.0 receiver.
differential output BOUT+ makes a differential pair with BOUT. The output
of this pin must be AC-coupled externally.
BOUT
11
self-biasing
Differential signal to SuperSpeed USB 3.0 receiver.
differential output BOUT makes a differential pair with BOUT+. The output
of this pin must be AC-coupled externally.
AOUT+
22
self-biasing
Differential signal to SuperSpeed USB 3.0 receiver.
differential output AOUT+ makes a differential pair with AOUT. The output
of this pin must be AC-coupled externally.
AOUT
23
self-biasing
Differential signal to SuperSpeed USB 3.0 receiver.
differential output AOUT makes a differential pair with AOUT+. The output
of this pin must be AC-coupled externally.
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Table 3.
Pin description …continued
Symbol
Pin
Type
Description
BIN+
19
self-biasing
differential input
Differential signal from SuperSpeed USB 3.0 transmitter.
BIN+ makes a differential pair with BIN. The input to this
pin must be AC-coupled externally.
BIN
20
self-biasing
differential input
Differential signal from SuperSpeed USB 3.0 transmitter.
BIN makes a differential pair with BIN+. The input to this
pin must be AC-coupled externally.
Configuration and control signals
CEN
5
CMOS input
Chip enable input (active HIGH); internally pulled-up.
If CEN is LOW, then the device is in Deep power-saving
state even if supply rail is ON; for the device to be able to
operate, the CEN pin must be HIGH.
RES
14
CMOS input
Reserved. Tie this pin to ground for normal operation.
AOS
4
input
5-level configuration pin for channel A Tx output swing
setting.
BOS
15
input
5-level configuration pin for channel B Tx output swing
setting.
AEQ
2
input
5-level configuration pin for channel A Rx equalization
gain setting.
BEQ/SDA 17
input/output
5-level configuration pin for channel B Rx equalization
gain setting or I2C-bus data pin.
ADE/ADD 3
input
5-level configuration pin for channel A Tx de-emphasis
setting or in I2C mode, this ADD pin enables selection of
1 out of 4 I2C-bus device addresses.
BDE/SCL
16
input/output
5-level configuration pin for channel B Tx de-emphasis
setting or I2C-bus clock pin
SQTH
7
input
5-level configuration pin for Channels A and B minimum
input signal threshold setting.
n.c.
24
-
not connected
power
3.3 V supply.
Power supply
VDD(3V3)
1, 13
Ground connection
PTN36241B
Product data sheet
GND
6, 10,
18, 21
power
Ground.
GND
center
pad
power
The center pad must be connected to GND plane for both
electrical grounding and thermal relief.
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SuperSpeed USB 3.0 redriver
8. Functional description
Refer to Figure 2 “Block diagram of PTN36241B”.
PTN36241B is a SuperSpeed USB 3.0 redriver meant to be used for signal integrity
enhancement on various platforms – notebooks, docking, desktop, AIO, peripheral
devices etc. With its high fidelity differential signal conditioning capability and wide
configurability, this chip is flexible and versatile enough for use under various system
environments.
The following sections describe the individual block functions and capabilities of the
device in more detail.
8.1 Receive equalization
On the high-speed signal path, the device performs receive equalization providing
frequency selective gain based on the configuration pin AEQ (BEQ) setting. Table 4 lists
the configuration options available in this device.
Table 4.
AEQ (BEQ) configuration options
5-level control input setting AEQ (BEQ)
SuperSpeed USB 3.0 signal equalization gain at
2.5 GHz
open
4.5 dB
short to GND
7.5 dB
short to VDD(3V3)
9 dB
pull-down resistor to GND[1]
pull-up resistor to VDD(3V3)
[1]
[1]
6 dB
15 dB
The value of these pull-up and pull-down resistors is 75 k.
Refer also to Section 8.4 for I2C-bus interface based configuration options for Rx
equalization of channels A and B.
8.2 Transmit de-emphasis and output swing
The PTN36241B device enhances signal content further by performing de-emphasis on
the high-speed signals. In addition, the device can provide flat frequency gain by boosting
output signal. Both flat and frequency selective gains prepare the system to cover up for
losses further down the link. Table 5 lists de-emphasis and Table 6 lists output swing
configuration options of PTN36241B.
Table 5.
PTN36241B ADE (BDE) configuration options
5-level control input setting ADE (BDE)
SuperSpeed USB 3.0 signal de-emphasis gain
open
3.5 dB
short to GND
6.0 dB
9.5 dB
short to VDD(3V3)
pull-down resistor to
GND[1]
pull-up resistor to VDD(3V3)
[1]
PTN36241B
Product data sheet
[1]
0 dB
6.0 dB
The value of these pull-up and pull-down resistors is 75 k.
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SuperSpeed USB 3.0 redriver
Table 6.
PTN36241B AOS (BOS) configuration options
5-level control input setting AOS (BOS)
SuperSpeed USB 3.0 transmit differential output
swing (peak-to-peak)
open
1000 mV
short to GND
850 mV
1100 mV
short to VDD(3V3)
pull-down resistor to
GND[1]
400 mV
[1]
600 mV
pull-up resistor to VDD(3V3)
[1]
The value of these pull-up and pull-down resistors is 75 k.
Figure 4 illustrates de-emphasis as a function of time for different settings.
1 bit
1 to N bits
1 bit
1 to N bits
VTX_DIFF_DEp-p
VTX_CM_DC
VTX_DIFFp-p
002aag010
Fig 4.
Output with 6 dB de-emphasis
Please refer also to Section 8.4 for I2C-bus interface based configuration options for
de-emphasis and output swing of Channels A and B.
8.3 Input signal threshold
To support various platforms that have different noise levels and still maintain sensitivity,
PTN36241B provides configuration option to set input signal threshold. When the signal
level falls below the threshold, the outputs are squelched and when signal is above the
threshold, redriving function is activated. Table 7 lists the possible input signal threshold
configuration options available with this device.
Table 7.
SQTH configuration options
5-level control input setting
Channel A input threshold
(peak-to-peak)
Channel B input threshold
(peak-to-peak)
short to GND
100 mV
100 mV
short to VDD(3V3)
125 mV
125 mV
open
75 mV
75 mV
GND[1]
150 mV
150 mV
pull-up resistor to VDD(3V3)[1]
175 mV
175 mV
pull-down resistor to
PTN36241B
Product data sheet
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[1]
The value of these pull-up and pull-down resistors is 75 k.
Please refer also to Section 8.4 for I2C-bus interface based configuration options.
8.4 I2C-bus programmability
PTN36241B has I2C-bus interface that enables system integrator to program register
settings suitable for the application needs. Table 8 describes possible settings for different
functions of the device. Although the device can be pin configured through
board-strapping, it also allows the system integrator to override the settings by
programming the internal registers through I2C.
After power-on, the device samples the board-strapped pin values (as I2C is not
operational yet) but does not reflect these directly in the register (default) values. So in
applications using I2C-bus interface, the system integrator must program the internal
registers of the device for proper operation. Further, it is expected that the system
integrator performs I2C configuration after power-on and not during normal operation. If
such an operation is attempted during normal operation, the device may not behave as
specified.
Table 8.
I2C-bus registers and description
Values indicated are typical only.
Register Register name
offset
Bit
Reset
value
Description
00
7:5
100b
Channel A de-emphasis level.
A_Tx_Control
If 0 to 3, set channel A de-emphasis as follows:
0 — set de-emphasis to 0 dB
1 — set de-emphasis to 3.5 dB
2 — set de-emphasis to 6 dB
3 — set de-emphasis to 9.5 dB
If 4 to 7, ADE pin controls channel A de-emphasis level.
4:0
00000b
Channel A output voltage swing.
At Power-On Reset (POR), these bits are set to 0 and AOS quinary pin
sets voltage swing. Use these bits to select one of the 24 output levels.
If 1 to 24, the channel A output swing is 50 mV times the value of the
register.
If 0, AOS pin controls channel A Tx output swing level.
01
A_signal_det
7:4
0x8
Controls the channel A squelch level (differential peak-to-peak value).
0000b — 75 mV
0001b — 100 mV
0010b — 125 mV
0011b — 150 mV
0100b — 175 mV
0101b — 200 mV
0110b — 225 mV
0111b — 250 mV
1000b to 1111b — use the value selected by SQTH pin
3:0
PTN36241B
Product data sheet
0
Reserved; must be 0.
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Table 8.
I2C-bus registers and description …continued
Values indicated are typical only.
Register Register name
offset
Bit
Reset
value
Description
02
7:0
0x8D
Adjusts the A channel receive termination.
A_Rx_termination
0x7C for 40  receive termination
0x8D for 45  receive termination
0xA0 for 50  receive termination
03
A_Equalizer
7:5
0
Reserved; must be 0.
4:0
0x18
Channel A Rx equalization gain.
If 0x18, equalizer setting is controlled by the AEQ quinary pin.
00000b — 0 dB
00001b — 1.5 dB
00010b — 3.0 dB
00011b — 4.5 dB
00100b — 6.0 dB
00101b — 7.5 dB
00110b — 9.0 dB
00111b — 10.5 dB
01111b — 12.0 dB
10111b — 13.5 dB
11111b — 15.0 dB
11000b — AEQ quinary pin sets channel A equalization.
04
B_Tx_control
7:5
100b
Channel B de-emphasis level.
If 0 to 3, set channel B de-emphasis as follows:
0 — set de-emphasis to 0 dB
1 — set de-emphasis to 3.5 dB
2 — set de-emphasis to 6 dB
3 — set de-emphasis to 9.5 dB
If 4 to 7, BDE pin controls channel B de-emphasis level.
4:0
00000b
Channel B output voltage swing.
At Power-On Reset (POR), these bits are set to 0 and BOS quinary pin
sets voltage swing. Use these bits to select one of the 24 output levels.
If 1 to 24, the channel B output swing is 50 mV times the value of the
register.
If 0, the BOS pin controls channel B Tx output swing level.
PTN36241B
Product data sheet
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Table 8.
I2C-bus registers and description …continued
Values indicated are typical only.
Register Register name
offset
Bit
Reset
value
Description
05
7:4
0x8
Controls the channel B squelch level (differential peak-to-peak value).
B_signal_det
0000b — 75 mV
0001b — 100 mV
0010b — 125 mV
0011b — 150 mV
0100b — 175 mV
0101b — 200 mV
0110b — 225 mV
0111b — 250 mV
1000b to 1111b — use the value selected by SQTH pin
06
B_Rx_termination
3:0
0
Reserved; must be 0.
7:0
0x8D
Adjusts the B channel receive termination.
0x7C for 40  receive termination
0x8D for 45  receive termination
0xAD for 50  receive termination
07
B_equalizer
7:5
001b
Reserved; must be 001b.
4:0
0x18
Channel B Rx equalization gain.
If 0x18, equalizer setting is controlled by the BEQ quinary pin.
00000b — 0 dB
00001b — 1.5 dB
00010b — 3.0 dB
00011b — 4.5 dB
00100b — 6.0 dB
00101b — 7.5 dB
00110b — 9.0 dB
00111b — 10.5 dB
01111b — 12.0 dB
10111b — 13.5 dB
11111b — 15.0 dB
11000b — BEQ quinary pin sets channel B equalization.
40
I2C_access_enable
44
reset
At POR, this is the only I2C-bus register enabled for reading and writing.
Set this register to 0xAE to unlock I2C registers.
0
Writing a 1 to this register resets the part. This is a self-clearing bit.
8.4.1 I2C-bus read and write operations
PTN36241B supports programming of the internal registers through the I2C-bus interface.
Reading/writing the internal registers must be done according to the following protocol.
The read protocol contains two phases:
• Command phase
• Data phase
PTN36241B
Product data sheet
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The command phase is an I2C write to PTN36241B that contains a single data byte
indicating the internal register address to read out. The data phase is an I2C read
operation that contains 4 bytes of data, starting from the least significant byte.
The I2C write operation contains only the command phase, which contains 8-bit internal
register address, followed by 4 bytes of data to be written to the register, starting from the
least significant byte.
PTN36241B is able to handle both single-byte and 4-byte write/read commands. 4-byte
read/write commands are address aligned with 2 LSBs as ‘0’. Figure 5 illustrates the
protocol used on the I2C-bus to read and write registers inside the device.
R/W(1)
Command
phase
START 7 bits slave address
0
ACK
8-bit offset
ACK
STOP
Data
phase
START 7 bits slave address
1
ACK
bits 7:0 of the register data
ACK
bits 15:8 of the register data
bits 23:16 of the register data
ACK
bits 31:24 of the register data
ACK
ACK
STOP
driven by master
driven by slave
002aah254
(1) R/W = read/write bit. 0b = I2C write; 1b = I2C read.
a. Read sequence
R/W(1)
START 7 bits slave address
0
ACK
8-bit offset
ACK
bits 7:0 of the register data
ACK
bits 15:8 of the register data
ACK
bits 23:16 of the register data
ACK
bits 31:24 of the register data
ACK
STOP
driven by master
driven by slave
002aah255
(1) R/W = read/write bit. 0b = I2C write; 1b = I2C read.
b. Write sequence
Fig 5.
I2C-bus read and write sequences
PTN36241B
Product data sheet
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Table 9 shows how the PTN36241B device addresses can be selected by using ADD
(I2C-bus device address) pin.
Table 9.
Device address selection
ADD pin
7-bit I2C-bus device address
short to GND
0010 010b
short to VDD(3V3)
0010 010b
pull-down resistor to GND[1]
0010 110b
[1]
0011 110b
pull-up resistor to VDD(3V3)
open
[1]
0011 010b
The value of these pull-up and pull-down resistors is 75 k.
PTN36241B has built-in I2C access lock mechanism that helps avoid inadvertent
writes/reads into the device. After power-up, only register offset 0x40 can be written by the
host controller. So before accessing any register (register offset 0x00 to 0x07, 0x41), the
host controller is expected to write 0xAE at address 0x40. This would open the I2C lock
enabling the host controller to configure the device registers suitably as required for the
application.
8.5 Device control — mode, enable, power-on initialization
PTN36241B has a built-in reset circuitry that generates reset signal after power-on. All the
internal registers and state machines are initialized and the registers take default values
as defined in Table 8.
The CEN enable pin can be toggled asynchronously any time after power-on and the
device can be put in Active or Deep power-saving state.
• When CEN is HIGH, the device is in Active state and when it is LOW, device is in
Deep power-saving state.
• The values of the configuration pins (AEQ, ADE, BEQ, BDE, AOS, BOS, SQTH) are
sampled on power-on and whenever CEN is toggled asynchronously any time
afterwards.
• When CEN is toggled LOW to HIGH, the device undergoes an equivalent of power-on
reset operation. All registers/state machines are put to power-on condition.
The normal functioning of the redriver is not guaranteed when the configuration and/or
control pins are being changed. The typical device usage is to set these control and
configuration pins to pre-determined levels at power-on and not to change thereafter.
PTN36241B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 22 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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NXP Semiconductors
SuperSpeed USB 3.0 redriver
8.6 Device states and power management
PTN36241B has implemented an advanced power management scheme that operates in
tune with USB 3.0 bus electrical condition. Although the device does not decode USB
power management commands (related to USB 3.0 U1/U2/U3 transitions) exchanged
between USB 3.0 host and peripheral/device, it relies on bus electrical conditions and
control pins/register settings to decide to be in one of the following states:
• Active state wherein device is fully operational, USB data is transported on
channels A and B. In this state, USB connection exists and the Receive Termination
indication remains active. But there is no need for Receive Termination detection.
• Power-saving state wherein the channels A and B are kept enabled. In this state,
squelching, LFPS detection and/or Receive termination detection circuitry are active.
Based on USB connection, there are 2 possibilities:
– No USB connection:
Receive Termination detection circuitry keeps polling periodically.
Receive Termination indication is not active.
– When USB connection exists, and when the link is in USB 3.0 U2/U3 mode:
Receive Termination detection circuitry keeps polling periodically.
Receive Termination indication is active.
• Deep power-saving or Shutdown state wherein the channel is in
Deep power-saving/Shutdown condition enabling significant power saving.
– DC common-mode voltage level is not maintained.
– Tx and Rx terminations are put to high-impedance condition.
– Transitioning to Active state would take several tens of microseconds.
Receive termination detection circuitry is implemented as part of a transmitter and
detect whether a load device with equivalent DC impedance ZRX_DC is present.
PTN36241B
Product data sheet
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Rev. 4 — 22 May 2014
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NXP Semiconductors
SuperSpeed USB 3.0 redriver
9. Limiting values
Table 10. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Min
Max
Unit
supply voltage (3.3 V)
[1]
0.3
+4.6
V
VI
input voltage
[1]
0.3
VDD(3V3) + 0.5 V
Tstg
storage temperature
65
+150
C
HBM
[2]
-
5000
V
CDM
[3]
-
1250
V
VDD(3V3)
VESD
Parameter
Conditions
electrostatic discharge
voltage
[1]
All voltage values (except differential voltages) are with respect to network ground terminal.
[2]
Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model Component level; Electrostatic Discharge Association, Rome, NY, USA.
[3]
Charged Device Model; ANSI/EOS/ESD-S5.3-1-1999, standard for ESD sensitivity testing, Charged Device
Model - Component level; Electrostatic Discharge Association, Rome, NY, USA.
10. Recommended operating conditions
Table 11.
Operating conditions
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD
supply voltage
3.3 V supply option
3.0
3.3
3.6
V
VI
input voltage
open-drain I/O with
respect to ground
(e.g., SCL, SDA)
-
VDD(3V3) -
V
control and configuration
pins (e.g., AEQ, BEQ,
ADE, BDE, AOS, BOS,
SQTH)
-
VDD(3V3) -
V
0
-
C
Tamb
PTN36241B
Product data sheet
ambient temperature operating in free air
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85
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NXP Semiconductors
SuperSpeed USB 3.0 redriver
11. Characteristics
11.1 Device characteristics
Table 12.
Device characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tstartup
start-up time
supply voltage within operating range to
specified operating characteristics
-
-
20
ms
ts(LH)
LOW to HIGH
settling time
disable to enable; CEN LOW  HIGH change
to specified operating characteristics; device is
supplied with valid supply voltage
-
-
1
ms
ts(HL)
HIGH to LOW
settling time
enable to disable; CEN HIGH  LOW change
to specified operating characteristics; device is
supplied with valid supply voltage
-
-
1
ms
trcfg
reconfiguration time
any quinary configuration pin change (AEQ,
BEQ, ADE, BDE, AOS, BOS, SQTH - from one
setting to another setting) to specified operating
characteristics; device is supplied with valid
supply voltage; reconfiguration can be triggered
by CEN toggle
-
-
100
s
tPD(dif)
differential propagation
delay
between 50 % level at input and output;
see Figure 6
-
-
1
ns
tidle
idle time
default wait time to wait before getting into
U2/U3 Power-saving states
-
300
-
ms
td(pwrsave-act) delay time from
power-save to active
time for exiting from Power-saving state and get
into Active state; see Figure 8
-
10
-
s
td(act-idle)
delay time from active
to idle
reaction time for squelch detection circuit;
see Figure 7
-
-
54
ns
td(idle-act)
delay time from idle
to active
reaction time for squelch detection circuit;
see Figure 7
-
4
6
ns
IDD
supply current
Active state; Rx equalization = 15 dB;
Tx output signal swing = 400 mV (differential
peak-to-peak value); Tx de-emphasis = 0 dB
-
100
-
mA
U2/U3 Power-saving state
-
16
-
mA
no USB connection state
-
6
-
mA
Deep power-saving state; CEN = LOW
-
-
3.5
mA
IN+
in
VSQTH
VDC_CM
IN−
tPD(dif)
tPD(dif)
td(idle-act)
td(act-idle)
OUT+
out
VDC_CM
002aag025
Fig 6.
Propagation delay
PTN36241B
Product data sheet
OUT−
Fig 7.
Electrical idle transitions in U0/U1 modes
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002aag026
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NXP Semiconductors
SuperSpeed USB 3.0 redriver
channel A, RX
U2 exit LFPS
RECOVERY
U2 exit LFPS
channel A, TX
channel B, RX
RECOVERY
RECOVERY
U2 exit handshake LFPS
U2 exit handshake LFPS
channel B, TX
RECOVERY
block active
td(pwrsave-act)
002aag028
Fig 8.
U2/U3 exit behavior
11.2 Receiver AC/DC characteristics
Table 13.
Receiver AC/DC characteristics
Symbol
Parameter
ZRX_DC
receiver DC common-mode impedance
ZRX_DIFF_DC
DC differential impedance
RX pair
ZIH
HIGH-level input impedance
DC input
VRX(diff)(p-p)
peak-to-peak differential receiver voltage
VRX_DC_CM
RX DC common mode voltage
-
1.8
-
V
VRX_CM_AC_P
RX AC common-mode voltage
peak
-
-
150
mV
Vth(i)
input threshold voltage
differential
peak-to-peak value
75
-
300
mV
PTN36241B
Product data sheet
Conditions
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 22 May 2014
Min
Typ
Max
Unit
20
-
28

72
-
120

25
-
-
k
75
-
1200
mV
© NXP Semiconductors N.V. 2014. All rights reserved.
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NXP Semiconductors
SuperSpeed USB 3.0 redriver
11.3 Transmitter AC/DC characteristics
Table 14.
Transmitter AC/DC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ZTX_DC
transmitter DC common-mode
impedance
18
-
30

ZTX_DIFF_DC
DC differential impedance
VTX_DIFFp-p
differential peak-to-peak
output voltage
72
-
120

400
-
1200
mV
VTX_DC_CM
transmitter DC common-mode
voltage
1.2
-
1.65
V
VTX_CM_ACpp_ACTIV
TX AC common-mode
peak-to-peak output voltage
(active state)
device input fed with
differential signal
-
-
100
mV
VTX_IDL_DIFF_ACpp
electrical idle differential
peak-to-peak output voltage
when link is in electrical idle
-
-
10
mV
VTX_RCV_DETECT
voltage change allowed during
receiver detection
positive voltage swing to
sense the receiver
termination detection
-
-
600
mV
tr(tx)
transmit rise time
measured using 20 % and
80 % levels; see Figure 9
30
50
-
ps
tf(tx)
transmit fall time
measured using 80 % and
20 % levels; see Figure 9
30
50
-
ps
t(r-f)tx
difference between transmit
rise and fall time
measured using 20 % and
80 % levels
-
-
20
ps
typical level decided by
configuration pin/I2C
register setting
80 %
20 %
tr(tx)
tf(tx)
002aag027
Fig 9.
PTN36241B
Product data sheet
Output rise and fall times
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NXP Semiconductors
SuperSpeed USB 3.0 redriver
11.4 Jitter performance
Table 15 provides jitter performance of PTN36241B under a specific set of conditions that
is illustrated by Figure 6.
Table 15. Jitter performance characteristics
Unit Interval (UI) = 200 ps.
Symbol
Parameter
Conditions
tjit(o)(p-p)
peak-to-peak output jitter time
total jitter at test point C
tjit(dtrm)(p-p)
peak-to-peak deterministic jitter time
tjit(rndm)(p-p)
peak-to-peak random jitter time
Min
Typ
Max
Unit
[1]
-
0.19
-
UI
[1]
-
0.11
-
UI
[1][2]
-
0.08
-
UI
[1]
Measured at test point C with K28.5 pattern, VID = 1000 mV (peak-to-peak), 5 Gbit/s; 3.5 dB de-emphasis from source.
[2]
Random jitter calculated as 14.069 times the RMS random jitter for 1012 bit error rate.
less than 76.2 cm (30-inch) FR4 trace
AWG
SIGNAL
SOURCE
test point A
test point C
test point B
PTN36241B
SMA
connector
SMA
connector
002aag032
Fig 10. Jitter measurement setup
11.5 Control inputs
Table 16.
CMOS control input characteristics (CEN and RES pins)
Symbol
Parameter
VIH
HIGH-level input voltage
VIL
LOW-level input voltage
ILI
input leakage current
PTN36241B
Product data sheet
Conditions
measured with input at
VIH(max) and VIL(min)
Min
Max
Unit
0.65  VDD(3V3) -
-
V
-
-
0.35  VDD(3V3) V
-
-
25
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Rev. 4 — 22 May 2014
Typ
A
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NXP Semiconductors
SuperSpeed USB 3.0 redriver
12. Package outline
+94)1SODVWLFWKHUPDOHQKDQFHGYHU\WKLQTXDGIODWSDFNDJHQROHDGV
WHUPLQDOVERG\[[PP
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627
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GHWDLO;
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/
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Z
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Fig 11. Package outline SOT616-3 (HVQFN24)
PTN36241B
Product data sheet
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Rev. 4 — 22 May 2014
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NXP Semiconductors
SuperSpeed USB 3.0 redriver
13. Packing information
Packing information for SOT616-3 (HVQFN24).
13.1 Packing method
3ULQWHGSODQRER[
%DUFRGHODEHO
5HHO
7DSH
4$6HDO
3UHSULQWHG(6'ZDUQLQJ
34ODEHOSHUPDQHQW
&LUFXODUVSURFNHWKROHVRSSRVLWHWKH
ODEHOVLGHRIUHHO
&RYHUWDSH
&DUULHUWDSH
DDN
Fig 12. Reel pack for SMD
Table 17.
PTN36241B
Product data sheet
Dimensions and quantities
Orderable
part number
Reel dimensions
d  w (mm)
SPQ/PQ
(pcs)
Reels
per box
Outer box dimensions
l  w  h (mm)
PTN36241BBS,115
180  12
1500
1
191  188  26
PTN36241BBS,118
330  12
6000
1
341  338  26
PTN36241BBS,128
330  12
6000
1
341  338  26
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 22 May 2014
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NXP Semiconductors
SuperSpeed USB 3.0 redriver
13.2 Product orientation
SLQ
SLQ
DDD
DDD
a. PTN36241BBS,115;
PTN36241BBS,118
b. PTN36241BBS,128
Fig 13. Product orientation in carrier tape
13.3 Carrier tape dimensions
PP
:
.
$
%
3
7
GLUHFWLRQRIIHHG
DDR
Fig 14. Carrier tape dimensions
Table 18. Carrier tape dimensions
In accordance with IEC 60286-3.
PTN36241B
Product data sheet
A0 (mm)
B0 (mm)
K0 (mm)
T (mm)
P1 (mm)
W (mm)
4.3
4.3
1.1
-
8
12
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Rev. 4 — 22 May 2014
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NXP Semiconductors
SuperSpeed USB 3.0 redriver
13.4 Reel dimensions
'
=
:
PPPLQ
PP PP
PLQ
PLQ
5PP
GHWDLO=
DDD
6FKHPDWLFYLHZRIUHHO
Fig 15. Schematic view of reel
Table 19. Reel dimensions
In accordance with IEC 60286-3.
PTN36241B
Product data sheet
Orderable part number
D (mm)
W (mm)
PTN36241BBS,115
180
12
PTN36241BBS,118
330
12
PTN36241BBS,128
330
12
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Rev. 4 — 22 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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NXP Semiconductors
SuperSpeed USB 3.0 redriver
13.5 Barcode label
)L[HGWH[W
&RXQWU\RIRULJLQ
LH0DGHLQRU
'LIIXVHGLQ(8>@
$VVHPEOHGLQ
3DFNLQJXQLW34LGHQWLILFDWLRQ
QGWUDFHDELOLW\ORWQXPEHU
QG\RXQJHVWGDWHFRGH
QG4XDQWLW\
7UDFHDELOLW\ORWQXPEHU
'DWHFRGH
:LWKOLQHDUEDUFRGH
4XDQWLW\
:LWKOLQHDUEDUFRGH
7\SHQXPEHU
1;31&
:LWKOLQHDUEDUFRGH
1;36(0,&21'8&7256
0$'(,1!&28175<
>352'8&7,1)[email protected]
447<
2SWLRQDOSURGXFWLQIRUPDWLRQ
5HDSSURYDOGDWHFRGH
2ULJLQFRGH
3URGXFW0DQXIDFWXULQJ&RGH
06/DWWKH3HDN%RG\VROGHU
WHPSHUDWXUHZLWKWLQOHDG
06/DWWKHKLJKHUOHDGIUHH
3HDN%RG\7HPSHUDWXUH
'PDWUL[ZLWKDOOGDWD
LQFOXGLQJWKHGDWDLGHQWLILHUV
+$/2*(1)5((
37<3(
5R+6FRPSOLDQW
3&2'(12
$GGLWLRQDOLQIRLIKDORJHQ
IUHHSURGXFW
$GGLWLRQDOLQIRRQ5R+6
738,'%
7/27
'5('$7(
''$7( 725,*
447<
730&
306/3%7
7/27
06/3%7
''$7(
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Fig 16. Box information barcode
1;3$66(0%/(',1!&28175<
37<3(
+$/2*(1)5((
7/27
447<
(8&15R+6FRPSOLDQW
''$7(
3&2'(12
DDN
Fig 17. Reel information barcode
Table 20.
Barcode dimensions
Box barcode label
l  w (mm)
Reel barcode label
l  w (mm)
100  75
35  75
14. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
PTN36241B
Product data sheet
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Rev. 4 — 22 May 2014
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NXP Semiconductors
SuperSpeed USB 3.0 redriver
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
14.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
14.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
14.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 18) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
PTN36241B
Product data sheet
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Rev. 4 — 22 May 2014
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PTN36241B
NXP Semiconductors
SuperSpeed USB 3.0 redriver
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 21 and 22
Table 21.
SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
 350
< 2.5
235
220
 2.5
220
220
Table 22.
Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 18.
temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 18. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
PTN36241B
Product data sheet
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Rev. 4 — 22 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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NXP Semiconductors
SuperSpeed USB 3.0 redriver
15. Soldering: PCB footprints
)RRWSULQWLQIRUPDWLRQIRUUHIORZVROGHULQJRI+94)1SDFNDJH
627
+[
*[
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63[
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63\
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6/\
Q63\
%\
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63[WRW
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*HQHULFIRRWSULQWSDWWHUQ
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VROGHUODQG
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+[
+\
,VVXHGDWH
VRWBIU
Fig 19. PCB footprint for SOT616-3 (HVQFN24); reflow soldering
PTN36241B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 22 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
27 of 31
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NXP Semiconductors
SuperSpeed USB 3.0 redriver
16. Abbreviations
Table 23.
Abbreviations
Acronym
Description
AIO
All In One
CDM
Charged-Device Model
CMOS
Complementary Metal-Oxide Semiconductor
ESD
ElectroStatic Discharge
HBM
Human Body Model
I2C-bus
Inter-Integrated Circuit bus
I/O
Input/Output
IC
Integrated Circuit
ISI
InterSymbol Interference
LFPS
Low Frequency Periodic Signaling
PCB
Printed-Circuit Board
SI
Signal Integrity
USB
Universal Serial Bus
17. Revision history
Table 24.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PTN36241B v.4
20140522
Product data sheet
-
PTN36241B v.3
Modifications:
•
•
•
•
Table 1 “Ordering information”: added column “Topside marking”
Added Section 5.1 “Ordering options”
Added Section 13 “Packing information”
Added Section 15 “Soldering: PCB footprints”
PTN36241B v.3
20130212
Product data sheet
-
PTN36241B v.2
PTN36241B v.2
20120725
Product data sheet
-
PTN36241B v.1
PTN36241B v.1
20120404
Product data sheet
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PTN36241B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 22 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
28 of 31
PTN36241B
NXP Semiconductors
SuperSpeed USB 3.0 redriver
18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
18.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PTN36241B
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 22 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
29 of 31
PTN36241B
NXP Semiconductors
SuperSpeed USB 3.0 redriver
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
PTN36241B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 22 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
30 of 31
PTN36241B
NXP Semiconductors
SuperSpeed USB 3.0 redriver
20. Contents
1
2
2.1
2.2
3
4
5
5.1
6
7
7.1
7.2
8
8.1
8.2
8.3
8.4
8.4.1
8.5
8.6
9
10
11
11.1
11.2
11.3
11.4
11.5
12
13
13.1
13.2
13.3
13.4
13.5
14
14.1
14.2
14.3
14.4
15
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
High-speed channel processing . . . . . . . . . . . . 1
Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . 2
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
System context diagrams . . . . . . . . . . . . . . . . . 3
Ordering information . . . . . . . . . . . . . . . . . . . . . 4
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pinning information . . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functional description . . . . . . . . . . . . . . . . . . . 7
Receive equalization . . . . . . . . . . . . . . . . . . . . 7
Transmit de-emphasis and output swing . . . . . 7
Input signal threshold . . . . . . . . . . . . . . . . . . . . 8
I2C-bus programmability . . . . . . . . . . . . . . . . . . 9
I2C-bus read and write operations . . . . . . . . . 11
Device control — mode, enable, power-on
initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Device states and power management . . . . . 14
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 15
Recommended operating conditions. . . . . . . 15
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 16
Device characteristics. . . . . . . . . . . . . . . . . . . 16
Receiver AC/DC characteristics . . . . . . . . . . . 17
Transmitter AC/DC characteristics . . . . . . . . . 18
Jitter performance. . . . . . . . . . . . . . . . . . . . . . 19
Control inputs . . . . . . . . . . . . . . . . . . . . . . . . . 19
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 20
Packing information . . . . . . . . . . . . . . . . . . . . 21
Packing method . . . . . . . . . . . . . . . . . . . . . . . 21
Product orientation . . . . . . . . . . . . . . . . . . . . . 22
Carrier tape dimensions . . . . . . . . . . . . . . . . . 22
Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . 23
Barcode label . . . . . . . . . . . . . . . . . . . . . . . . . 24
Soldering of SMD packages . . . . . . . . . . . . . . 24
Introduction to soldering . . . . . . . . . . . . . . . . . 24
Wave and reflow soldering . . . . . . . . . . . . . . . 25
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 25
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 25
Soldering: PCB footprints. . . . . . . . . . . . . . . . 27
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 28
18
18.1
18.2
18.3
18.4
19
20
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29
29
29
29
30
30
31
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2014.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 22 May 2014
Document identifier: PTN36241B