Download Datasheet

STA333IS
Sound Terminal®
2-channel high-efficiency digital audio system
Datasheet - production data
Applications
• LCDs
CSP 5x6 array
• DVDs
• Cradles
• Digital speakers
• Wireless-speaker cradles
Features
• Wide-range supply voltage (4.5 V - 20 V)
• 2 channels of ternary PWM (stereo mode)
• 2 channels of 24-bit FFX™
• 100 dB SNR and dynamic range
• Selectable 32- to 192-kHz input sampling rates
• Digital gain -80 dB to +48 dB in 0.5 dB steps
• Software volume update
• Individual channel and master gain/attenuation
• Individual channel and master software and
hardware mute
• Independent channel volume bypass
• Automatic zero-detect mute
• Automatic invalid input detect mute
• Short-circuit detection at startup (Out-Vcc, OutGnd, Out 1b-Out 2a)
• 2-channel I2S input data interface
Description
The STA333IS is an integrated circuit comprising
digital audio processing, digital amplifier control
and an FFX™ power output stage to create a
high-power, single-chip FFX solution for all-digital
amplification with high quality and high efficiency.
The STA333IS power section consists of four
independent half-bridge stages. Two channels
can be provided by two full bridges, delivering up
to 10 W + 10 W of power.
Also featured in the STA333IS are new advanced
modes for reducing AM radio interference. The
serial audio data input interface accepts all
possible formats, including the popular I2S format.
Two channels of FFX™ processing are provided.
The STA333IS is part of the Sound Terminal®
family that provides full digital audio streaming to
the speaker, offering cost effectiveness, lowpower dissipation and sound enrichment.
• 2 Hz DC cut filter (input)
Table 1. Device summary
• Input channel mapping
• Automatic volume control for limiting maximum
power
• 96 kHz internal processing sampling rate,
24-bit precision
Order code
STA333IS
Package
CSP 5x6 array
Packaging
Tape and reel
• Advanced modes for AM interference
frequency switching and noise suppression
• Embedded thermal-overload and short-circuit
protection
• Video application: 576 * fS input mode support
April 2013
This is information on a product in full production.
DocID022855 Rev 3
1/43
www.st.com
43
Contents
STA333IS
Contents
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
2.1
Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2
Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.3
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.4
Electrical specifications - digital section . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.5
Electrical specifications - power section . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.6
Power-off sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.7
Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.8
Serial audio interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.8.1
4
I2C bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1
Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1.1
Data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1.2
Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1.3
Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1.4
Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.2
Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3
Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.4
2/43
Serial audio interface protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3.1
Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3.2
Multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.4.1
Current address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.4.2
Current address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.4.3
Random address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.4.4
Random address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
DocID022855 Rev 3
STA333IS
5
Contents
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1
5.2
Configuration registers (addr 0x00 to 0x05) . . . . . . . . . . . . . . . . . . . . . . . 20
5.1.1
Configuration register A (addr 0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1.2
Configuration register B (addr 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1.3
Configuration register C (addr 0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1.4
Configuration register D (addr 0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.1.5
Configuration register E (addr 0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.1.6
Configuration register F (addr 0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Volume control registers (addr 0x06 to 0x09) . . . . . . . . . . . . . . . . . . . . . . 30
5.2.1
Mute/line output configuration register (addr 0x06) . . . . . . . . . . . . . . . . 30
5.2.2
Master volume register (addr 0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.2.3
Channel volume (addr 0x08, 0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.3
Automodes™ register (0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.4
Channel configuration registers (addr 0x0E, 0x0F) . . . . . . . . . . . . . . . . . 33
5.5
Variable max power correction registers (addr 0x27, 0x28) . . . . . . . . . . . 33
5.6
Variable distortion compensation registers (addr 0x29, 0x2A) . . . . . . . . . 33
5.7
Fault-detect recovery constant registers (addr 0x2B, 0x2C) . . . . . . . . . . 34
5.8
Device status register (addr 0x2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.9
Reserved registers (addr 0x2E, 0x2F, 0x30, 0x31) . . . . . . . . . . . . . . . . . 35
5.10
Postscale registers (addr 0x32, 0x33) . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.11
Output limit register (addr 0x34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.11.1
5.12
6
Thermal and overcurrent warning output limit register . . . . . . . . . . . . . 35
Short-circuit protection registers SHOKx (addr 0x35, 0x37, 0x38) . . . . . . 37
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.1
Application scheme for power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
DocID022855 Rev 3
3/43
List of tables
STA333IS
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
4/43
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Electrical characteristics for digital section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Electrical specifications for power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
MCS bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Interpolation ratio select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
IR bit settings as a function of input sampling rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Thermal warning recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Thermal warning adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Fault-detect recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Serial audio input interface format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Serial data first bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Support serial audio input formats for MSB-first (SAIFB = 0) . . . . . . . . . . . . . . . . . . . . . . . 23
Supported serial audio input formats for LSB-first (SAIFB = 1) . . . . . . . . . . . . . . . . . . . . . 24
Channel input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
FFX power output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
FFX compensating pulse size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Overcurrent warning detect adjustment bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Zero-detect mute enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Max power correction variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Noise-shaper bandwidth selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
AM mode enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PWM speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Distortion compensation variable enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Zero-crossing volume enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Zero-crossing volume enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Invalid input detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Binary output mode clock loss detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
LRCK double trigger protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Auto EAPD on clock loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
External amplifier power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Master mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Channel mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Master volume offset as a function of MV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Channel volume as a function of CxV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
AM interference frequency switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Automodes™ AM switching frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Status bits description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Output limit values for thermal and overcurrent warnings. . . . . . . . . . . . . . . . . . . . . . . . . . 36
Recommended soldering reflow values for mounting on PCB . . . . . . . . . . . . . . . . . . . . . . 39
CSP 5x6 array package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
DocID022855 Rev 3
STA333IS
Table 49.
List of tables
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
DocID022855 Rev 3
5/43
List of figures
STA333IS
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
6/43
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin connections (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power-off sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Current deadtime test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
I2S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Left-justified . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write-mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Read-mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Short-circuit protection timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Recommended soldering reflow profile for mounting on PCB . . . . . . . . . . . . . . . . . . . . . . 39
CSP 5x6 array outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
DocID022855 Rev 3
STA333IS
1
Block diagram
Block diagram
Figure 1. Block diagram
I2 C
Protection
current/thermal
2
I S
interface
Volume
control
Channel
1A
Power
control
Logic
Channel
1B
FFX
Channel
2A
Regulators
Channel
2B
PLL
Bias
Digital DSP
Power
DocID022855 Rev 3
7/43
Pin description
STA333IS
2
Pin description
2.1
Pinout
Figure 2. Pin connections (package top view)
1
A
8/43
2
3
4
5
GND 1
OUT1
NC
VD D R E G
SDI
B
GND 1
VCC1
NC
LRCKI
VD D _ D IG
C
OUT1 B
VCC1
G ND REG
BICK I
G ND _ D IG
D
OUT2 A
VCC2
VCCREG
SD A
X TI
E
GND 2
VCC2
NC
SCL
VD D _ P L L
F
GND 2
OUT2 B
NC
VSS
GND _ P L L
DocID022855 Rev 3
STA333IS
2.2
Pin description
Pin list
Table 2. Pin description
Pin
number
Name
Description
Pad information
I/O pins
B4
LRCKI
I2S Left/Right clock
C4
BICKI
I2S serial clock
A5
SDI
I2S serial data channels 1 & 2
D5
XTI
Master clock input
E4
SCL
I2C serial clock
D4
SDA
I2C serial data
Power output pins
A2
OUT1A
Positive output 1
C1
OUT1B
Negative output 1
D1
OUT2A
Positive output 2
F2
OUT2B
Negative output 2
Power supplies (preliminary)
B2/C2
VCC1
Positive supply (upper MOSFET) to left H-bridge P output
E2/D2
VCC2
Positive supply (upper MOSFET) to right H-bridge P output
A1/B1
GND1
Negative supply (lower MOSFET) to left H-bridge P output
E1/F1
GND2
Negative supply (lower MOSFET) to right H-bridge P output
D3
VCCREG Reference voltage to Vcc
C3
GNDREG Reference voltage to ground
A4
VDDREG Reference voltage to 3.3 V
F4
VSS
Reference voltage to Vcc - 3.3 V
B5
VDD_DIG Digital supply
C5
GND_DIG Digital ground
E5
VDD_PLL PLL supply
F5
GND_PLL PLL ground
A3, B3,
E3, F3
NC
These pins are output pins
that must be externally
filtered. Do not connect
these pins to external supply
voltage.
Not connected
DocID022855 Rev 3
9/43
Electrical specifications
STA333IS
3
Electrical specifications
3.1
Absolute maximum ratings
Table 3. Absolute maximum ratings
Symbol
Parameter
Typ
Max
Unit
VCC
Analog supply voltage (pins VCCx)
-0.3
-
22
V
VDD
Digital supply voltage (pins VDD_DIG)
-0.3
-
4.0
V
IL
Logic input interface
-0.3
-
4.0
V
Top
Operating junction temperature
0
-
150
°C
Tstg
Storage temperature
-40
-
150
°C
Warning:
3.2
Min
Stresses beyond those listed in Table 3: Absolute maximum
ratings may cause permanent damage to the device. These
are stress ratings only, and functional operation of the device
at these or any other conditions beyond those indicated in
Table 5: Recommended operating conditions are not implied.
Exposure to absolute maximum rated conditions for
extended periods may affect device reliability. In the real
application, a power supply with nominal value rated within
the limits of the recommended operating conditions may rise
beyond the maximum operating conditions for a short time
when no or very low current is sunk (amplifier in mute state).
In this case the reliability of the device is guaranteed,
provided that the absolute maximum ratings are not
exceeded.
Thermal data
Table 4. Thermal data
Symbol
Parameter
Min
Max
Unit
RTh(j-a)
Thermal resistance junction-to-ambient(1)
-
45
-
°C/W
Tsd
Thermal shutdown junction temperature
140
150
160
°C
Tw
Thermal warning temperature
-
130
-
°C
Thsd
Thermal shutdown hysteresis
18
20
22
°C
1. Measurements performed on ST 2-layer reference board (1 oz. PCB, 3.8
dissipation area)
10/43
Typ
DocID022855 Rev 3
cm2
exposed copper
STA333IS
3.3
Electrical specifications
Recommended operating conditions
Table 5. Recommended operating conditions
Symbol
3.4
Parameter
Min
Typ
Max
Unit
VCC
Analog supply voltage (VCCx)
4.5
-
20
V
VDD
Digital supply voltage (VDD_DIG)
3.0
3.3
3.6
V
IL
Logic input interface
3.0
3.3
3.6
V
Tamb
Ambient temperature
0
-
70
°C
Max
Unit
Electrical specifications - digital section
Table 6. Electrical characteristics for digital section
Symbol
Iil
Parameter
Conditions
Min
Typ
Input current, no pull-up or
pull-down resistor
Vi = 0 V
-
-
±10
µA
Vi = VDD = 3.6 V
-
-
±10
µA
Vil
Low-level input voltage
-
-
-
0.2 *
VDD
V
Vih
High-level input voltage
-
0.8 *
VDD
-
-
V
Vol
Low-level output voltage
Iol = 2 mA
-
-
0.3V
V
Voh
High-level output voltage
Ioh = 2 mA
VDD –
-
-
V
Ipu
Pull-up current
-
25
66
125
µA
Rpu
Equivalent pull-up
resistance
-
-
50
-
kΩ
Iih
DocID022855 Rev 3
0.3V
11/43
Electrical specifications
3.5
STA333IS
Electrical specifications - power section
The specifications in Table 7 below are given for the conditions VCC = 13 V, VDD = 3.3 V,
fSW = 384 kHz, Tamb = 25 °C and RL = 8 Ω, unless otherwise specified.
Table 7. Electrical specifications for power section
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
THD = 1%
-
8
-
THD = 10%
-
10
-
ld = 1 A
-
110
-
mΩ
-
-
10
µA
Po
Output power BTL
RdsON
Power P-channel/N-channel
MOSFET (total bridge)
ldss
Power P-channel/N-channel leakage VCC = 20 V
gP
Power P-channel RdsON matching
ld = 1 A
95
-
-
%
gN
Power N-channel RdsON matching
ld = 1 A
95
-
-
%
ILDT
Low-current dead time (static)
Resistive load, refer to Figure 4
-
5
10
ns
IHDT
High-current dead time (dynamic)
Refer to Figure 5
-
10
20
ns
tr
Rise time
Resistive load, refer to Figure 4
-
8
10
ns
tf
Fall time
Resistive load, refer to Figure 4
-
8
10
ns
VCC
Supply voltage
-
4.5
-
20
V
Supply current from VCC in powerdown
At power-ON (EAPD bit = 0)
30
60
200
µA
-
30
50
mA
-
30
50
mA
-
11
25
mA
2.2
3.5
4.3
A
2.7
3.8
5.0
A
-
3.5
4.3
V
20
30
60
ns
IVCC
Supply current from VCC in
operation
Supply current for FFX processing
IVDD_DIG (reference only)
Supply current in standby
ILIM
Overcurrent limit
PCM input signal = -60 dBfs
Internal clock = 49.152 MHz
Switching frequency = 384 kHz
No LC filters
(PWDN bit = 0)
Non-linear output
(1)
(2)
W
ISCP
Short-circuit protection
High-impedance output
VUVP
Undervoltage protection threshold
-
tmin
Output minimum pulse width
No load
THD+N
Total harmonic distortion and noise
FFX stereo mode, Po = 1 W, f = 1 kHz
-
0.05
-
%
DR
Dynamic range
-
-
100
-
dB
Signal to noise ratio in ternary mode A-weighted
-
100
-
Signal to noise ratio in binary mode
A-weighted
-
90
-
Power supply rejection ratio
FFX stereo mode, < 5 kHz,
VRIPPLE = 1 V RMS
audio input = dither only
-
80
-
SNR
PSRR
12/43
DocID022855 Rev 3
dB
dB
STA333IS
Electrical specifications
Table 7. Electrical specifications for power section (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
XTALK
Crosstalk
FFX stereo mode, < 5 kHz,
One channel driven at 1 W
the other channel measured
-
80
-
dB
η
Peak efficiency in FFX mode
Po = 2 x 10 W into 8 Ω
-
90
-
%
1. The ILIM data is for 1 channel of BTL configuration, thus, 2 * ILIM drives the 2-channel BTL configuration. The
current limit is active when OCRB = 0 (see Table 23: Overcurrent warning detect adjustment bypass on
page 26. When OCRB = 1, then ISC applies.
2. The ISCP current limit data is for 1 channel of BTL configuration, thus, 2 * ISCP drives the 2-channel BTL
configuration. The short-circuit current is applicable when OCRB = 1 (see Table 23: Overcurrent warning
detect adjustment bypass on page 26.
DocID022855 Rev 3
13/43
Electrical specifications
3.6
STA333IS
Power-off sequence
The power-off sequence shown in Figure 3 below ensures a pop-free turn-off.
Figure 3. Power-off sequence
No specific VCC and VDD_DIG turn-off sequence is required
VCC
Don’t care
VDD_DIG
XTI
Don’t care
Mute
Register 0x07
FE
Don’t care
Don’t care
Bit EAPD
Register 0x05
3.7
Testing
Figure 4. Test circuit
OUTxY
Vcc
(3/4)Vcc
Low current dead time = MAX(DTr,DTf)
(1/2)Vcc
(1/4)Vcc
+Vcc
t
DTr
Duty cycle = 50%
DTf
M58
OUTxY
INxY
R 8Ω
M57
+
-
gnd
V67 =
vdc = Vcc/2
D03AU1458
Figure 5. Current deadtime test circuit
High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B))
+VCC
Duty cycle=A
Duty cycle=B
DTout(A)
M58
DTin(A)
Q2
Q1
Rload=8Ω
OUTA
INA
L67 22μ
Q3
C69
470nF
DTin(B)
OUTB
INB
Iout=4A
Lout
= 1.5 A
C71 470nF
C70
470nF
Q4
Duty cycle A and B: Fixed to have DC output current of 4A in the direction shown in figure
14/43
M64
L68 22μ
Iout=4A
Lout
= 1.5 A
M57
DTout(B)
DocID022855 Rev 3
M63
D03AU1517
STA333IS
Electrical specifications
3.8
Serial audio interface description
3.8.1
Serial audio interface protocols
The STA333IS serial audio input was designed to interface with standard digital audio
components and to accept serial data formats. The STA333IS always acts as a slave when
receiving audio input from standard digital audio components. Serial data for two channels
is provided using 3 input pins: left/right clock LRCKI (pin B4), serial clock BICKI (pin C4),
and serial data SDI (pin A5).
The available formats are shown in Figure 6 and Figure 7, and set through Configuration
register B (addr 0x01) on page 22.
Figure 6. I2S
LRCKI
BICKI
SDI
1
2
3
1
n-1 n
2
3
n-1 n
Figure 7. Left-justified
LRCKI
BICKI
SDI
1
2
3
n-1 n
1
2
3
DocID022855 Rev 3
n-1 n
15/43
I2C bus specification
4
STA333IS
I2C bus specification
The STA333IS supports the I2C protocol via the input ports SCL and SDA. This protocol
defines any device that sends data to the bus as a transmitter and any device that reads the
data as a receiver. The device that controls the data transfer is known as the master and the
other as the slave. The master always starts the transfer and provides the serial clock for
synchronization. The STA333IS is always a slave device in all of its communications. It
supports up to 400 kb/s (fast-mode bit rate).
4.1
Communication protocol
4.1.1
Data transition or change
Data changes on the SDA line must only occur when the SCL clock is low. An SDA
transition while the clock is high is used to identify a START or STOP condition.
4.1.2
Start condition
START is identified by a high-to-low transition of the data bus SDA signal while the clock
signal SCL is stable in the high state. A START condition must precede any command for
data transfer.
4.1.3
Stop condition
STOP is identified by a low-to-high transition of the data bus SDA signal while the clock
signal SCL is stable in the high state. A STOP condition terminates communication between
the STA333IS and the bus master.
4.1.4
Data input
During data input the STA333IS samples the SDA signal on the rising edge of clock SCL.
For correct device operation the SDA signal must be stable during the rising edge of the
clock and the data can change only when the SCL line is low.
4.2
Device addressing
To start communication between the master and the STA333IS, the master must initiate a
start condition. Following this, the master sends to the SDA line 8 bits (MSB first)
corresponding to the device select address and read or write mode.
The 7 most significant bits are the device address identifiers, corresponding to the I2C bus
definition. In the STA333IS the I2C interface has device address 0x38.
The 8th bit (LSB) identifies the read or write operation RW, this bit is set to 1 for read mode
and 0 for write mode. After a START condition the STA333IS identifies the device address
on the SDA bus and if a match is found, acknowledges the identification during the 9th bit
time. The byte following the device identification byte is the internal space address.
16/43
DocID022855 Rev 3
I2C bus specification
STA333IS
4.3
Write operation
Following the START condition the master sends a device select code with the RW bit set
to 0. The STA333IS acknowledges this and then waits for the byte of internal address. After
receiving the internal byte address, the STA333IS again responds with an
acknowledgement.
4.3.1
Byte write
In the byte write mode the master sends one data byte which is acknowledged by the
STA333IS. The master then terminates the transfer by generating a STOP condition.
4.3.2
Multi-byte write
The multi-byte write modes can start from any internal address. The master generating a
STOP condition terminates the transfer.
Figure 8. Write-mode sequence
ACK
BYTE
WRITE
ACK
DEV-ADDR
START
SUB-ADDR
RW
STOP
ACK
MULTIBYTE
WRITE
ACK
DATA IN
ACK
DEV-ADDR
START
SUB-ADDR
RW
ACK
DATA IN
ACK
DATA IN
STOP
4.4
Read operation
4.4.1
Current address byte read
Following the START condition the master sends a device select code with the RW bit set
to 1. The STA333IS acknowledges this and then responds by sending one byte of data. The
master then terminates the transfer by generating a STOP condition.
4.4.2
Current address multi-byte read
The multi-byte read modes can start from any internal address. Sequential data bytes are
read from sequential addresses within the STA333IS. The master acknowledges each data
byte read and then generates a STOP condition, terminating the transfer.
4.4.3
Random address byte read
Following the START condition the master sends a device select code with the RW bit set
to 0. The STA333IS acknowledges this and then the master writes the internal address byte.
After receiving the internal byte address, the STA333IS again responds with an
acknowledgement. The master then initiates another START condition and sends the device
select code with the RW bit set to 1. The STA333IS acknowledges this and then responds
by sending one byte of data. The master then terminates the transfer by generating a STOP
condition.
DocID022855 Rev 3
17/43
I2C bus specification
4.4.4
STA333IS
Random address multi-byte read
The multi-byte read modes can start from any internal address. Sequential data bytes are
read from sequential addresses within the STA333IS. The master acknowledges each data
byte read and then generates a STOP condition to terminate the transfer.
Figure 9. Read-mode sequence
ACK
CURRENT
ADDRESS
READ
DEV-ADDR
NO ACK
DATA
RW
START
STOP
ACK
RANDOM
ADDRESS
READ
DEV-ADDR
DEV-ADDR
NO ACK
ACK
SUB-ADDR
DATA
DEV-ADDR
S T AR T
RW
RW= ACK
HIGH
START
SEQUENTIAL
CURRENT
READ
ACK
RW
ACK
STOP
NO ACK
ACK
DATA
DATA
DATA
STOP
START
ACK
SEQUENTIAL
RANDOM
READ
DEV-ADDR
START
18/43
ACK
ACK
SUB-ADDR
RW
DEV-ADDR
S T AR T
ACK
DATA
RW
DocID022855 Rev 3
ACK
DATA
NO ACK
DATA
STOP
STA333IS
5
Register description
Register description
Table 8. Register summary
Addr
Name
D7
D6
D5
D4
D3
D2
D1
D0
0x00
CONFA
FDRB
TWAB
TWRB
IR1
IR0
MCS2
MCS1
MCS0
0x01
CONFB
C2IM
C1IM
Reserved
SAIFB
SAI3
SAI2
SAI1
SAI0
0x02
CONFC
OCRB
Reserved
CSZ3
CSZ2
CSZ1
CSZ0
OM1
OM0
0x03
CONFD
Reserved
ZDE
0x04
CONFE
SVE
ZCE
DCCV
PWMS
AME
NSBW
MPC
MPCV
0x05
CONFF
EAPD
PWDN
ECLE
LDTE
BCLE
IDE
0x06
MUTE
0x07
MVOL
MV7
MV6
MV5
MV4
0x08
C1VOL
C1V7
C1V6
C1V5
0x09
C2VOL
C2V7
C2V6
C2V5
0x0C
AUTO
0x0E
C1CFG
Reserved
C1VBP
Reserved
0x0F
C2CFG
Reserved
C2VBP
Reserved
0x27
MPCC1
MPCC15
MPCC14
MPCC13
MPCC12
MPCC11
MPCC10
MPCC9
MPCC8
0x28
MPCC2
MPCC7
MPCC6
MPCC5
MPCC4
MPCC3
MPCC2
MPCC1
MPCC0
0x29
DCC1
DCC15
DCC14
DCC13
DCC12
DCC11
DCC10
DCC9
DCC8
0x2A
DCC2
DCC7
DCC6
DCC5
DCC4
DCC3
DCC2
DCC1
DCC0
0x2B
FDRC1
FDRC15
FDRC14
FDRC13
FDRC12
FDRC11
FDRC10
FDRC9
FDRC8
0x2C
FDRC2
FDRC7
FDRC6
FDRC5
FDRC4
FDRC3
FDRC2
FDRC1
FDRC0
0x2D
STATUS
PLLUL
FAULT
UVFAULT
OVFAULT
OCFAULT
OCWARN
TFAULT
TWARN
0x2E
BIST1
Reserved
RO1BACT
R5BACT
R1BACT
0x2F
BIST2
Reserved
R01BEND
R5BEND
R1BEND
0x30
BIST3
R5BBAD
R1BBAD
0x31
TSTCTL
0x32
C1PS
C1PS7
C1PS6
C1PS5
C1PS4
C1PS3
C1PS2
C1PS1
C1PS0
0x33
C2PS
C2PS7
C2PS6
C2PS5
C2PS4
C2PS3
C2PS2
C2PS1
C2PS0
0x34
OLIM
OLIM7
OLIM6
OLIM5
OLIM4
OLIM3
OLIM2
OLIM1
OLIM0
0x35
SHEN
ENABLE_SH
Reserved
0x36
Reserved
0x37
SHORT
SHGND1A
SHGND1B
SHGND2A
SHGND2B
SHVCC1A
SHVCC1B
SHVCC2A
SHVCC2B
0x38
SHOUT
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SHOUT
Reserved
Reserved
C2M
C1M
MMUTE
MV3
MV2
MV1
MV0
C1V4
C1V3
C1V2
C1V1
C1V0
C2V4
C2V3
C2V2
C2V1
C2V0
AMAM2
AMAM1
AMAM0
AMAME
Reserved
Reserved
Reserved
Reserved
Reserved
DocID022855 Rev 3
19/43
Register description
STA333IS
5.1
Configuration registers (addr 0x00 to 0x05)
5.1.1
Configuration register A (addr 0x00)
D7
D6
D5
D4
D3
D2
D1
D0
FDRB
TWAB
TWRB
IR1
IR0
MCS2
MCS1
MCS0
0
1
1
0
0
0
1
1
Master clock select
Table 9. Master clock select
Bit
R/W
RST
Name
0
R/W
1
MCS0
1
R/W
1
MCS1
2
R/W
0
MCS2
Description
Master clock select: Selects the ratio between the
input I2S sampling frequency and the input clock.
The STA333IS supports sampling rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz,
176.4 kHz, and 192 kHz. Therefore the internal clock is:
•
32.768 MHz for 32 kHz
•
45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz
•
49.152 MHz for 48 kHz, 96 kHz, and 192 kHz
The external clock frequency provided to the XTI pin must be a multiple of the input
sampling frequency (fS).
The relationship between the input clock and the input sampling rate is determined by both
the MCSx and the IR (input rate) register bits. The MCSx bits determine the PLL factor
generating the internal clock and the IR bit determines the oversampling ratio used
internally.
Table 10. MCS bits
Input sampling rate
fS (kHz)
20/43
MCS[2:0]
IR
101
100
011
010
001
000
32, 44.1, 48
00
576 * fS
128 * fS
256 * fS
384 * fS 512 * fS 768 * fS
88.2, 96
01
NA
64 * fS
128 * fS
192 * fS 256 * fS 384 * fS
176.4, 192
1X
NA
32 * fS
64 * fS
96 * fS
DocID022855 Rev 3
128 * fS 192 * fS
STA333IS
Register description
Interpolation ratio select
Table 11. Interpolation ratio select
Bit
4:3
R/W
R/W
RST
00
Name
IR [1:0]
Description
Interpolation ratio select: Selects internal
interpolation ratio based on input I2S sampling
frequency.
The STA333IS has variable interpolation (oversampling) settings such that internal
processing and FFX output rates remain consistent. The first processing block interpolates
by either 2 times or 1 time (pass-through) or provides a 2-time downsampling. The
oversampling ratio of this interpolation is determined by the IR bits.
Table 12. IR bit settings as a function of input sampling rate
Input sampling rate fS (kHz)
IR
1st stage interpolation ratio
32
00
2-time oversampling
44.1
00
2-time oversampling
48
00
2-time oversampling
88.2
01
Pass-through
96
01
Pass-through
176.2
10
2-time downsampling
192
10
2-time downsampling
Thermal warning recovery bypass
Table 13. Thermal warning recovery
Bit
5
R/W
R/W
RST
1
Name
TWRB
Description
Thermal warning recovery bypass:
0: thermal warning recovery enabled
1: thermal warning recovery disabled
If the thermal warning adjustment is enabled (TWAB = 0), then the thermal warning recovery
determines if the -3 dB output limit is removed when thermal warning is negative.
If TWRB = 0 and TWAB = 0, then when a thermal warning disappears, the -3 dB output limit
is removed and the gain is added back to the system. If TWRB = 1 and TWAB = 0, then
when a thermal warning disappears, the -3 dB output limit remains until TWRB is changed
to zero or the device is reset.
DocID022855 Rev 3
21/43
Register description
STA333IS
Thermal warning adjustment bypass
Table 14. Thermal warning adjustment
Bit
6
R/W
RST
R/W
1
Name
Description
Thermal warning adjustment bypass:
0: thermal warning adjustment enabled
1: thermal warning adjustment disabled
TWAB
The on-chip STA333IS power output block provides feedback to the digital controller using
inputs to the power control block. The TWARN input is used to indicate a thermal warning
condition. When TWARN is asserted (set to 0) for a period of time greater than 400 ms, the
power control block will force a -3 dB output limit (determined by TWOCL in coefficient
RAM) to the modulation limit in an attempt to eliminate the thermal warning condition. Once
the thermal warning output limit adjustment is applied, it remains in this state until reset
unless FDRB = 0.
Fault-detect recovery bypass
Table 15. Fault-detect recovery
Bit
7
R/W
RST
R/W
0
Name
Description
Fault-detect recovery bypass:
0: fault-detect recovery enabled
1: fault-detect recovery disabled
FDRB
The on-chip STA333IS power output block provides feedback to the digital controller using
inputs to the power control block. The FAULT input is used to indicate a fault condition
(either overcurrent or thermal). When FAULT is asserted (set to 0), the power control block
attempts a recovery from the fault by asserting the 3-state output (setting it to 0 which
directs the power output block to begin recovery), holding it at 0 for period of time in the
range of 0.1 ms to 1 second as defined by the fault-detect recovery constant register (FDRC
registers 0x2B, 0x2C), then toggling it back to 1. This sequence is repeated as long as the
fault indication exists. This feature is enabled by default but can be bypassed by setting the
FDRB control bit to 1.
5.1.2
22/43
Configuration register B (addr 0x01)
D7
D6
D5
D4
D3
D2
D1
D0
C2IM
C1IM
Reserved
SAIFB
SAI3
SAI2
SAI1
SAI0
1
0
0
0
0
0
0
0
DocID022855 Rev 3
STA333IS
Register description
Serial audio input interface format
Table 16. Serial audio input interface format
Bit
R/W
RST
Name
0
R/W
0
SAI0
1
R/W
0
SAI1
2
R/W
0
SAI2
3
R/W
0
SAI3
Description
Determines the interface format of the input serial
digital audio interface.
Serial data interface
The STA333IS audio serial input interfaces with standard digital audio components and
accepts a number of serial data formats. The STA333IS always acts as a slave when
receiving audio input from standard digital audio components. Serial data for two channels
is provided using three inputs: left/right clock LRCKI, serial clock BICKI, and serial data SDI.
Bits SAIx and bit SAIFB are used to specify the serial data format. The default serial data
format is I2S, MSB first. Available formats are shown in the tables that follow.
Serial data first bit
Table 17. Serial data first bit
SAIFB
Format
0
MSB-first
1
LSB-first
Table 18. Support serial audio input formats for MSB-first (SAIFB = 0)
BICKI
32 * fS
48* fS
64* fS
SAI [3:0]
SAIFB
Interface format
0000
0
I2S
0001
0
Left/right justified 16-bit data
0000
0
I2S 16- to 23-bit data
0001
0
Left-justified 16- to 24-bit data
0010
0
Right-justified 24-bit data
0110
0
Right-justified 20-bit data
1010
0
Right-justified 18-bit data
1110
0
Right-justified 16-bit data
0000
0
I2S 16- to 24-bit data
0001
0
Left-justified 16- to 24-bit data
0010
0
Right-justified 24-bit data
0110
0
Right-justified 20-bit data
1010
0
Right-justified 18-bit data
1110
0
Right-justified 16-bit data
DocID022855 Rev 3
15-bit data
23/43
Register description
STA333IS
Table 19. Supported serial audio input formats for LSB-first (SAIFB = 1)
BICKI
32* fS
48* fS
48* fS
64* fS
24/43
SAI[3:0]
SAIFB
Interface format
1100
1
I2S 15-bit data
1110
1
Left/right justified 16-bit data
0100
1
I2S 20-bit data
1000
1
I2S 18-bit data
1100
1
LSB-first I2S 16-bit data
0001
1
Left-justified 24-bit data
0101
1
Left-justified 20-bit data
1001
1
Left-justified 18-bit data
1101
1
Left-justified 16-bit data
0010
1
Right-justified 24-bit data
0110
1
Right-justified 20-bit data
1010
1
Right-justified 18-bit data
1110
1
Right-justified 16-bit data
0000
1
I2S 24-bit data
0100
1
I2S 20-bit data
1000
1
I2S 18-bit data
1100
1
LSB-first I2S 16-bit data
0001
1
Left-justified 24-bit data
0101
1
Left-justified 20-bit data
1001
1
Left-justified 18-bit data
1101
1
Left-justified 16-bit data
0010
1
Right-justified 24-bit data
0110
1
Right-justified 20-bit data
1010
1
Right-justified 18-bit data
1110
1
Right-justified 16-bit data
DocID022855 Rev 3
STA333IS
Register description
Channel input mapping
Table 20. Channel input mapping
Bit
R/W
RST
Name
Description
6
R/W
0
C1IM
0: processing channel 1 receives left I2S input
1: processing channel 1 receives right I2S input
7
R/W
0
C2IM
0: processing channel 2 receives left I2S input
1: processing channel 2 receives right I2S input
Each channel received via I2S can be mapped to any internal processing channel via the
channel input mapping registers. This allows for flexibility in processing. The default settings
of these registers map each I2S input channel to its corresponding processing channel.
5.1.3
Configuration register C (addr 0x02)
D7
D6
D5
D4
D3
D2
D1
D0
OCRB
Reserved
CSZ3
CSZ2
CSZ1
CSZ0
OM1
OM0
1
0
0
1
0
1
1
1
FFX power output mode
Table 21. FFX power output mode
Bit
R/W
RST
Name
0
R/W
1
OM0
1
R/W
1
OM1
Description
The FFX power output mode selects the configuration
of the FFX output:
00: drop compensation
01: discrete output stage: tapered compensation
10: full-power mode
11: variable drop compensation (CSZx bits)
FFX compensation pulse size register
Table 22. FFX compensating pulse size
Bit
R/W
RST
Name
2
R/W
1
CSZ0
3
R/W
0
CSZ1
4
R/W
1
CSZ2
5
R/W
0
CSZ3
Description
When OM[1:0] = 11, this register determines the size of
the FFX compensating pulse from 0 to 15 clock periods:
0000: 0 ns (0 ticks) compensating pulse size
0001: 20 ns (1 tick) clock period compensating pulse size
1111: 300 ns (15 ticks) clock period compensating pulse
size
DocID022855 Rev 3
25/43
Register description
STA333IS
Overcurrent warning detect adjustment bypass
Table 23. Overcurrent warning detect adjustment bypass
Bit
7
R/W
RST
R/W
1
Name
Description
0: overcurrent warning adjustment enabled
1: overcurrent warning adjustment disabled
OCRB
The status bit OCWARN is used to warn of an overcurrent condition. When OCWARN is
asserted (set to 0), the power control block forces an adjustment to the modulation limit
(default -3 dB) in an attempt to eliminate the overcurrent warning condition. Once the
overcurrent warning volume adjustment is applied, it remains applied until the device is
reset. The overcurrent limit can be changed via register OLIM (Output limit register (addr
0x34) on page 35).
5.1.4
Configuration register D (addr 0x03)
D7
D6
Reserved
ZDE
D5
0
1
D4
D3
D2
D1
D0
0
0
0
Reserved
0
0
0
Zero-detect mute enable
Table 24. Zero-detect mute enable
Bit
6
R/W
RST
R/W
1
Name
Description
ZDE
1: enable the automatic zero-detect mute
Setting the ZDE bit enables the zero-detect automatic mute. The zero-detect circuit looks at
the data for each processing channel at the output of the crossover (bass management)
filter. If any channel receives 2048 consecutive zero-value samples (regardless of fS) then
that individual channel is muted if this function is enabled.
5.1.5
Configuration register E (addr 0x04)
D7
D6
D5
D4
D3
D2
D1
D0
SVE
ZCE
DCCV
PWMS
AME
NSBW
MPC
MPCV
1
1
0
0
0
0
1
0
Max power correction variable
Table 25. Max power correction variable
Bit
0
26/43
R/W
R/W
RST
0
Name
MPCV
Description
0: use standard MPC coefficient
1: use MPCC bits for MPC coefficient
DocID022855 Rev 3
STA333IS
Register description
Max power correction
Table 26. Max power correction
Bit
1
R/W
R/W
RST
1
Name
Description
1: enable power bridge correction for THD reduction
near maximum power output.
MPC
Setting the MPC bit turns on special processing that corrects the STA333IS power device at
high power. This mode lowers the THD+N of a full FFX system at maximum power output
and slightly below. If enabled, MPC is operational in all output modes except tapered
(OM[1:0] = 01) and binary. When OCFG = 00, MPC does not affect channels 3 and 4, the
line-out channels.
Noise-shaper bandwidth selection
Table 27. Noise-shaper bandwidth selection
Bit
2
R/W
R/W
RST
0
Name
NSBW
Description
1: 3rd order NS
0: 4th order NS
AM mode enable
Table 28. AM mode enable
Bit
3
R/W
R/W
RST
0
Name
AME
Description
0: normal FFX operation
1: AM reduction mode FFX operation
The STA333IS features an FFX processing mode that minimizes the amount of noise
generated in the frequency range of AM radio. This mode is intended for use when FFX is
operating in a device with an active AM tuner. The SNR of the FFX processing is reduced to
approximately 83 dB in this mode, which is still greater than the SNR of AM radio.
PWM speed mode
Table 29. PWM speed mode
Bit
4
R/W
R/W
RST
0
Name
PWMS
Description
0: normal speed (384 kHz) all channels
1: odd speed (341.3 kHz) all channels
Distortion compensation variable enable
Table 30. Distortion compensation variable enable
Bit
5
R/W
R/W
RST
0
Name
DCCV
Description
0: uses preset DC coefficient
1: uses DCC coefficient
DocID022855 Rev 3
27/43
Register description
STA333IS
Zero-crossing volume enable
Table 31. Zero-crossing volume enable
Bit
R/W
6
R/W
RST
1
Name
Description
1: volume adjustments will only occur at digital zero-crossings
0: volume adjustments will occur immediately
ZCE
The ZCE bit enables zero-crossing volume adjustments. When the volume is adjusted on
digital zero-crossings, no clicks will be audible.
Soft volume update enable
Table 32. Zero-crossing volume enable
Bit
7
5.1.6
R/W
RST
R/W
1
Name
Description
1: volume adjustments ramp according to SVR settings
0: volume adjustments will occur immediately
SVE
Configuration register F (addr 0x05)
D7
D6
D5
D4
D3
D2
EAPD
PWDN
ECLE
LDTE
BCLE
IDE
0
1
0
1
1
1
D1
D0
Reserved
0
0
Invalid input detect mute enable
Table 33. Invalid input detect mute enable
Bit
2
R/W
R/W
RST
1
Name
IDE
Description
1: enables the automatic invalid input detect mute
Setting the IDE bit enables this function, which looks at the input I2S data and will
automatically mute if the signals are perceived as invalid.
Binary output mode clock loss detection
Table 34. Binary output mode clock loss detection
Bit
3
R/W
R/W
RST
1
Name
BCLE
Description
Binary output mode clock loss detection enable
The BCLE bit detects loss of input MCLK in binary mode and outputs 50% of the duty cycle.
28/43
DocID022855 Rev 3
STA333IS
Register description
LRCK double trigger protection
Table 35. LRCK double trigger protection
Bit
4
R/W
R/W
RST
1
Name
LDTE
Description
LRCLK double trigger protection enable
The LDTE bit actively prevents double triggering of LRCLK.
Auto EAPD on clock loss
Table 36. Auto EAPD on clock loss
Bit
5
R/W
R/W
RST
0
Name
ECLE
Description
Auto EAPD on clock loss
When active, the ECLE bit will issue a device power-down signal (EAPD) on clock loss
detection.
IC power-down
Table 37. Power-down
Bit
6
R/W
R/W
RST
1
Name
PWDN
Description
0: power-down, low-power condition
1: normal operation
The PWDN register is used to put the IC in a low-power state. When PWDN is 0, the output
begins a soft-mute. After the mute condition is reached, EAPD is asserted to power down
the power stage, then the master clock to all internal hardware except the I2C block is gated.
This puts the IC in a very low power consumption state.
External amplifier power down
Table 38. External amplifier power-down
Bit
7
R/W
R/W
RST
1
Name
EAPD
Description
0: external power stage power-down active
1: normal operation
The EAPD register directly disables/enables the internal power circuitry.
When EAPD = 0, the internal power section is placed in a low-power state (disabled).
DocID022855 Rev 3
29/43
Register description
STA333IS
5.2
Volume control registers (addr 0x06 to 0x09)
5.2.1
Mute/line output configuration register (addr 0x06)
D7
D6
D5
D4
D3
Reserved
0
0
0
0
0
D2
D1
D0
C2M
C1M
MMUTE
0
0
0
Master mute
Table 39. Master mute
Bit
0
R/W
R/W
RST
0
Name
MMUTE
Description
0: normal operation
1: all channels are in mute condition
Channel mute
Table 40. Channel mute
Bit
30/43
R/W
RST
Name
Description
1
R/W
0
C1M
Channel 1 mute:
0: not muted, it is possible to set the channel volume
1: hardware muted
2
R/W
0
C2M
Channel 2 mute:
0: not muted, it is possible to set the channel volume
1: hardware muted
DocID022855 Rev 3
STA333IS
5.2.2
5.2.3
Register description
Master volume register (addr 0x07)
D7
D6
D5
D4
D3
D2
D1
D0
MV7
MV6
MV5
MV4
MV3
MV2
MV1
MV0
1
1
1
1
1
1
1
1
Channel volume (addr 0x08, 0x09)
D7
D6
D5
D4
D3
D2
D1
D0
C1V7
C1V6
C1V5
C1V4
C1V3
C1V2
C1V1
C1V0
0
1
1
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
C2V7
C2V6
C2V5
C2V4
C2V3
C2V2
C2V1
C2V0
0
1
1
0
0
0
0
0
Volume setting
The volume structure of the STA333IS consists of individual volume registers for each
channel and a master volume register that provides an offset to each channel’s volume
setting. The individual channel volumes are adjustable in 0.5-dB steps from +48 dB to
-80 dB. As an example, if C3V = 0x00 or +48 dB and MV = 0x18 or -12 dB, then the total
gain for channel 3 = +36 dB.
The master mute, when set to 1, will mute all channels at once, whereas the individual
channel mutes (CxM) mute only that channel. Both the master mute and the channel mutes
provide a “soft mute” with the volume ramping down to mute in 4096 samples from the
maximum volume setting at the internal processing rate (about 96 kHz). A hard mute can be
obtained by commanding a value of all 1’s (255) to any channel volume register or the
master volume register. When volume offsets are provided via the master volume register,
any channel whose total volume is less than -80 dB is muted.
All changes in volume take place at zero-crossings when ZCE = 1 (configuration register F)
on a per-channel basis as this creates the smoothest possible volume transitions. When
ZCE = 0, volume updates will occur immediately.
Table 41. Master volume offset as a function of MV
MV[7:0]
Volume offset from channel value
00000000 (0x00)
0 dB
00000001 (0x01)
-0.5 dB
00000010 (0x02)
-1 dB
…
…
01001100 (0x4C)
-38 dB
…
…
11111110 (0xFE)
-127.5 dB
11111111 (0xFF)
Hard master mute
DocID022855 Rev 3
31/43
Register description
STA333IS
Table 42. Channel volume as a function of CxV
CxV[7:0]
5.3
Volume
00000000 (0x00)
+48 dB
00000001 (0x01)
+47.5 dB
00000010 (0x02)
+47 dB
…
…
01011111 (0x5F)
+0.5 dB
01100000 (0x60)
0 dB
01100001 (0x61)
-0.5 dB
…
…
11010111 (0xD7)
-59.5 dB
11011000 (0xD8)
-60 dB
11011001 (0xD9)
-61 dB
11011010 (0xDA)
-62 dB
…
…
11101100 (0xEC)
-80 dB
11101101 (0xED)
Hard channel mute
…
…
11111111 (0xFF)
Hard channel mute
Automodes™ register (0x0C)
D7
D6
D5
D4
Reserved
0
0
0
D3
D2
D1
D0
AMAM2
AMAM1
AMAM0
AMAME
0
0
0
0
0
AM interference frequency switching
Table 43. AM interference frequency switching
Bit
0
R/W
R/W
RST
0
Name
AMAME
Description
0: switching frequency determined by PWMS setting
1: switching frequency determined by AMAM setting
AMAM bits
Table 44. Automodes™ AM switching frequency selection
AMAM[2:0]
32/43
48 kHz / 96 kHz input fS
44.1 kHz / 88.2 kHz input fS
000
0.535 MHz - 0.720 MHz
0.535 MHz - 0.670 MHz
001
0.721 MHz - 0.900 MHz
0.671 MHz - 0.800 MHz
010
0.901 MHz - 1.100 MHz
0.801 MHz - 1.000 MHz
011
1.101 MHz - 1.300 MHz
1.001 MHz - 1.180 MHz
100
1.301 MHz - 1.480 MHz
1.181 MHz - 1.340 MHz
101
1.481 MHz - 1.600 MHz
1.341 MHz - 1.500 MHz
110
1.601 MHz - 1.700 MHz
1.501 MHz - 1.700 MHz
DocID022855 Rev 3
STA333IS
5.4
Register description
Channel configuration registers (addr 0x0E, 0x0F)
D7
D6
D5
D4
D3
Reserved
0
0
D7
D6
0
0
0
D5
D4
D3
Reserved
0
0
0
D2
D1
C1VBP
0
0
D2
D1
C2VBP
0
0
0
D0
Reserved
0
D0
Reserved
0
0
Volume bypass
Each channel contains an individual channel volume bypass. If a particular channel has
volume bypassed via the CxVBP = 1 register, then only the channel volume setting for that
particular channel affects the volume setting, the master volume setting will not affect that
channel.
5.5
Variable max power correction registers (addr 0x27, 0x28)
The MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This
coefficient is used in place of the default coefficient when MPCV = 1.
5.6
D7
D6
D5
D4
D3
D2
D1
D0
MPCC15
MPCC14
MPCC13
MPCC12
MPCC11
MPCC10
MPCC9
MPCC8
0
0
0
1
1
0
1
0
D7
D6
D5
D4
D3
D2
D1
D0
MPCC7
MPCC6
MPCC5
MPCC4
MPCC3
MPCC2
MPCC1
MPCC0
1
1
0
0
0
0
0
0
Variable distortion compensation registers (addr 0x29, 0x2A)
D7
D6
D5
D4
D3
D2
D1
D0
DCC15
DCC14
DCC13
DCC12
DCC11
DCC10
DCC9
DCC8
1
1
1
1
0
0
1
1
D7
D6
D5
D4
D3
D2
D1
D0
DCC7
DCC6
DCC5
DCC4
DCC3
DCC2
DCC1
DCC0
0
0
1
1
0
0
1
1
The DCC bits determine the 16 MSBs of the distortion compensation coefficient. This
coefficient is used in place of the default coefficient when DCCV = 1.
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33/43
Register description
5.7
STA333IS
Fault-detect recovery constant registers (addr 0x2B, 0x2C)
D7
D6
D5
D4
D3
D2
D1
D0
FDRC15
FDRC14
FDRC13
FDRC12
FDRC11
FDRC10
FDRC9
FDRC8
0
0
0
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
FDRC7
FDRC6
FDRC5
FDRC4
FDRC3
FDRC2
FDRC1
FDRC0
0
0
0
0
1
1
0
0
The FDRC bits specify the 16-bit fault-detect recovery time delay. When status register bit
FAULT is asserted, the tristate output is immediately asserted low and held low for the time
period specified by this constant. A value of 0x0001 in this register is approximately
0.083 ms. The default value of 0x000C gives approximately 0.1 ms.
Note:
0x0000 is a reserved value for this register pair. This value must not be used.
5.8
Device status register (addr 0x2D)
D7
D6
D5
D4
D3
D2
D1
D0
PLLUL
FAULT
UVFAULT
OVFAULT
OCFAULT
OCWARN
TFAULT
TWARN
This read-only register provides the fault, warning and PLL status from the power control
block.
Table 45. Status bits description
Bit
34/43
R/W
RST
Name
Description
0
RO
-
TWARN
Thermal warning:
0: junction temperature is close to the fault condition
1: normal operation
1
RO
-
TFAULT
Thermal fault:
0: junction temperature limit detection
1: normal operation
2
RO
-
OCWARN
Overcurrent warning:
0: warning
1: normal operation
3
RO
-
OCFAULT
Overcurrent fault:
0: fault detected
1: normal operation
4
-
-
-
Reserved
5
RO
-
UVFAULT
Undervoltage warning:
0: VCCx below lower voltage threshold
1: normal operation
6
RO
-
FAULT
Power bridge fault:
0: fault detected
1: normal operation
7
RO
-
PLLUL
PLL lock:
0: locked
1: not locked
DocID022855 Rev 3
STA333IS
5.9
Register description
Reserved registers (addr 0x2E, 0x2F, 0x30, 0x31)
These registers are not to be used.
5.10
Postscale registers (addr 0x32, 0x33)
D7
D6
D5
D4
D3
D2
D1
D0
C1PS7
C1PS6
C1PS5
C1PS4
C1PS3
C1PS2
C1PS1
C1PS0
0
1
1
1
1
1
1
1
D7
D6
D5
D4
D3
D2
D1
D0
C2PS7
C2PS6
C2PS5
C2PS4
C2PS3
C2PS2
C2PS1
C2PS0
0
1
1
1
1
1
1
1
Postscale
The STA333IS provides one additional multiplication after the last interpolation stage and
the distortion compensation on each channel, which can be used to limit the maximum
modulation index and therefore the peak current through the power device. The register
values represent an 8-bit signed fractional number. This number is extended to a 24-bit
number, by adding zeros to the right, and then directly multiplied by the data on that
channel. An independent postscale is provided for each channel but all channels can use
channel 1 postscale factor by setting the postscale link bit. By default, all postscale factors
are set to 0x7F (pass-through).
5.11
Output limit register (addr 0x34)
5.11.1
Thermal and overcurrent warning output limit register
D7
D6
D5
D4
D3
D2
D1
D0
OLIM7
OLIM6
OLIM5
OLIM4
OLIM3
OLIM2
OLIM1
OLIM0
0
1
0
1
1
0
1
0
The STA333IS provides a simple mechanism for reacting to a thermal or overcurrent
warning in the power device. When the TWARN or OCWARN status bit is asserted, the
output is limited to the OLIM setting. The limit can be adjusted by modifying the thermal
warning/overcurrent output limit value. As for the normal postscale, the register value
represents an 8-bit signed fractional number. This number is extended to a 24-bit number,
by adding zeros to the right, and then directly multiplied by the data on both channels. The
scaling value range is from 0x80 = -1 to 0x7F = 0.992. To avoid phase changes in the output
signal only the positive range is used (0x00 to 0x7F). The default setting of 0x5A provides a
-3-dB limit.
If the cause of the limiting is a thermal warning, the output limiting is removed when the
thermal warning situation disappears. If the cause of the limiting is an overcurrent warning,
output limiting remains in effect until the device is reset.
DocID022855 Rev 3
35/43
Register description
STA333IS
Table 46. Output limit values for thermal and overcurrent warnings
OLIM[7:0]
36/43
Attenuation (dB)
0x7F
0.06
0x7E
0.13
....
....
0x5A
3.0
....
....
0x40
6.0
....
....
0x28
10
....
....
0x01
42
0x00
Inf
DocID022855 Rev 3
STA333IS
5.12
Register description
Short-circuit protection registers SHOKx (addr 0x35, 0x37,
0x38)
D7
D6
D5
D4
D3
D2
D1
D0
reserved
reserved
reserved
reserved
reserved
reserved
ENABLE_SH
reserved
0
0
0
0
0
0
0 (default)
1
D7
D6
D5
D4
D3
D2
D1
D0
SHGND1A
SHGND1B
SHGND2A
SHGND2B
SHVCC1A
SHVCC1B
SHVCC2A
SHVCC2B
1
1
1
1
1
1
1
1
D7
D6
D5
D4
D3
D2
D1
D0
reserved
reserved
reserved
reserved
reserved
reserved
reserved
SHOUT
0
0
0
0
0
1
0
1
The following power bridge pin short-circuit protections are implemented in the STA333IS:
•
OUTxx vs GNDx
•
OUTxx vs VCCx
•
OUT1B vs OUT2A
The protection is enabled when reg. 0x35 bit 1 (ENABLE_SH) is set to ‘1’. The protection
will check the short-circuit when the EAPD bit is toggled from ‘0’ to ‘1’ (i.e. the power bridge
is switched on), and only if the test passes (no short) does the power bridge leave the
tristate condition.
Register 0x37 and 0x38 (read-only registers) give more information about the detected short
type. SHGNDxx equal to ‘0’ means that OUTxx is shorted to ground, while the same value
on SHVCCxx means that OUTxx is shorted to Vcc, and finally SHOUT=’0’ means that
OUT1B is shorted to OUT2A. To be noted that once the check is performed and the tristate
released, the short protection is no longer active until the next EAPD 0->1 toggling, which
means that shorts that occurred during normal operation cannot be detected. To be noted
that registers 0x37 and 0x38 are meaningful only after the EAPD bit is set to ‘1’ at least
once.
The short-circuit protections implemented are effective only in BTL configuration, and they
must not be activated if a single-ended application scheme is needed.
Figure 10. Short-circuit protection timing diagram
Sta r t g n d te s t
Sta r t v c c te s t
Start o ut test
En d o f Sh o r t te s t
EAPD
OUT1A
OUT1B
OUT2A
OUT2B
SHOK1[7:4]
SHOK1[3:0]
SHOK2[0]
50005 cycles
44
cycles
50005 cycles
DocID022855 Rev 3
TBD cycles
1cycle
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Application information
STA333IS
6
Application information
6.1
Application scheme for power supplies
Figure 11 below shows a typical application scheme for the STA333IS.
Special care has to be taken with regard to the power supplies when laying out the PCB. In
particular the 3.3-Ω resistors on the digital supplies (VDD_DIG) have to be placed as close
as possible to the device. This prevents unwanted oscillation on the digital parts of the
device due to the inductive effects of the PCB tracks. The same rule also applies to all the
decoupling capacitors; they should be placed as close as possible to the device in order to
limit the effect of spikes on the supplies.
Figure 11. Application diagram
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Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
The STA333IS comes in a CSP 5x6 array package.
Soldering information
Figure 12. Recommended soldering reflow profile for mounting on PCB
Table 47. Recommended soldering reflow values for mounting on PCB
Profile
Typ.
Max.
0.9 °C/s
3 °C/s
2 °C/s
3 °C/s
Peak temp. in reflow
240 - 245 °C
260 °C
Time above 220 °C
60 s
90 s
-2 to -3 °C
-6 °C
Temp. gradient in preheat (T = 70 - 180 °C)
Temp. gradient (T = 200 - 225 °C)
Temp. gradient in cooling
Time from 50 to 220 °C
160 to 220 s
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Package mechanical data
STA333IS
Figure 13 below shows the package outline and Table 48 gives the dimensions.
Figure 13. CSP 5x6 array outline drawing
7224730_I
Note 1: The terminal A1 on the backside of the product is identified by a distinguishing feature (for instance by a
circular "clear area", typically 0.5 mm diameter).
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Package mechanical data
Table 48. CSP 5x6 array package dimensions
mm
Symbol
Min
Typ
Max
A
0.585
0.65
0.715
A1
0.210
0.25
0.29
A2
0.38
0.4
0.42
b
0.265
0.315
0.365
D
2.52
2.57
2.62
D1
E
2
3.19
3.24
E1
3.29
2.5
e
0.45
0.5
0.55
se
0.2
0.25
0.3
fD
0.277
0.285
0.293
fE
0.362
0.370
0.378
ccc
0.08
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Revision history
8
STA333IS
Revision history
Table 49. Document revision history
Date
Revision
16-Jan-2013
1
Initial release.
11-Mar-2013
2
Document status promoted to “production data”
Updated Description on page 1
Updated Table 1: Device summary on page 1
Updated VCC (max) in Table 3: Absolute maximum ratings
Updated RTh(j-case) in Table 4: Thermal data
Updated Vol and Voh in Table 6: Electrical characteristics for digital section
Updated Table 7: Electrical specifications for power section
Updated Figure 6: I2S
Updated Figure 7: Left-justified
Updated Section 4.2: Device addressing
Updated Table 19: Supported serial audio input formats for LSB-first (SAIFB = 1)
Updated Figure 11
02-Apr-2013
3
Textual update in Table 4: Thermal data
Added Figure 12: Recommended soldering reflow profile for mounting on PCB
Added Table 47: Recommended soldering reflow values for mounting on PCB
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Changes
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