EQCO62T20.3/EQCO31T20.3 EQCO62T20.3 6.25 Gbps Asymmetric Coax Driver EQCO31T20.3 3.125 Gbps Asymmetric Coax Driver Features Introduction • Complies with the CoaXPress v1.1 Camera Standard (1) • Supports up to 68 Meters of Cable at 6.25 Gbps Using High-Quality Coax • Supports up to 212 Meters of Cable at 1.25 Gbps Using High-Quality Coax • Single-Chip Solutions for Both the Camera Side and the Frame Grabber Side, Making a Bidirectional Connection Over a Single 75Ω Coax Cable • Full-Duplex, Bidirectional Data Channel - Downlink Speeds from 1.25 Gbps up to 6.25 Gbps; Differential Interfacing Straightforward with Internal Termination Resistors - Uplink Supporting 21 Mbps, Allowing Nanoseconds Precise Triggering Events Driven by the Frame Grabber • Supports Power Distribution Over the Coax up to 900 mA, Powering the Camera Through the Same Coax Transporting Data Signals • Low Power Consumption (<70 mW, 1.2V supply) • 16-Pin, 0.65 mm Pin Pitch, 4 mm QFN Package • Small PCB Footprint for EQCO62T20 and Off-Chip Components, with Guaranteed RF-Performance • -40°C to +85°C Industrial Temperature Range • Pb-Free and RoHS Compliant The EQCO62T/R20(2) chipset is a driver/equalizer chipset that forms a bidirectional, full-duplex communication link over a single coax cable. The EQCO62T/R20 chipset is designed to transport up to 6.25 Gbps over the downlink channel and to transport 21 Mbps over the uplink channel. The EQCO62T20 is designed to transmit the downlink signal up to 6.25 Gbps and receive the uplink signal. The EQCO62R20 is designed to receive the downlink signal up to 6.25 Gbps and to transmit the uplink signal. Power can be transferred over the same cable via external inductors. The chipset is designed to work with several types of 75Ω coaxial cables, including legacy cables as well as thin, flexible lightweight cables. Note 1: CoaXPress V1.1 standard. Free download from the JIIA website: http://jiia.org/en/standardization/list/ 2: The EQCO31T20 and EQCO31R20 are lower-speed versions of the EQCO62T20 and EQCO62R20, with a maximum bit rate of 3.125 Gbps for the high-speed downlink and the same uplink speed. Applications • High-Definition/High-Bandwidth Links to Cameras • Machine Vision for Semiconductor Chips and Display Panel Inspection Systems • Military, Aerospace, Medical Applications • Broadcast and Surveillance Camera Systems • Traffic License Plate and Monitoring Systems • High-Speed Inspection Systems for Food Inspection, Bottling Inspection, Panel Inspection, etc. • Any application requiring a single coax cable which carries power, video data and camera control stream 2011-2016 Microchip Technology Inc. DS60001301B-page 1 EQCO62T20.3/EQCO31T20.3 Typical Link Performance Table 1, Table 2 and Table 3 give an overview of typical link performance at room temperature for the link containing the EQCO62T20 coax driver in conjunction with the EQCO62R20 receiver, using the downlink channel, uplink channel and power transmission simultaneously. Performance for EQCO62T/R20 and EQCO31T/R20 is equal for bit rates up to 3.125 Gbps. TABLE 1: BELDEN TYPICAL LINK PERFORMANCE Name Belden 7731A Belden 1694A Belden 1505A Belden 1505F Belden 1855A Type Long Distance Industry Standard Compromise Coax Flexible Thinnest Cable Diameter (mm) 10.3 6.99 5.94 6.15 4.03 1.25 Gbps (m) 194 130 107 80 55 2.5 Gbps (m) 162 110 94 66 55 3.125 Gbps (m) 147 100 86 60 55 5.0 Gbps (m) 87 60 52 35 38 6.25 Gbps (m) 58 40 35 23 25 TABLE 2: GEPCO TYPICAL LINK PERFORMANCE Name Gepco VHD1100 Gepco VSD2001 Gepco VPM2000 Gepco VHD2000M Gepco VDM230 Type Long Distance Industry Standard Compromise Coax Flexible Thinnest Cable Diameter (mm) 10.3 6.91 6.15 6.15 4.16 1.25 Gbps (m) 212 140 109 81 66 2.5 Gbps (m) 185 120 94 67 66 3.125 Gbps (m) 169 110 86 61 62 5.0 Gbps (m) 102 66 53 36 38 6.25 Gbps (m) 68 44 35 24 25 CANARE TYPICAL LINK PERFORMANCE(1) TABLE 3: Name Canare L-7CFB Canare L-5CFB Canare L-4CFB Canare L-3CFB Canare L-2.5CFB Type Long Distance Industry Standard Compromise Coax Thin Cable Thinnest Cable Diameter (mm) 10.2 7.7 6.1 5.5 4 1.25 Gbps (m) 165 118 94 72 43 2.5 Gbps (m) 135 98 79 66 43 3.125 Gbps (m) 122 88 71 60 43 5.0 Gbps (m) 71 52 42 36 30 6.25 Gbps (m) 46 34 28 24 20 Note 1: Specifications from Canare are only up to 2 GHz. 5 Gbps and 6.25 Gbps performance are by extrapolation. DS60001301B-page 2 2011-2016 Microchip Technology Inc. EQCO62T20.3/EQCO31T20.3 Table of Contents 1.0 2.0 3.0 4.0 Device Overview .......................................................................................................................................................................... 4 Application Information................................................................................................................................................................. 8 Electrical Characteristics ............................................................................................................................................................ 15 Packaging................................................................................................................................................................................... 17 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at email@example.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. 2011-2016 Microchip Technology Inc. DS60001301B-page 3 EQCO62T20.3/EQCO31T20.3 1.0 DEVICE OVERVIEW The EQCO62T/R20 single-coax chipset is designed to simultaneously transmit and receive signals along with power on a single 75Ω coax cable. In one direction, a downlink signal is transmitted. In the opposite direction, a lower-speed uplink is provided. The EQCO62T/R20 chipset consists of two chips. The EQCO62T20 is a high-speed line driver with an integrated low-speed receiver. The EQCO62R20 is a high-speed receiver with an integrated low-speed transmitter. Figure 1-1 illustrates a typical EQCO62T/R20 link setup. The downlink signal is transmitted with 600 mV transmit amplitude at the EQCO62T20 side. This signal is attenuated in the coax and recovered by an equalizer integrated in the EQCO62R20. The low-speed uplink is transmitted with a lower amplitude of 130 mV to limit the crosstalk with the downlink channel. FIGURE 1-1: In addition to the downlink channel and the low-speed uplink, the system allows power transmission over the coax by using ferrite beads and external inductors. These external inductors give the communication channel a high-pass characteristic. The uplink receiver inside the EQCO62T20 chip recovers the signal lost by this high-pass filter. Appropriate inductors need to be selected for correct operation of the link. Correct operation is only guaranteed with the inductor combination used in Figure 2-1, even though other components might be suited. The EQCO62T/R20 chipset is compatible with the CoaXPress v1.1 camera standard. TYPICAL EQCO62T/R20 LINK SETUP Up to 6.25 Gbps downlink High Definition Camera Up to 900 mA DC EQCO 62T20 21 Mbps uplink DS60001301B-page 4 The downlink channel is intended for 8B/10B NRZ coded data with bitrates from 1.25 Gbps up to 6.25 Gbps. The low-speed uplink operates at a bit rate of 21 Mbps, and has a single-ended LVTLL input and output. Up to 212 meters 75Ω Coax Up to 900 mA DC Up to 6.25 Gbps downlink Frame Store + Camera Control EQCO 62R20 21 Mbps uplink 2011-2016 Microchip Technology Inc. EQCO62T20.3/EQCO31T20.3 1.1 Pinout and Pin Description FIGURE 1-2: TABLE 1-1: Pin Number EQCO62T20.3 PIN DIAGRAM(VIEWED FROM TOP) NC NC LFO LFVCC 16 15 14 13 GND 1 12 VCC SDIp 2 11 SDOp SDIn 3 10 SDOn GND 4 9 VCC EQCO62T20.3 GND TAB 5 6 7 8 NC NC NC NC EQCO62T20.3 PIN DESCRIPTIONS Pin Name Signal Type Description (TAB) GND Power Connect to ground. 9, 12 VCC Power Connect to +1.2V of power supply. 1, 4 GND Power Connect to ground of power supply. 2, 3 SDIp/SDIn Differential Input Serial input positive/negative differential serial input. Typical input swing is 2x300 mV. Minimal input swing is 2x250 mV. 2x50Ω on-chip termination resistor. 11, 10 SDOp/SDOn Differential Output Differential serial output pair. On-Chip 75Ω termination resistors. SDOp is connected to the coax cable by a capacitor. SDOn needs to be connected to GND by 75Ω termination resistor and capacitor. Swing is fixed to VCC/2. 13 LFVCC Power Power supply for the uplink output (between 1.2V and 3.3V). 14 LFO Output Low-frequency uplink output. LVTTL with output swing equal to LFVCC. Supports capacitive loads up to 20 pF for 21 Mbps operation. 5, 6, 7, 8, 15, 16 NC 2011-2016 Microchip Technology Inc. — Do not connect. Leave these pins floating. Used for internal testing. DS60001301B-page 5 EQCO62T20.3/EQCO31T20.3 1.1.1 SDIp/SDIn SDIp/SDIn together form a differential input pair. The serial data received on these pins will be transmitted on SDOp/SDOn. The input pre-driver automatically corrects for variations in signal levels and different edge slew rates at these inputs before they go into the active splitter/combiner for transmission over the coax. Between SDIp and SDIn inputs, there is a termination resistor of 100Ω. The intention is to always use AC coupling. A transmit wake-up detection circuit puts both the input pre-driver and the output driver into a low-power mode when no signal is detected on the SDIp/SDIn signal pair. 1.1.2 SDOp/SDOn The signal at the inputs SDIp/SDIn is transmitted onto the cable by outputs SDOp/SDOn. Both outputs are internally terminated with 75Ω. The signal on the SDOp pin is the sum of the incoming signal (i.e. the signal transmitted by the EQCO62R20 on the far end side of the coax) and the outgoing signal (i.e. the signal created based on SDIp/SDIn). The farend signal is extracted by subtraction of the near-end signal and the far-end signal, and is restored by the uplink receiver inside the EQCO62T20 chip. The SDOn signal carries a precise anti-phase signal to the transmitted signal on SDOp. SDOn must be connected directly to GND at the connector via a resistor precisely matched to the impedance of the coaxial cable used and an AC coupling capacitor. 1.1.3 LFO LFO is the output of the uplink receiver inside the EQCO62T20. The maximum allowed capacitance at the output is 20 pF, with rise and fall times of 5 ns. The maximum output current is 1 mA when LFVCC is 3.3V. 1.1.4 LFVCC The output driver of the uplink receiver in the EQCO62T20 has a separate power supply pin. The power supply voltages can be 1.2V up to 3.3V. The output swing at LFO is equal to this power supply voltage. A filter capacitor must be placed close to the LFVVC pin of the EQCO62T20. DS60001301B-page 6 2011-2016 Microchip Technology Inc. EQCO62T20.3/EQCO31T20.3 1.2 Circuit Operation FIGURE 1-3: EQCO62T20.3 BLOCK DIAGRAM SHOWING ELECTRICAL CONNECTIONS EQCO62T20.3 SDIp Input Pre-Driver SDIn Transmit Detection PRE-DRIVER The pre-driver removes any dependency for the amplitude and rise time of the incoming signal on SDI. 1.2.2 ACTIVE SIGNAL SPLITTER/ COMBINER The active splitter/combiner controls the amplitude and rise time of the outgoing coax signal and transmits it via a 75Ω output termination resistor. The output resistor, when balanced with the coax characteristic impedance, also forms part of a hybrid splitter circuit which subtracts the TX output from the signal on the SDO output to give yield the far-end TX signal. 1.2.3 SDOn LF receiver LF Output Driver LFO 1.2.1 SDOp Active Signal Splitter/Combiner TRANSMIT DETECTION The transmit detection detects if an input signal is applied at SDI. The detection circuit looks at the signal amplitude of SDI; if no signal is detected, the pre-driver and output driver are disabled. The LF receiver then continues to operate independently. At the moment the output driver is turned on or off, there can be a bit error in the uplink channel, e.g. by the LF-receiver. 2011-2016 Microchip Technology Inc. 1.2.4 LF RECEIVER The uplink receiver removes unwanted crosstalk from the transmitted near-end signal. Afterwards, the uplink signal is restored by detecting edges coming from the uplink signal. At the moment the high-speed output driver is turned on or off, there can be a bit error in the uplink channel, e.g. by the LF-receiver. The initial output state of the LF receiver can be wrong, and subsequent bits will still be received correctly. 1.2.5 LF OUTPUT DRIVER The uplink output driver converts the signal detected by the LF receiver to an LVTTL signal with a controlled rise and fall time. It is required to set the output signal amplitude of this LVTTL signal by connecting the LFVCC to the appropriate power supply voltage (max 3.3V). DS60001301B-page 7 EQCO62T20.3/EQCO31T20.3 2.0 APPLICATION INFORMATION Figure 2-1 illustrates a typical schematic implementation. FIGURE 2-1: TABLE 2-1: EQCO62T20.3 TYPICAL APPLICATION CIRCUIT COMPONENT RECOMMENDATION FOR THE EQCO62T20.3 BOARD LAYOUT Element Value Size Recommended Component Fb1, Fb2 1 kΩ @ 100 MHz Ferrite Bead 0603 FBMH1608HM102 from Taiyo Yuden (Critical) L1 10 µH 1812 1812PS_103 from Coilcraft (Critical) R1 75Ω ±1% 0402 R3 1 kΩ 0402 C1 33 nF, 50V, X7R C2 33 nF, X7R 0402/0603 0603 C3, C4, C5 100 nF, X7R 0402 C6 10 nF, 50V, X7R 0402 C7 1 µF, 50V, X7R 0805 C8, C9, C10 10 nF, X7R 0402 BNC1 75Ω right angle BNC connector Ferrite Beads Fb1 and Fb2 (FBMH1608HM102 from Taiyo Yuden) and inductor L1 (1812PS_103 from Coilcraft [10 µH]) are recommended for CoaXPress. For other applications the inductor value can be larger, leading to a physical larger inductor. DS60001301B-page 8 5413558-1 from Tyco (Recommended) Connector BNC1 (75Ω right angle BNC connector 5413558-1 from Tyco) is recommended for CoaXPress. Other inductors/ferrite beads/BNC connectors can possibly be used, however, they must be selected carefully for their RF-performance, since performance can decrease significantly. 2011-2016 Microchip Technology Inc. EQCO62T20.3/EQCO31T20.3 2.1 Guidelines for PCB Layout When using the EQCO62T/R20 chipset at its full purpose, including low-speed uplink and power supply transmission, it is important not to disturb the RFperformance of the high-speed downlink channel. Implementing the circuit illustrated in Figure 2-1 with a different PCB layout will in first instance not deliver full data sheet performance. The simplest way of meeting optimal performance, including jitter and return-loss requirements, is to precisely follow the component and layout recommendations. Note that at multi-gigabit speeds, using "equivalent" components or small PCB layout changes (even moving a via) can have significant detrimental effects. FIGURE 2-2: The easiest way for achieving the requirements of the CoaXPress 1.1 specification is to use the recommended circuits, components and layout illustrated in Figure 2-1. For easy implementation, Microchip will provide the Gerber file. Please ask for it by email. Note: 2.1.1 Email address: firstname.lastname@example.org RIGHT ANGLE BNC Figure 2-2 below shows the four layers of the recommended footprint for the EQCO62T20.3 chip and the off-chip components that are critical for the RF-performance of the system. RECOMMENDED PCB LAYOUT FOR EQCO62T20.3 2011-2016 Microchip Technology Inc. DS60001301B-page 9 EQCO62T20.3/EQCO31T20.3 In this layout, the size of the PCB area needed for the chip is minimized. Approximately two times the BNC footprint area is required for the full bidirectional system: including the necessary elements for the power transport. The differential input of the chip must be a 100Ω differential transmission line. To minimize the parasitic capacitance of the input pins, a cut-out of the ground and power plane underneath the input pins is recommended. For best performance, no vias should be used in this high-speed signal path. FIGURE 2-3: A large cut-out underneath the right angle BNC connector, the AC coupling capacitors, ferrite beads and inductor is needed for minimal parasitics. This proposed layout is designed to be largely independent of the used PCB-layer stack. This will work as well for four, six or even higher numbers of layers. Possible extra layers should have cut-outs as large as the full proposed footprint. PCB LAYOUT OF MULTILANE COAXPRESS 0V1 DEMO BOARD PAIR Camera Side CD_1 CD_2 CD_3 CD_4 EQ_5 5x6.25Gb/s + 5x21Mb/s CD_5 EQ_4 EQ_3 EQ_2 EQ_1 Host Side DS60001301B-page 10 2011-2016 Microchip Technology Inc. EQCO62T20.3/EQCO31T20.3 2.1.2 MULTILANE COAXPRESS 4+1 LAYOUT WITH DIN1.0/2.3 CONNECTORS Figure 2-3 shows an example of a Multilane CoaXPress 4+1 setup. The recommended Din1.0/2.3 connector is the NPF 4076 from Cambridge Connectors. The cable example shows the pitches in millimeters. Figure 2-4 shows the four layers of the recommended footprints and the off-chip components that are critical for RF-performance of the cable drivers CD_1 to CD_4 at the camera side, which have Power over CoaXPress (PoCXP). Figure 2-5 shows the variant without PoCXP used for CD_5 at the host side. The exact dimensions in millimeters are given in Section 4.1 “Package Marking Information”. It is recommended to copy these dimensions, especially the connection between the DIN1.0/2.3 connector and the chip, as this is a complex entity with coupled currents and compensated parasitic capacitances. Despite the critical layout, this proposed layout is designed to be largely independent of the used PCBlayer stack, as the critical parts are mainly the top-layer only. This will work as well for four, six or even higher numbers of layers. Possible extra layers should have cut-outs as large as the full proposed footprint. In these layouts, the size of the PCB area needed for the chip is minimized. This allows multiple lanes close together. Only two of four connector GND pins are connected to the GND plane to reduce the capacitance. The differential CD inputs must be a 100Ω differential transmission line. A cut-out of the ground and power plane underneath the input pins is recommended to minimize the parasitic capacitance. For best performance, no vias should be used in this high-speed signal path. The Components Express 4+1 connector in Figure 2-3 is only shown as an example. Other connector configurations are available with DIN1.0/2.3 connectors such as 6+1, 2+1, 1+1, dual or single lane configurations. 2011-2016 Microchip Technology Inc. DS60001301B-page 11 EQCO62T20.3/EQCO31T20.3 FIGURE 2-4: RECOMMENDED PCB LAYOUT FOR EQCO62T20.3 WITH DIN1.0/2.3 CONNECTOR WITH PoCXP Top Ground F G E M H V3 V1 V2 D C V5 A B V7 K I N L V4 J V6 O P V8 Q S T V9 R V10 Bottom Power V W Z X Y Â U Î Ê Ô DS60001301B-page 12 2011-2016 Microchip Technology Inc. EQCO62T20.3/EQCO31T20.3 FIGURE 2-5: RECOMMENDED PCB LAYOUT FOR EQCO62T20.3 WITH DIN1.0/2.3 CONNECTOR WITHOUT PoCXP Ground Top Aa Dd Bb V4 Cc V3 V5 V7 Ee V6 V8 Sg Th Ff Power Bottom Ai Dl Bj Ck Em Sn To 2011-2016 Microchip Technology Inc. DS60001301B-page 13 EQCO62T20.3/EQCO31T20.3 2.2 Guidelines for Power Receive Unit At the Power-OUT connection, the voltage supply for the camera (including the power supply for the EQCO62T20.3) is expected. This load current should have low ripple. Highfrequency ripple will be rejected by C7/L1/FB1/FB2 filtering in the reference circuit. However, mid-frequency ripple is to be avoided by the power supply itself. In a typical application, one could want to step-down from the 24V supply to all supply voltages needed inside the camera. It is in this case preferred to use a DC-to-DC converter that has a high switching frequency (e.g. 2 MHz) above one that has lower switching frequency (200 kHz). The latter typically induces larger voltage spikes at the Power-OUT connection. These will be only partially filtered out by said filter; the remainder will become crosstalk for the uplink channel. When too much crosstalk remains on the uplink channel, additional power supply filtering is required. This may be achieved by placing an extra filter network (not shown) in series with the Power-OUT node. 2.3 Power Over CoaXPress The EQCO62T20.3 is compatible with the Power over CoaXPress system (PoCXP). Hence, power can be switched on and off by the host (e.g. frame grabber) through the 10 µH inductor specified by the CXP standard. This switching is supported through a relay and through an electronic switch. Powering through a wide-band bias-T is also supported. The EQCO62T20.3 is also protected against the following events: • Hot plugging by frame grabber: in case the frame grabber has already applied its 24V on the coax when connecting the cable, no damage will occur to the EQCO62T20.3 when connecting the powered coax cable. • Fast turn on and turn off of power supply by frame grabber Direct 24V application, i.e. not through a 10 µH inductor, is not supported since it causes permanent damage to the EQCO62T20 device. DS60001301B-page 14 2011-2016 Microchip Technology Inc. EQCO62T20.3/EQCO31T20.3 3.0 ELECTRICAL CHARACTERISTICS 3.1 Absolute Maximum Ratings Stresses beyond those listed under this section may cause permanent damage to the device. These are stress ratings only and are not tested. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. TABLE 3-1: ABSOLUTE MAXIMUM RATINGS Parameter Conditions Min. Typ. Max. Units -65 — +150 °C Power Applied -55 — +125 °C Normal Operation (VCC = 1.2V ±5%) -40 — +85 °C Supply Voltage to Ground -0.5 — +1.4 V DC Input Voltage -0.5 — +1.6 V -0.5 — +1.6 V — — 90 mA Storage Temperature Ambient Temperature Operating Temperature DC Voltage to Outputs Current into Outputs TABLE 3-2: Outputs Low ELECTRICAL CHARACTERISTICS (OVER THE OPERATING VCC AND -40 TO +85°C RANGE) Parameter Description Min. Typ. Max. Unit 1.15 1.2 1.25 V Power Supply VCC Supply Voltage IS Supply Current, both Transmitting and Receiving — 60 — mA Isr Supply Current when only Receiving — 30 — mA 2x250 2x300 — mV SDIp/SDIn Input ⌂Vi Input Amplitude VSDIp,n Vturnon ⌂Vi to Turn On Transmit Function — 2x150 2x250 mV Vturnoff ⌂Vi to Turn Off Transmit Function 2x50 2x150 — mV Rinput Differential Input Termination — 2x50 — Ω SDOp Connection to Coax Zcoax Coax Cable Characteristic Impedance — 75 — Ω RSDOp Input Impedance between SDOp and VCC/GND — 75 — Ω Rloss Coax Return Loss as Seen on SDOp pin Frequency Range = 5 MHz-1 GHz — — -15 dB Rloss Coax Return Loss as Seen on SDOp pin Frequency Range = 1 GHz-1.5 GHz — — -10 dB Rloss Coax Return Loss as Seen on SDOp pin Frequency Range = 1.5 GHz-3.2 GHz — — -7 dB ⌂VTX Transmit Amplitude 500 600 700 mV trise_tx Rise/Fall Time 20% to 80% of ⌂Vtx — — 80 ps DCD Duty Cycle Distortion on of VSDOp — 5 — ps 2011-2016 Microchip Technology Inc. DS60001301B-page 15 EQCO62T20.3/EQCO31T20.3 TABLE 3-2: ELECTRICAL CHARACTERISTICS (OVER THE OPERATING VCC AND -40 TO +85°C RANGE) (CONTINUED) LFO Output (LVTTL-Like) LFVCC Uplink Output Driver Power Supply 1.2 — 3.3 V Rise/Fall Time 20% to 80% of VLFO for 20 pF Load LFVCC = 1.2V — 6 — ns trise_LFO LFVCC = 3.3V — 5 — ns Min. Typ. Max. Units TABLE 3-3: JITTER NUMBERS Parameter Conditions Additive Peak to Peak Jitter on SDOp/SDOn (EQCO62T20) Downlink Signal = 1.25 up to 6.25 Gbps, prbs7 — — 30 ps EQCO31T20 Downlink Signal = 1.25 up to 3.125 Gbps, prbs7 — — 30 ps Peak to Peak Jitter on LFO 0-130m Belden 1694A coax, Over Full VCC and Temperature Range; Low-Speed Signal = 21 Mbps, 8B/10B, Downlink Signal= 1.25-6.25 Gbps,8B/10B — — 15 ns DS60001301B-page 16 2011-2016 Microchip Technology Inc. EQCO62T20.3/EQCO31T20.3 4.0 PACKAGING INFORMATION 4.1 Package Marking Information 16-Lead Plastic Quad Flat, No Lead Package – 4x4x0.9 mm Body [QFN] 16-Lead QFN (4x4x0.9 mm) PIN 1 Example PIN 1 EQCO 62T20.3 YYWWNNN Legend: XX...X Y YY WW NNN e3 * Note: YYWWNNN Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2011-2016 Microchip Technology Inc. DS60001301B-page 17 EQCO62T20.3/EQCO31T20.3 16-Lead Plastic Quad Flat, No Lead Package (8E) - 4x4x0.9 mm Body [QFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A B N NOTE 1 1 2 E (DATUM B) (DATUM A) 2X 0.20 C 2X TOP VIEW 0.20 C 0.10 C C A1 A SEATING PLANE 16X SIDE VIEW (A3) 0.10 0.08 C C A B D2 (16X K) 0.10 C A B E2 e 2 2 1 16X L N e BOTTOM VIEW 16X b 0.10 0.05 C A B C Microchip Technology Drawing C04-259B Sheet 1 of 2 DS60001301B-page 18 2011-2016 Microchip Technology Inc. EQCO62T20.3/EQCO31T20.3 16-Lead Plastic Quad Flat, No Lead Package (8E) - 4x4x0.9 mm Body [QFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits Number of Pins N e Pitch A Overall Height Standoff A1 A3 Terminal Thickness Overall Width E E2 Exposed Pad Width D Overall Length D2 Exposed Pad Length b Terminal Width Terminal Length L K Terminal-to-Exposed-Pad MIN 0.80 0.00 1.95 1.95 0.25 0.45 MILLIMETERS NOM 16 0.65 BSC 0.87 0.02 0.20 REF 4.00 BSC 2.05 4.00 BSC 2.05 0.30 0.55 0.425 REF MAX 0.95 0.05 2.15 2.15 0.35 0.65 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-259B Sheet 2 of 2 2011-2016 Microchip Technology Inc. DS60001301B-page 19 EQCO62T20.3/EQCO31T20.3 16-Lead Plastic Quad Flat, No Lead Package (8E) - 4x4x0.9 mm Body [QFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C1 X2 16 G1 1 X1 2 C2 Y2 Y1 E SILK SCREEN RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Optional Center Pad Width X2 Optional Center Pad Length Y2 Contact Pad Spacing C1 Contact Pad Spacing C2 Contact Pad Width (X16) X1 Contact Pad Length (X16) Y1 Contact Pad to Center Pad (X16) G1 MIN MILLIMETERS NOM 0.65 BSC MAX 2.15 2.15 3.625 3.625 0.30 0.725 0.20 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2259A DS60001301B-page 20 2011-2016 Microchip Technology Inc. EQCO62T20.3/EQCO31T20.3 APPENDIX A: REVISION HISTORY Revision B (March 2016) • Updated Section 4.0 “Packaging Information”. • Removed electrostatic discharge ratings from Table 3-1. • Minor typographical changes. Revision A (August 2014) • This is the initial release of the document in the Microchip format. This replaces EqcoLogic document version 1v5. TABLE A-1: REVISION HISTORY Version Date 1v5 1/27/14 Added references 1v4 4/10/12 Added Multilane CoaXPress 4+1 layout with DIN1.0/2.3 connectors 1v3 10/4/11 Section 5.5 on PoXCXP was added 1v2 9/29/11 C1 and C2 in application circuit of Figure 5 have changed to 33 nF 1v1 8/31/11 Quality review 1v0 8/30/11 Initial release of this document 2011-2016 Microchip Technology Inc. Comments DS60001301B-page 21 EQCO62T20.3/EQCO31T20.3 APPENDIX B: TYPICAL LINE DRIVER CHARACTERISTICS All measurements at VCC = 1.2V, Temp = +25ºC, data pattern = PRBS7, 2x300 mV input amplitude. Note: The imperfections in the output eye are caused by the limited bandwidth of the 75Ω to 50Ω matching pad that was used in this setup. The output amplitude is reduced due to this matching pad. FIGURE B-1: 1.25 GBPS FIGURE B-4: 2.5 GBPS FIGURE B-2: 3.125 GBPS FIGURE B-5: 5 GBPS (EQCO62T20 ONLY) FIGURE B-3: 6.25 GBPS (EQCO62T20 ONLY) DS60001301B-page 22 2011-2016 Microchip Technology Inc. EQCO62T20.3/EQCO31T20.3 APPENDIX C: TYPICAL UPLINK CHARACTERISTICS All measurements at VCC = 1.2V, Temp = +25ºC, data pattern = 8B/10B test pattern at 21 Mbps, 110 mV transmit amplitude using Belden 1694A coaxial cable. Measurements include power supply transmission; EQCO62T20 is powered over the cable. Measured into 15 pF capacitive load. FIGURE C-1: 0M, NO DOWNLINK SIGNAL FIGURE C-3: 130M, NO DOWNLINK SIGNAL FIGURE C-2: 0M, DOWNLINK SIGNAL = 1.25 GBPS, 8B/10B CODED SIGNAL FIGURE C-4: 130M, DOWNLINK SIGNAL = 1.25 GBPS, 8B/10B CODED SIGNAL 2011-2016 Microchip Technology Inc. DS60001301B-page 23 EQCO62T20.3/EQCO31T20.3 APPENDIX D: TYPICAL RETURN-LOSS Figure D-1 shows the return-loss at the BNC connector of the EQCO62T20.3 evaluation board as shown in Section 2.0 “Application Information” and Section 2.1 “Guidelines for PCB Layout” with a supply current of 0 mA and 703 mA (maximum supply current for CoaXPress) through the inductor (L1) and the ferrite beads (Fb1 & Fb2) and compares it with the CoaXPress (Full-Speed) return-loss specification. FIGURE D-1: RETURN-LOSS OF THE EQCO62T20.3 BNC EVALUATION BOARD WITH AND WITHOUT SUPPLY CURRENT DS60001301B-page 24 2011-2016 Microchip Technology Inc. EQCO62T20.3/EQCO31T20.3 APPENDIX E: FIGURE E-1: FOOTPRINTS USED FOR THE MULTILANE COAXPRESS LAYOUT 0402, 0603 AND VIA WITH THERMAL ISOLATION FOOTPRINTS 0.90 0.35 drill 0.60 0.52 0.40 0.71 copper 1.20 FIGURE E-2: 0.30 0.75 0.52 DIN1.0/2.3 AND L1 INDUCTOR 1812 FOOTPRINTS 0.80 drill 2.28 3.00 1.50 copper 2.54 1.60 drill 2.60 copper 2.54 1.60 TABLE E-1: Component NPF 4076 COMPONENT POSITIONS OF Figure 2-4 Footprint X Y Angle DIN1.0/2.3 0 0 — EQCO62T20.3 QFN 0 -7.4 — C1 (50V) 0603 -0.325 -2.4 90° C2 0402 0.675 -2 90° R1 0402 0.675 -3.6 90° FB1 0603 -2.025 0.6 — FB2 0603 -2.025 -0.6 — R3 0402 -4.025 0.3 — C6 (50V) 0402 -4.5 1.675 90° C9 0402 -1.975 -4.4 — C10 0402 1.875 -4.4 — C8 0402 -3.325 -10.35 90° 2011-2016 Microchip Technology Inc. Bottom DS60001301B-page 25 EQCO62T20.3/EQCO31T20.3 Footprint X Y Angle L1 Component 1812 -4.5 -7.875 90° Bottom C7 (50V) 0603 -1.6 -7.325 90° Bottom C5 0402 0 -9.825 90° Bottom TABLE E-2: VIA POSITIONS OF Figure 2-4 VIA Thermal 1 2 X Y Connected To -4.9 -4.4 Top-Bottom -4.1 -4.4 Top-Bottom -1.575 -5.15 Top-Power 3 Not isolated 4 Not isolated 1.575 -5.15 Top-Power 5 Not isolated -2.325 -5.575 Top-GND-Bottom 6 Not isolated 2.275 -5.65 Top-GND-Bottom 7 Isolated -1.575 -9.375 Top-GND-Bottom 8 Isolated 1.575 -9.375 Top-GND-Bottom 9 Isolated -0.95 -10.35 Power-Bottom 10 Isolated 0.95 -10.35 Power-Bottom TABLE E-3: GROUND AND VCC PLANE POSITION OF Figure 2-4 GND Plane Coordinates A X Y -3.15 -9.4 VCC Plane Coordinates X Y U -2.475 -9.45 B -2.475 -8.725 V -2.475 -5.225 C -2.475 -6.225 W -0.8 -5.225 D -2.775 -5.925 X -0.8 -6.3 E -2.775 -2.525 Y 0.8 -6.3 F -1.25 -2.525 Z 0.8 -5.225 G -1.25 -3.175 Â 2.475 -5.225 H 0.675 -3.75 Ê 2.475 -9.45 I 0.675 -6.3 J 0.8 -6.3 K 0.8 -4.9 L 1.525 -4.175 M 1.525 -2.525 N 2.375 -2.525 O 2.375 -5.7 P 2.475 -5.7 Q 2.475 -8.725 R 3.15 -9.4 S -0.8 -8.5 Î -0.8 -8.5 T 0.8 -10.05 Ô 0.8 -10.35 DS60001301B-page 26 2011-2016 Microchip Technology Inc. EQCO62T20.3/EQCO31T20.3 FIGURE E-3: TRACK DIMENSIONS OF Figure 2-4 Track Width 1 0.3 2 100Ω QFN.1; QFN.4 (GND) diff(1) QFN.2-3 (SDIp-SDIn) 3 0.3 QFN.9;QFN.12 (VCC) 4 0.2 QFN.10 (SDOn) 5 0.3 QFN.11 (SDOp) 6 0.2 QFN.12 (LFVCC) 7 0.2 QFN.13 (LFO) 8 0.4/0.2 QFN.TAB to C9,C10 9 0.5 C9,C10 to DIN1.0/2.3 10 0.5 C9,C10 to V3,4 11 0.4 C1 to DIN1.0/2.3 12 0.4 C2 13 0.4/0.7 FB 14 0.2 C6 15 0.5 Bottom Tracks Width and spaces between lines needs to be calculated based on PCB layer stack. Impedance should be 100Ω differential. Note 1: TABLE E-4: Component NPF 4076 COMPONENT POSITIONS OF Figure 2-5 Footprint X Y Angle DIN1.0/2.3 0 0 — EQCO62T20.3 QFN 0 -6.375 — C1 (50V) 0603 -0.525 -2.125 90° C2 0402 1.6 -0.05 90° R1 0402 0.675 -2.375 90° C9 0402 -3 -4.85 90° C10 0402 3 -4.85 90° C8 0402 -3.45 -7.55 90° C5 0402 0 -6.775 90° TABLE E-5: VIA Bottom Bottom VIA POSITIONS OF Figure 2-5 Thermal X Y Connected To 3 Not isolated -1.6 -4.325 Top-Power 4 Not isolated 1.6 -4.325 Top-Power 5 Isolated -3.675 -5.25 Top-GND-Bottom 6 Isolated 3 -6.025 Top-GND-Bottom 7 Isolated -1.5 -8.025 Top-GND-Bottom 8 Isolated 1.5 -8.025 Top-GND-Bottom 2011-2016 Microchip Technology Inc. DS60001301B-page 27 EQCO62T20.3/EQCO31T20.3 TABLE E-6: GROUND PLANE POSITION OF Figure 2-5 GND Plane Coordinates X Y a -1.15 -3.1 b -1.15 c 1.15 VCC Plane Coordinates X Y h -1.15 -3.95 -5.3 i -1.15 -5.3 -5.3 j 1.15 -5.3 d 1.15 -3.1 k 1.15 -3.95 e 4.225 -3.1 l 3.925 -3.95 f -0.8 -7.475 m -0.8 -7.475 g 0.8 -9.025 n 0.8 -9.325 FIGURE E-4: TRACK WIDTHS OF Figure 2-5 Track Width 1 0.3 2 100Ω diff. QFN.1; QFN.4 (GND) QFN.2-3 (SDIp-SDIn) 3 0.3 QFN.9; QFN.12 (VCC) 4 0.2 QFN.10 (SDOn) 5 0.3 QFN.11 (SDOp) 6 0.2 QFN.12 (LFVCC) 7 0.2 QFN.13 (LFO) 8 0.2 QFN.TAB to C9,C10 9 0.4 C9,C10 to V3,4 10 0.5 C9,C10 to V5,6 11 0.4 C1 to DIN1.0/2.3 12 0.4 C2 13 0.5 Bottom tracks FIGURE E-5: USED LAYER STACK DS60001301B-page 28 2011-2016 Microchip Technology Inc. EQCO62T20.3/EQCO31T20.3 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our web site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: Users of Microchip products can receive assistance through several channels: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQs), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://microchip.com/support CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions. 2011-2016 Microchip Technology Inc. DS60001301B-page 29 EQCO62T20.3/EQCO31T20.3 PRODUCT IDENTIFICATION SYSTEM To order parts, including industrial, or obtain information, for e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. I RM Device Temp. Range Radio Module XXX Firmware F Revision Number Examples: a) b) Device: EQCO62T20.3 Temperature Range: I Package: DS60001301B-page 30 EQCO62T20.3 = Industrial temperature, 16-Lead QFN Tube packaging EQCO62T20.3-TRAY = Industrial temperature, 16-Lead QFN Tray packaging = -40C to +85C (Industrial temperature) TRAY = Tray (Blank) = Tube 2011-2016 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, AnyRate, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, ETHERSYNCH, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2011-2016 Microchip Technology Inc. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2011-2016, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. 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