1-, 2- and 4-Channel Low Capacitance ESD Arrays

CM1215
1, 2 and 4-Channel
Low Capacitance
ESD Arrays
Product Description
http://onsemi.com
The CM1215 family of diode arrays provides ESD protection for
electronic components or sub−systems requiring minimal capacitive
loading. These devices are ideal for protecting systems with high data
and clock rates or for circuits requiring low capacitive loading. Each
ESD channel consists of a pair of diodes in series which steer the
positive or negative ESD current pulse to either the positive (VP) or
negative (VN) supply rail. The CM1215 protects against ESD pulses
up to ±15 kV per the IEC 61000−4−2 standard.
This device is particularly well−suited for protecting systems using
high−speed ports such as USB2.0, IEEE1394 (Firewire®, iLinkt),
Serial ATA, DVI, HDMI and corresponding ports in removable
storage, digital camcorders, DVD−RW drives and other applications
where extremely low loading capacitance with ESD protection are
required in a small package footprint.
SOT23−3
SO SUFFIX
CASE 419AH
SOT23−5
SO SUFFIX
CASE 527AH
SOT23−6
SO SUFFIX
CASE 527AJ
MARKING DIAGRAM
Features
• One, two, and four channels of ESD Protection
• Provides ±15 kV ESD Protection on Each Channel Per the IEC
•
•
•
•
•
•
•
SOT143
SR SUFFIX
CASE 527AF
61000−4−2 ESD Requirements
Channel Loading Capacitance of 1.6 pF Typical
Channel I/O to GND Capacitance Difference of 0.04 pF Typical
Mutual Capacitance of 0.13 pF Typical
Minimal Capacitance Change with Temperature and Voltage
Each I/O Pin Can Withstand Over 1000 ESD Strikes
SOT Packages
These Devices are Pb−Free and are RoHS Compliant
Applications
• IEEE1394 Firewire® Ports at 400 Mbps / 800 Mbps
• DVI Ports, HDMI Ports in Notebooks, Set Top Boxes, Digital TVs,
LCD Displays
• Serial ATA Ports in Desktop PCs and Hard Disk Drives
• PCI Express Ports
• General Purpose High−Speed Data Line ESD Protection
E151 MG
G
E152 MG
G
E153 MG
G
E154 MG
G
1
1
1
XXXX = Specific Device Code
M
= Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device
Package
Shipping†
CM1215−01SO
SOT23−3
(Pb−Free)
3000/Tape & Reel
CM1215−02SR
SOT143
(Pb−Free)
3000/Tape & Reel
CM1215−02SO
SOT23−5
(Pb−Free)
SOT23−6
(Pb−Free)
3000/Tape & Reel
CM1215−04SO
3000/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2011
July, 2011 − Rev. 3
1
Publication Order Number:
CM1215/D
CM1215
BLOCK DIAGRAM
VP
VP
CH1
CH4
CH1
VN
CM1215−01SO
VP
CH3
CH2
VN
CM1215−02SO
CM1215−02SR
CH1 VN CH2
CM1215−04SO
PACKAGE / PINOUT DIAGRAMS
Top View
CH1
VN
1
CH1
3−Pin SOT23−3
2
CH2
3
4−Pin SOT143
NC
1
VN
2
CH1
3
5
VP
4
CH2
5−Lead SOT23−5
CH1
1
VN
2
CH2
3
E154
VN
2
VP
4
Top View
E153
3
1
Top View
E152
E151
VP
Top View
6
CH4
5
VP
4
CH3
6−Pin SOT23−6
Table 1. PACKAGE PIN DESCRIPTIONS
SOT23−3
SOT143
SOT23−5
SOT23−6
Pin Name
Pin No.
Pin No.
Pin No.
Pin No.
Type
CH1
1
2
3
1
I/O
Description
ESD Channel
VN
3
1
2
2
GND
CH2
−
3
4
3
I/O
ESD Channel
CH3
−
−
−
4
I/O
ESD Channel
VP
2
4
5
5
PWR
CH4
−
−
−
6
I/O
ESD Channel
N/C
−
−
1
−
−
No Connection
http://onsemi.com
2
Negative voltage supply rail
Positive voltage supply rail
CM1215
SPECIFICATIONS
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Units
Operating Supply Voltage (VP−VN)
6
V
Diode Forward DC Current (Note 1)
20
mA
(VN−0.5) to (VP+0.5)
V
Ambient
−40 to +85
°C
Junction
−40 to +125
°C
Storage Temperature Range
−40 to +150
°C
DC Voltage at any Channel Input
Operating Temperature Range
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. STANDARD OPERATING CONDITIONS
Parameter
Operating Temperature Range
Rating
Units
–40 to +85
°C
Package Power Rating
SOT23−3 Package (CM1215−01SO)
SOT143 Package (CM1215−02SR)
SOT23−5 Package (CM1215−02SO)
SOT23−6 Package (CM1215−04SO)
mW
225
225
225
225
Table 4. ELECTRICAL OPERATING CHARACTERISTICS (Note 1)
Symbol
Parameter
Conditions
VP
Operating Supply Voltage (VP−VN)
IP
Operating Supply Current
(VP−VN) = 3.3 V
VF
Diode Forward Voltage
Top Diode
Bottom Diode
IF = 20 mA; TA = 25°C
Channel Leakage Current
Channel Input Capacitance
ILEAK
CIN
ΔCIN
CMUTUAL
VESD
VCL
RDYN
Min
0.6
0.6
Typ
Max
Unit
3.3
5.5
V
8
mA
V
0.8
0.8
0.95
0.95
TA = 25°C; VP = 5 V, VN = 0 V
±0.1
±1.0
mA
At 1 MHz, VP = 3.3 V,
VN = 0 V, VIN = 1.65V;
1.6
2.0
pF
Channel I/O to GND Capacitance Difference
Mutual Capacitance
(VP−VN) = 3.3 V
ESD Protection
Peak Discharge Voltage at any channel input,
in system, contact discharge
per IEC 61000−4−2 standard
TA = 25°C
(Notes 2 and 3)
Channel Clamp Voltage
Positive Transients
Negative Transients
IPP = 1 A, tP = 8/20 mS;
TA = 25°C;
Dynamic Resistance
Positive transients
Negative transients
IPP = 1 A, tP = 8/20 mS;
TA = 25°C;
1. All parameters specified at TA = −40°C to +85°C unless otherwise noted.
2. Standard IEC 61000−4−2 with CDischarge = 150 pF, RDischarge = 330 W, VP = 3.3 V, VN grounded.
3. From I/O pins to VP or VN only. VP bypassed to VN with low ESR 0.2 mF ceramic capacitor.
http://onsemi.com
3
0.04
pF
0.13
pF
kV
±15
VP+1.5
VN−1.5
0.4
0.4
V
W
CM1215
PERFORMANCE INFORMATION
Input Channel Capacitance Performance Curves
Figure 1. Typical Variation of CIN vs. VIN
(f = 1 MHz, VP= 3.3 V, VN = 0 V, 0.1 mF Chip Capacitor between VP and VN, TA =
255C)
Figure 2. Typical Filter Performance (Nominal Conditions unless
Specified Otherwise, 50 Ohm Environment)
http://onsemi.com
4
CM1215
APPLICATION INFORMATION
Design Considerations
In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic
series inductances on the Supply/ Ground rails as well as the signal trace segment between the signal input (typically
a connector) and the ESD protection device. Refer to Figure 1, which illustrates an example of a positive ESD pulse striking
an input channel. The parasitic series inductance back to the power supply is represented by L1 and L2. The voltage VCL on
the line being protected is:
VCL = Fwd voltage drop of D1 + VSUPPLY + L1 x d(IESD) / dt+ L2 x d(IESD) / dt
where IESD is the ESD current pulse, and VSUPPLY is the positive supply voltage.
An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge
per the IEC61000−4−2 standard results in a current pulse that rises from zero to 30 Amps in 1ns. Here d(IESD)/dt can be
approximated by d(ESD)/dt, or 30/(1x10−9). So just 10 nH of series inductance (L1 and L2 combined) will lead to a 300 V
increment in VCL!
Similarly for negative ESD pulses, parasitic series inductance from the VN pin to the ground rail will lead to drastically
increased negative voltage on the line being protected.
As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected
electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the VP pin of the Protection
Array as possible, with minimum PCB trace lengths to the power supply, ground planes and between the signal input and the
ESD device to minimize stray series inductance.
Additional Information
See also ON Semiconductor Application Note, “Design Considerations for ESD Protection”, in the Applications section.
L1
POSITIVE SUPPLY
PATH OF ESD CURRENT
PULSE (IESD)
D1
C1
LINE BEING
PROTECTED
ONE
CHANNEL
D2
SYSTEM OR
CIRCUITRY
BEING
PROTECTED
CHANNEL
IMPUT
GROUND RAIL
CHASSI‘S GROUND
Figure 3. Application of Positive ESD Pulse between Input Channel and Ground
http://onsemi.com
5
CM1215
PACKAGE DIMENSIONS
SOT−23 3−Lead (TO−236AA)
CASE 419AH−01
ISSUE O
D
3X
b
L2
3
GAUGE
PLANE
E1
E
1
L
2
e
e
C
DETAIL Z
A
SEATING
PLANE
M
DIM
A
A1
b
c
D
E
E1
e
L
L2
M
c
0.05
C
A1
SEATING
PLANE
DETAIL Z
RECOMMENDED
SOLDERING FOOTPRINT*
3X
0.56
2.74
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.15 PER SIDE. DIMENSIONS D AND E1 ARE
DETERMINED AT DATUM H.
5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE.
3X
0.82
0.95
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
6
MILLIMETERS
MIN
MAX
0.75
1.17
0.05
0.15
0.30
0.50
0.08
0.20
2.80
3.05
2.10
2.64
1.20
1.40
0.95 BSC
0.40
0.60
0.25 BSC
0°
8°
CM1215
PACKAGE DIMENSIONS
SOT−143, 4 Lead
CASE 527AF−01
ISSUE A
SYMBOL
MIN
A
0.80
1.22
D
A1
0.05
0.15
e
A2
0.75
b
0.30
0.50
b2
0.76
0.89
4
3
E1
1
E
c
0.08
D
2.80
E
2.10
E1
1.20
e
2
0.40
L1
2.64
1.30
0.50
0°
A1
L1
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC TO-253.
http://onsemi.com
7
0.60
c
L
b2
1.40
8°
q
A
3.04
0.25
θ
A2
0.20
2.90
0.54 REF
L2
TOP VIEW
1.07
0.20 BSC
L
b
0.90
MAX
1.92 BSC
e1
e1
NOM
L2
CM1215
PACKAGE DIMENSIONS
SOT−23, 5 Lead
CASE 527AH−01
ISSUE O
D
E1
SYMBOL
MIN
A
0.90
A1
0.00
A2
0.90
b
0.30
0.50
c
0.08
0.22
E
0.15
1.15
D
2.90 BSC
E
2.80 BSC
1.60 BSC
e
0.95 BSC
L
MAX
1.45
E1
e
PIN #1 IDENTIFICATION
NOM
0.45
0.30
L1
0.60 REF
L2
0.25 REF
1.30
0.60
θ
0°
4°
8°
θ1
5°
10°
15°
θ2
5°
10°
15°
TOP VIEW
θ1
A2
A
θ
b
θ2
L1
A1
SIDE VIEW
L2
L
END VIEW
Notes:
(1) All dimensions in millimeters. Angles in degrees.
(2) Complies with JEDEC standard MO-178.
http://onsemi.com
8
c
CM1215
PACKAGE DIMENSIONS
SOT−23, 6 Lead
CASE 527AJ−01
ISSUE A
D
A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DATUM C IS THE SEATING PLANE.
B
6
5
4
1
2
3
E
E
GAGE
PLANE
6X
e
TOP VIEW
L2
b
0.20
SEATING
PLANE
L
M
C A
S
B
S
DETAIL A
A2
0.10 C
A1
C
SIDE VIEW
MILLIMETERS
MIN
MAX
--1.45
0.00
0.15
0.90
1.30
0.20
0.50
0.08
0.26
2.70
3.00
2.50
3.10
1.30
1.80
0.95 BSC
0.20
0.60
0.25 BSC
c
A
6X
DIM
A
A1
A2
b
c
D
E
E1
e
L
L2
DETAIL A
SEATING
PLANE
END VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
3.30
6X
0.85
6X
0.56
0.95
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
FireWire is a registered trademark of Apple Computer, Inc.
iLink is a trademark of S. J. Electro Systems, Inc.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
http://onsemi.com
9
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
CM1215/D
Similar pages