CM1213A 1, 2 and 4-Channel Low Capacitance ESD Protection Arrays Product Description The CM1213A family of diode arrays has been designed to provide ESD protection for electronic components or subsystems requiring minimal capacitive loading. These devices are ideal for protecting systems with high data and clock rates or for circuits requiring low capacitive loading. Each ESD channel consists of a pair of diodes in series which steer the positive or negative ESD current pulse to either the positive (VP) or negative (VN) supply rail. A Zener diode is embedded between VP and VN, offering two advantages. First, it protects the VCC rail against ESD strikes, and second, it eliminates the need for a bypass capacitor that would otherwise be needed for absorbing positive ESD strikes to ground. The CM1213A will protect against ESD pulses up to 8 kV per the IEC 61000−4−2 standard. These devices are particularly well−suited for protecting systems using high−speed ports such as USB 2.0, IEEE1394 (Firewire®, iLinkt), Serial ATA, DVI, HDMI and corresponding ports in removable storage, digital camcorders, DVD−RW drives and other applications where extremely low loading capacitance with ESD protection are required in a small package footprint. http://onsemi.com SOT23−3 SO SUFFIX CASE 527AG SOT23−6 SO SUFFIX CASE 527AJ • • • Note: For 6 and 8−channel Devices, See the CM1213 Datasheet Provides ESD Protection to IEC61000−4−2 Level 4 • ±8 kV Contact Discharge Low Channel Input Capacitance of 0.85 pF Typical Minimal Capacitance Change with Temperature and Voltage Channel Input Capacitance Matching of 0.02 pF Typical is Ideal for Differential Dignals Zener Diode Protects Supply Rail and Eliminates the Need for External By−pass Capacitors Each I/O Pin Can Withstand Over 1000 ESD Strikes* These Devices are Pb−Free and are RoHS Compliant Applications • USB2.0 Ports at 480 Mbps in Desktop PCs, Notebooks and Peripherals • IEEE1394 Firewire® Ports at 400 Mbps / 800 Mbps • DVI Ports, HDMI Ports in Notebooks, Set Top Boxes, Digital TVs, • • • SC70−6 S7 SUFFIX CASE 419AD MSOP−10 MR SUFFIX CASE 846AE XXXMG G XXXMG G • One, Two, and Four Channels of ESD Protection • • • SOT23−5 SO SUFFIX CASE 527AH MARKING DIAGRAM Features • SOT143 SR SUFFIX CASE 527AF LCD Displays Serial ATA Ports in Desktop PCs and Hard Disk Drives PCI Express Ports General Purpose High−Speed Data Line ESD Protection 1 1 XXX = Specific Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION Device Package Shipping† CM1213A−01SO SOT23−3 (Pb−Free) 3000/Tape & Reel CM1213A−02SR SOT143−4 3000/Tape & Reel (Pb−Free) CM1213A−02SO SOT23−5 (Pb−Free) SOT23−6 (Pb−Free) SC70−6 (Pb−Free) MSOP−10 (Pb−Free) CM1213A−04SO CM1213A−04S7 CM1213A−04MR 3000/Tape & Reel 3000/Tape & Reel 3000/Tape & Reel 4000/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. *Standard test condition is IEC61000−4−2 level 4 test circuit with each pin subjected to ±8 kV contact discharge for 1000 pulses. Discharges are timed at 1 second intervals and all 1000 strikes are completed in one continuous test run. The part is then subjected to standard production test to verify that all of the tested parameters are within spec after the 1000 strikes. © Semiconductor Components Industries, LLC, 2011 July, 2011 − Rev. 7 1 Publication Order Number: CM1213A/D CM1213A BLOCK DIAGRAM VP CH1 VN CM1213A−01SO VP CH4 CH1 VP CH3 CH2 VN CM1213A−02SR CM1213A−02SO http://onsemi.com 2 CH1 VN CH2 CM1213A−04SO CM1213A−04MR CM1213A−04S7 CM1213A PACKAGE / PINOUT DIAGRAMS Table 1. PIN DESCRIPTIONS 1−Channel, 3−Lead SOT23−3 Package (CM1213A−01SO) Top View Pin Name Type Description 1 CH1 I/O 2 VP PWR Positive voltage supply rail 3 VN GND Negative voltage supply rail CH1 (1) ESD Channel 1 D231 VP (2) 3 VN (3) 2 3−Lead SOT23−3 2−Channel, 4−Lead SOT143−4 Package (CM1213A−02SR) Pin Name Type Description 1 VN GND 2 CH1 I/O ESD Channel 3 CH2 I/O ESD Channel 4 VP PWR Negative voltage supply rail Top View Type NC − 2 VN GND 3 CH1 I/O ESD Channel 4 CH2 I/O ESD Channel 5 VP PWR 2 VP (4) 3 CH2 (3) Description No Connect Top View Negative voltage supply rail Positive voltage supply rail NC (1) 1 VN (2) 2 CH1 (3) 3 5 VP (5) 4 CH2 (4) D233 1 CH1 (2) 4 4−Lead SOT143−4 2−Channel, 5−Lead SOT23−5 Package (CM1213A−02SO) Name 1 D232 Positive voltage supply rail Pin VN (1) 5−Lead SOT23−5 4−Channel, 6−Lead SOT23−6 (CM1213A−04SO) and SC70−6 (CM1213A−04s7) Pin Name Type 1 CH1 I/O Top View Description ESD Channel VN GND CH2 I/O Negative voltage supply rail ESD Channel 4 CH3 I/O ESD Channel 5 VP PWR 6 CH4 I/O 1 VN 2 CH2 3 D38 2 3 CH1 6 CH4 5 VP 4 CH3 6−Lead SC70−6 Positive voltage supply rail ESD Channel Top View 4−Channel, 10−Lead MSOP−10 Package (CM1213A04MR) Type 1 CH1 I/O 2 NC − 3 VP PWR 4 CH2 I/O 5 NC − 6 CH3 I/O 7 NC − 8 VN GND 9 CH4 I/O 10 NC − Description ESD Channel No Connect 1 VN 2 CH2 3 6 CH4 5 VP 4 CH3 6−Lead SOT23−6 Positive voltage supply rail ESD Channel No Connect Top View ESD Channel CH1 NC VP CH2 NC No Connect Negative voltage supply rail ESD Channel 1 2 3 4 5 10 9 8 7 6 D237 Name D234 Pin CH1 NC CH4 VN NC CH3 10−Lead MSOP−10 No Connect http://onsemi.com 3 CM1213A SPECIFICATIONS Table 2. ABSOLUTE MAXIMUM RATINGS Parameter Rating Units 6.0 V Operating Temperature Range –40 to +85 °C Storage Temperature Range –65 to +150 °C (VN − 0.5) to (VP + 0.5) V Operating Supply Voltage (VP − VN) DC Voltage at any channel input Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 3. STANDARD OPERATING CONDITIONS Parameter Operating Temperature Range Package Power Rating SOT23−3, SOT143−4, SOT23−5, SOT23−6, and SC70−6 Packages MSOP−10 Package Rating Units –40 to +85 °C mW 225 400 Table 4. ELECTRICAL OPERATING CHARACTERISTICS (Note1) Symbol Parameter Conditions VP Operating Supply Voltage (VP−VN) IP Operating Supply Current (VP−VN) = 3.3 V VF Diode Forward Voltage Top Diode Bottom Diode IF = 8 mA; TA = 25°C Channel Leakage Current Min Max Units 3.3 5.5 V 8.0 mA V 0.80 0.80 0.95 0.95 TA = 25°C; VP = 5 V, VN = 0 V 0.1 1.0 mA Channel Input Capacitance At 1 MHz, VP = 3.3 V, VN = 0 V, VIN = 1.65 V (Note 2) 0.85 1.2 pF DCIN Channel Input Capacitance Matching At 1 MHz, VP = 3.3 V, VN = 0 V, VIN = 1.65 V (Note 2) 0.02 VESD ESD Protection − Peak Discharge Voltage at any channel input, in system Contact discharge per IEC 61000−4−2 standard TA = 25°C (Notes 2, 3, and 4) VCL Channel Clamp Voltage Positive Transients Negative Transients TA = 25°C, IPP = 1A, tP = 8/20 mS (Notes 2 and 4) RDYN Dynamic Resistance Positive Transients Negative Transients IPP = 1A, tP = 8/20 mS Any I/O pin to Ground (Notes 2 and 4) ILEAK CIN 0.60 0.60 Typ pF kV 1. All parameters specified at TA = –40°C to +85°C unless otherwise noted. 2. Standard IEC 61000−4−2 with CDischarge = 150 pF, RDischarge = 330 W, VP = 3.3 V, VN grounded. 3. These measurements performed with no external capacitor on VP (VP floating). http://onsemi.com 4 8 +10 –1.7 0.9 0.5 V W CM1213A PERFORMANCE INFORMATION Input Channel Capacitance Performance Curves Figure 1. Typical Variation of CIN vs. VIN (f = 1 MHz, VP = 3.3 V, VN = 0 V, 0.1 F Chip Capacitor between VP and VN, 255C) Figure 2. Typical Variation of CIN vs. Temp (f = 1 MHz, VIN = 30 mV, VP = 3.3 V, VN = 0 V, 0.1 F Chip Capacitor between VP and VN) http://onsemi.com 5 CM1213A PERFORMANCE INFORMATION (Cont’d) Typical Filter Performance (nominal conditions unless specified otherwise, 50 Ohm Environment) Figure 3. Insertion Loss (S21) vs. Frequency (0 V DC Bias, VP=3.3 V) Figure 4. Insertion Loss (S21) vs. Frequency (2.5 V DC Bias, VP=3.3 V) http://onsemi.com 6 CM1213A APPLICATION INFORMATION Design Considerations In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic series inductances on the Supply/Ground rails as well as the signal trace segment between the signal input (typically a connector) and the ESD protection device. Refer to Application of Positive ESD Pulse between Input Channel and Ground, which illustrates an example of a positive ESD pulse striking an input channel. The parasitic series inductance back to the power supply is represented by L1 and L2. The voltage VCL on the line being protected is: VCL = Fwd Voltage Drop of D1 + VSUPPLY + L1 x d(IESD) / dt + L2 x d(IESD) / dt where IESD is the ESD current pulse, and VSUPPLY is the positive supply voltage. An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge per the IEC61000−4−2 standard results in a current pulse that rises from zero to 30 Amps in 1 ns. Here d(IESD)/dt can be approximated by DIESD/Dt, or 30/(1x10−9). So just 10 nH of series inductance (L1 and L2 combined) will lead to a 300 V increment in VCL! Similarly for negative ESD pulses, parasitic series inductance from the VN pin to the ground rail will lead to drastically increased negative voltage on the line being protected. The CM1213A has an integrated Zener diode between VP and VN. This greatly reduces the effect of supply rail inductance L2 on VCL by clamping VP at the breakdown voltage of the Zener diode. However, for the lowest possible VCL, especially when VP is biased at a voltage significantly below the Zener breakdown voltage, it is recommended that a 0.22 mF ceramic chip capacitor be connected between VP and the ground plane. As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the VP pin of the Protection Array as possible, with minimum PCB trace lengths to the power supply, ground planes and between the signal input and the ESD device to minimize stray series inductance. Additional Information See also ON Semiconductor Application Note “Design Considerations for ESD Protection”, in the Applications section. L2 VP ÇÇÇÇÇÇ ÇÇÇÇÇÇ ÇÇÇÇÇÇ ÇÇÇÇÇÇ ÇÇÇÇÇÇ ÇÇÇÇÇÇ D1 0.22 mF ONE CHANNEL D2 OF CM1213 VN POSITIVE SUPPLY RAIL VCC PATH OF ESD CURRENT PULSE IESO LINE BEING PROTECTED L1 CHANNEL INPUT 25 A 0A ÇÇÇÇÇÇ ÇÇÇÇÇÇ ÇÇÇÇÇÇ ÇÇÇÇÇÇ ÇÇÇÇÇÇ SYSTEM OR CIRCUITRY BEING PROTECTED VCL GROUND RAIL CHASSIS GROUND Figure 5. Application of Positive ESD Pulse between Input Channel and Ground http://onsemi.com 7 CM1213A PACKAGE DIMENSIONS SOT−23 3−Lead CASE 527AG−01 ISSUE O MIN SYMBOL D 3 E1 1 E 2 e MAX A 0.89 1.12 A1 0.013 0.10 b 0.37 0.50 c 0.085 0.18 D 2.80 3.04 E 2.10 2.64 E1 1.20 1.40 e 0.95 BSC e1 1.90 BSC L 0.40 REF e1 L1 TOP VIEW θ A NOM 0.54 REF 0º 8º q b L1 A1 SIDE VIEW L END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC TO-236. http://onsemi.com 8 c CM1213A PACKAGE DIMENSIONS SOT−143, 4 Lead CASE 527AF−01 ISSUE A SYMBOL MIN NOM MAX A 0.80 1.22 D A1 0.05 0.15 e A2 0.75 4 3 E1 1 E 2 e1 TOP VIEW b 0.30 0.50 0.76 0.89 c 0.08 0.20 D 2.80 E 2.10 E1 1.20 2.90 1.30 e 1.92 BSC 0.20 BSC 0.40 0.50 L1 0.54 REF L2 0.25 0° A1 L1 SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC TO-253. http://onsemi.com 9 0.60 c L b2 1.40 8° q A 3.04 2.64 e1 θ A2 1.07 b2 L b 0.90 L2 CM1213A PACKAGE DIMENSIONS SOT−23, 5 Lead CASE 527AH−01 ISSUE O D E1 SYMBOL MIN A 0.90 A1 0.00 A2 0.90 b 0.30 c 0.08 E NOM 1.45 0.15 1.15 0.22 D 2.90 BSC E 2.80 BSC 1.60 BSC e 0.95 BSC L 0.45 0.30 L1 PIN #1 IDENTIFICATION 1.30 0.50 E1 e MAX 0.60 0.60 REF L2 0.25 REF θ 0° 4° 8° θ1 5° 10° 15° θ2 5° 10° 15° TOP VIEW θ1 A2 A θ b θ2 L1 A1 SIDE VIEW L2 L END VIEW Notes: (1) All dimensions in millimeters. Angles in degrees. (2) Complies with JEDEC standard MO-178. http://onsemi.com 10 c CM1213A PACKAGE DIMENSIONS SOT−23, 6 Lead CASE 527AJ−01 ISSUE A D A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DATUM C IS THE SEATING PLANE. B 6 5 4 1 2 3 E E GAGE PLANE 6X e TOP VIEW L2 b 0.20 SEATING PLANE L C A M S B S DETAIL A A2 c A 6X 0.10 C A1 SIDE VIEW C SEATING PLANE DETAIL A END VIEW RECOMMENDED SOLDERING FOOTPRINT* 3.30 6X 0.85 6X 0.56 0.95 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 11 DIM A A1 A2 b c D E E1 e L L2 MILLIMETERS MIN MAX --1.45 0.00 0.15 0.90 1.30 0.20 0.50 0.08 0.26 2.70 3.00 2.50 3.10 1.30 1.80 0.95 BSC 0.20 0.60 0.25 BSC CM1213A PACKAGE DIMENSIONS SC−88 (SC−70 6 Lead), 1.25x2 CASE 419AD−01 ISSUE A D e e E1 E SYMBOL MIN A 0.80 MAX 1.10 A1 0.00 0.10 A2 0.80 1.00 b 0.15 0.30 c 0.10 0.18 D 1.80 2.00 2.20 E 1.80 2.10 2.40 E1 1.15 1.25 1.35 0.65 BSC e L TOP VIEW NOM 0.26 0.36 L1 0.42 REF L2 0.15 BSC 0.46 θ 0º 8º θ1 4º 10º q1 A2 A q q1 b L L1 A1 SIDE VIEW c END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-203. http://onsemi.com 12 L2 CM1213A PACKAGE DIMENSIONS MSOP 10, 3x3 CASE 846AE−01 ISSUE O SYMBOL MIN NOM 1.10 A E E1 MAX A1 0.00 0.05 0.15 A2 0.75 0.85 0.95 b 0.17 0.27 c 0.13 0.23 D 2.90 3.00 3.10 E 4.75 4.90 5.05 E1 2.90 3.00 3.10 0.50 BSC e L 0.40 L1 0.80 0.25 BSC L2 θ 0.60 0.95 REF 0º 8º DETAIL A TOP VIEW D A END VIEW A2 A1 c e b q SIDE VIEW L2 Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-187. L L1 DETAIL A FireWire is a registered trademark of Apple Computer, Inc. iLink is a trademark of S. J. Electro Systems, Inc. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 13 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative CM1213A/D