AT73C204 - Mature

Features
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300 mA/1.9V/2.5V DC to DC for Co-processor Core
80 mA/2.8V Dual-mode LDO for Memories (LDO1)
130 mA/2.7V/2.8V LDO for Camera Module (LDO2)
130 mA/2.8V LDO for Analog Section Supply of Audio Stereo Codec (LDO6)
10 mA/1.8V/2.8V LDO for Digital Section Supply of Audio Stereo Codec (LDO7)
130 mA/2.8V LDO for Analog Section Supply of Bluetooth® Module (LDO4)
130 mA/2.8V LDO for Digital Section Supply of Bluetooth® Module (LDO5)
2 mA/2.4V/2.7V LDO for Low-power Device Control (LDO3)
Open Drain Switch
Three-channel Level Shifters
LED Driver
0.5 mA/1.5V Bufferized Voltage Reference
Power Management Start-up Controller and Reset Generation
Over- and Under-voltage Protections
Over-temperature Protection
Shutdown, Sleep and Enable Modes
Straightforward and Easy Interfacing to any Baseband Controller
Small 5 mm x 5 mm, 49-ball BGA Package
Power
Management for
Mobiles (PM)
AT73C204
Description
The AT73C204 device provides an integrated power management solution for the addon multimedia features in new-generation mobile phones. These features include a
camera module, sound system for polyphonic ringing tones, memory module for
downloaded MP3 files, Bluetooth module for cordless headset, etc. The most common
approach to the IC architecture of these new-generation mobile phones is a baseband
processor for the basic telephony functions and a separate co-processor for the multimedia features. Atmel proposes the AT73C202 for power management of the
baseband processor and RF elements, and the AT73C204 for power management of
the multimedia features.
The AT73C204 is suitable for any telecommunications standard: GSM/GPRS, PDS,
CDMA, CDMA2000, WCDMA or UMTS. It is packaged in a small form-factor 49-ball
5 mm x 5 mm BGA package.
6014A–PMGMT–10/03
Functional Block Diagram
Figure 1. AT73C204 Functional Block Diagram
E1
VINF
D5
C1
CE
RESB
Reset
Generator
LEDI
LED Driver
LEDO
F6
C2
LX
G6
D4
G5
VINA
DC-DC
Converter
1.9V/2.5V
300mA
DVA
DM
F7
VOUT0
GNDA
G4
G7
Oscillator
A5
B5
C7
E5
B7
C5
B3
A4
B3
A4
VOUT1
VINB
LDO1
2.8V/130mA
EN2
CREF
GNDG
VOUT2
VR
LDO2
2.7V/2.8V/130mA
VREF
SWI
SWO
GNDD
LDO3
Open Drain
Switch
2.4V/2.7V/2mA
LDO4
2.8V/130mA
VINC
EN4
VOUT3
GNDB
VOUT4
VOUT5
C4
D7
E6
G1
G3
F4
E4
F3
G2
LDO5
2.8V/130mA
EN5
VIND
EN6
GNDC
LDO6
2.8V/130mA
VOUT6
LDO7
1.8V/2.8V/10mA
VOUT7
B4
A6
A7
B1
A1
A2
E7
VINE
EN7
E3
DVB
LSI1
LSO1
Three-channel
Level Shifter
LSI2
LSO2
LSO3
LSI3
D6
2
B6
F5
C3
D2
D3
GNDE
D1
F1
F2
E2
GNDF
C6
AT73C204
6014A–PMGMT–10/03
AT73C204
Pin Description
Table 1. AT73C204 Pin Description
Signal
Ball
Type
Description
LEDI
C1
I
LED driver input
LEDO
C2
O
LED driver output
VINF
E1
Power Supply
Input voltage
Power On Block
CE
D5
I
Chip Enable
GNDF
C6
Ground
RES-B
F6
O
GNDG
E5
Ground
Ground
Reset open collector output
Ground
Baseband Supply Block
VINA
G6
Power Supply
Input supply for DC-DC converter
LX
F7
O
DC-DC converter Output Inductor
DM
G5
I
Low-power/Full-power selector
VOUTO
G4
O
DC-DC converter output
GNDA
G7
Ground
VINB
A5
EN2
B5
I
Enable LDO2
VOUT2
B4
O
LDO2 output voltage
GNDB
A7
Ground
VOUT1
B6
O
LDO1 output voltage
VREF
B7
O
Bufferized voltage reference
VOUT3
A6
O
LDO3 output voltage
Ground of DC-DC Converter
Input supply for LDO1, LDO2, LDO3
Ground for LDO1, LDO2, LDO3
RF Supply Block
VINC
A3
Power Supply
Input supply for LDO4, LDO5
EN4
B2
I
Enable LDO4
EN5
C4
I
Enable LDO5
VOUT4
B1
O
LDO4 output voltage
GNDC
A2
Ground
VOUT5
A1
O
Ground for LDO4, LDO5
LDO5 output voltage
Vibrator and Buzzer Driver Block
VIND
D7
Power Supply
LDO6 input supply
EN6
E6
I
Enable LDO6
VOUT6
E7
O
LDO6 output voltage
SWI
C5
I
Open drain enable
SWO
B3
O
Open drain output
3
6014A–PMGMT–10/03
Table 1. AT73C204 Pin Description (Continued)
Signal
Ball
Type
Description
GNDD
A4
Ground
Open drain ground
SIM Interface Block
VINE
G1
Power Supply
LDO7 input supply
EN7
G3
I
Enable LDO7
DVB
F4
I
Dual-voltage setting on LDO7
LSI1
E4
I
Channel 1 level shifter input
LSI2
F3
I
Channel 2 level shifter input
LSI3
G2
IO
Channel 3 level shifter input
VOUT7
E3
O
LDO7 output voltage
LSO1
F1
O
Channel 1 level shifter output
LSO2
F2
O
Channel 2 level shifter output
LSO3
E2
IO
Channel 3 level shifter output
Miscellaneous
CREF
C7
IO
Band gap decoupling
GNDE
D1
Ground
DVA
D4
I
NC
D2
NC
D3
NC
C3
NC
D6
Digital ground
Dual-voltage setting for DC-DC, LDO2, LDO3
Figure 2. AT73C204 Pin Configuration in 49-ball BGA Package
1
2
3
4
5
6
7
VOUT5
GNDC
VINC
GNDD
VINB
VOUT3
GNDB
VOUT4
EN4
SWO
VOUT2
EN2
VOUT1
VREF
LEDI
LED0
NC
EN5
SWI
GNDF
CREF
GNDE
NC
NC
DVA
CE
NC
VIND
VINF
LSO3
VOUT7
LSI1
GNDG
EN6
VOUT6
LSO1
LSO2
LSI2
DVB
NC
RESB
LX
VINE
LSI3
EN7
VOUT0
DM
VINA
GNDA
A
B
C
D
E
F
G
4
AT73C204
6014A–PMGMT–10/03
AT73C204
Application Schematic
Figure 3. AT73C204 Application Schematic
Application
Processor
VBAT
E1
VINF
Main
Control
Unit
VBAT
CE
C1
LEDI
G6
VINA
D4
DVA
G5
DM
Reset
Generator
LED Driver
DC-DC
Converter
1.9V/2.5V
300mA
RESB
F6
LEDO
C2 D1
LX
F7 L1
VOUT0
G4
GNDA
G7
VOUT1
B6
R1
C1
VBAT
C2
Oscillator
C11
A5
C10
Power
Device
D5
VINB
B5
EN2
C7
CREF
E5
B7
GNDG
C5
SWI
B3
SWO
LDO1
2.8V/130mA
VOUT2
VR
A4
GNDD
A3
VINC
B2
EN4
B4
LDO2
2.7V/2.8V/130mA
VREF
LDO3
Open Drain
Switch
2.4V/2.7V/2mA
Memory Module
C3
Camera Module
C4
VOUT3
GNDB
A6
VOUT4
B1
A7
Low-power Device
C5
e.g. Buzzer
VOUT0
or
VOUT1
C4
EN5
D7
VIND
E6
EN6
G1
VINE
G3
EN7
F4
DVB
E4
LSI1
F3
LSI2
G2
LSI3
LDO4
2.8V/130mA
A1
GNDC
A2
LDO6
2.8V/130mA
VOUT6
E7
LDO7
1.8V/2.8V/10mA
VOUT7
WLAN Module
C7
MP3 Player Module
C8
E3
Audio Codec
C9
Three-channel
Level Shifter
GNDE
D6
VOUT5
LDO5
2.8V/130mA
Bluetooth Module
C6
F5
C3
D2
D3
D1
LSO1
F1
LSO2
F2
LSO3
E2
Interface
GNDF
C6
5
6014A–PMGMT–10/03
External Components Specifications
Table 2. External Component Specifications
6
Symbol
Parameters
R1
4.7 kΩ, 1/8 W, 0603
C1, C3, C4, C5, C6, C7, C8
2.2 µF - X5R 6.3V/10%, 0603
C2
22 µF Tantale R, TYPEA
C9
220 nF - X5R 10V/10%, 0603
C10
10 nF - X5R 10V/10%, 0402
C11
10 µF - X5R 6.3V/10%
L1
10 µH
D1
HSMH - C670
AT73C204
6014A–PMGMT–10/03
AT73C204
Functional Description
300 mA/1.9V/2.5V DC-toDC Converter for
Co-processor Core
This DC-to-DC converter is a synchronous mode DC-to-DC “buck”-switched regulator
using fixed- frequency architecture (PWM) and capable of providing 300 mA of continuous current. It has two levels of voltage programming for the co-processor core (1.9V or
2.5V). The operating supply range is from 3.1V to 4.2V, making it suitable for Li-Ion, Lipolymer or Ni-MH battery applications. This DC-to-DC converter is based on the pulse
width modulation architecture to control the noise perturbation for switching noise sensitive applications (GSM). The operating frequency is set to 900 KHz using an internal
clock, allowing the use of small surface inductor and moderate output voltage ripple.
The controller consists of a reference ramp generator, a feedback comparator, the logic
driver used to drive the internal switches, the feedback circuits used to manage the different modes of operation and the over-current protection circuits. An economic mode
has been defined to reduce quiescent current. A low-dropout voltage regulator in parallel to the DC-to-DC converter minimizes standby current consumption during standby
mode.
Figure 4. Dual-power DC-to-DC Converter
DC-to-DC Buck
1.9V or 2.5V
300 mA
Internal FET
VBAT
DM
L
VOUT0
LDO
1.9V or 2.5V
10 mA
Low Power
C
Low undershoot voltage is expected when going from PWM to LDO mode and viceversa. The circuit is designed in order to avoid any spikes when transition between two
modes is enabled.
Figure 5. Low-power/Full-power DC-to-DC Converter Transition
VOUT0
DM
VOUT0
High Power
Low Power
DM
High Power
Low Power
7
6014A–PMGMT–10/03
Figure 6 shows typical efficiency levels of the DC-to-DC converter for several input
voltages.
Figure 6. DC-to-DC Converter with 1.9V Target Typical Case(1)
100
Efficiency (%)
95
90
85
VIN=3.1V
80
VIN=3.6V
75
VIN=4.2V
70
0
50
100
150
200
250
300
350
400
Load Current (m A)
Note:
LDO1, LDO3, LDO4,
LDO5
1. L = 10 µH, ESR = 0.2 Ohm, c = 22 µF, @ESR = 0.1 Ohm
The PSRR measures the degree of immunization against voltage fluctuations achieved
by a regulator. An example of its importance is in the case of a GSM phone when the
antenna switch activates the RF power amplifier (PA). This causes a current peak of up
to 2A on the battery, with an important spike on the battery voltage. The voltage regulator must filter or attenuate this spike.
Figure 7. Functional Diagram of LDO Single Mode
VBAT
VINT
ON
ON
IBIAS
VBG
ON
Pass
Device
VOUT
GND
GND
VOUTS
ON
Current
Sensing and
Limiter
R1
GND
R2
ON
GND
8
AT73C204
6014A–PMGMT–10/03
AT73C204
Figure 8 shows the Power Supply Rejection Ratio as functions of frequency and battery
voltage. If a noise signal occurs at 1 kHz when the battery voltage is at 3V, the noise will
be attenuated by 70 dB (divided by more than 3000) at the output of the regulator. Consequently, a 2V spike on the battery is attenuated to less than 1 mV, which is low
enough to avoid any risk of malfunction by a device supplied by the regulator.
Figure 8. Power Supply Rejection Ratio in Function of Frequency and Battery Voltage
P o w e r S u p p ly R e je ctio n Ra tio a t F u ll L o a d
P o w e r S u p p ly R e je ctio n R a ti o a t F u ll L o a d
ve rsu s B a tte ry V o lta g e
10
100
1000
10000
100000
3.0
-30
-35
4.5
5.0
5.5
-50
-45
-60
-50
-55
P S RR [d B]
PSRR [ d B]
4.0
-40
V B A T = 3V
-40
V B A T = 4.25V
-60
-65
3.5
-30
V B A T = 5.5V
-70
-80
F req = 1 k Hz
-90
F req = 20 k Hz
F req = 100 k Hz
-100
-70
-110
-75
F req = 100 Hz
-120
-80
B a tte ry V o lta g e [V ]
Fr e q [ Hz ]
LDO2, LDO6
The first approach to reducing standby current is to decrease the standby current inside
the regulators themselves. Atmel achieves this by implementing a dual mode architecture where two output transistors are used in parallel as switches in the regulation loop.
Figure 9 illustrates this architecture.
Figure 9. Functional Diagram of LDO Dual Mode
VBAT
ON
LP
V BG
ON
LP
V BG
ON
ON
GND
ON
LP
VOUT
Current Sensing
and Limiting
GND
GND
VOUTS
R1
R2
ON
IBIAS
ON, LP
GND
GND
9
6014A–PMGMT–10/03
In Figure 9, the left-hand output transistor is sized large enough for the required output
current under full load, for example, 100 mA. In order to achieve a sufficient margin of
stability, the current sensing block uses a bias cell where the current consumption is
linked to the required output current. The higher the output current, the higher the bias
current needed to stabilize the loop.
The right-hand output transistor delivers a very small output current, typically less than 1
mA, sufficient only to maintain the output voltage with enough current to cover the leakage current of the supplied device. This requires a much smaller bias current and,
consequently, a smaller standby current inside the regulator.
LDO7
This regulator has extremely low quiescent current and is suited where power supply is
enabled almost all the time. Typical use could be the supply of back-up battery.
Temperature Sensor
The temperature sensor voltage output is a linear function of temperature.
The temperature seen by the sensor is directly related to the chip activity and the power
internally dissipated. To get a good indication of the ambient temperature, the software
must take into account this offset.
Three-channel Level
Shifters
This block provides a DC-to-DC or Memory Card level shifter and specific ESD protections. Signals are level-shifted on the LDO2 supply, allowing dual-voltage option: 1.8V
or 2.8V. If the memory type is Subscriber Identity Module (SIM) Card, level shifters are
compliant with ETSI GSM11.12 & 11.18.
Absolute Maximum Ratings
Operating Temperature (Industrial)............... -40°C to +85°C
Storage Temperature ................................. -55°C to + 150°C
Power Supply Input
VINA, VINB,...,VINF ............................................ -0.3V to +6.5V
I/O Input (all except to power supply........ -0.3V to VMAX+0.3
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or other
conditions beyond those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Recommended Operating Conditions
Table 3. Recommended Operating Conditions
Parameter
Conditions
Operating Temperature
Power Supply Input
10
VINA, VINB,..., VINF
Min
Maw
Unit
-20
85
°C
3.0
4.5
V
AT73C204
6014A–PMGMT–10/03
AT73C204
Electrical Characteristics
VOUT0
Table 4. VOUT0 Electrical Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VINA
Operating Supply Voltage
5.5
V
VOUT0
Output Voltage
Full-power
(DVA = 0, DM = 0)
1.80
1.90
2.0
V
VOUT0
Output Voltage
Full-power
(DVA = 1, DM = 0)
2.45
2.50
2.55
V
IOUT0
Output Current
Full-power
(DM = 0)
300
400
mA
ISD
Shutdown Current
0.1
1
µA
EFF
Efficiency
IOUT = 10 mA to 200 mA @1.9V
90
%
∆VDCLD
Static Load Regulation
Full-power Mode (10% to 90% of
IOUT(MAX)
50
mV
∆VTRLD
Transient Load Regulation
Full-power Mode (10% to 90% of
IOUT(MAX),TR = TF = 5µs
50
mV
∆VDCLE
Static Line Regulation
Full-power Mode (10% to 90% of
IOUT(MAX), 3.2V to 4.2V)
20
mV
∆VTRLE
Transient Line Regulation
Full-power Mode (10% to 90% of
IOUT(MAX), 3.2V to 4.2V)
35
mV
VOUT0
Output Voltage
Low-power Mode
(DVA = 0, DM = 1)
1.75
1.85
1.95
V
VOUT0
Output Voltage
Low-power Mode
(DVA = 1, DM = 1)
2.35
2.40
2.45
V
IOUT0
Output Current
Low-power Mode (DM = 1)
10
mA
VDROP
Dropout Voltage
Low-power Mode (DM = 1)
400
mV
IQC
Quiescent Current
Low-power Mode (DM = 1)
14
µA
∆VDCLD
Static Load Regulation
Low-power Mode (0 to 10 mA)
50
mV
∆VTRLD
Transient Load Regulation
Low-power Mode (0 to 10 mA),
TR = TF = 5µs
10
mV
∆VDCLE
Static Line Regulation
Low-power Mode (3.2V to 4.2V)
8
mV
∆VTRLE
transient Line Regulation
Low-power Mode (3.2V to 4.2V)
15
mV
PSRR
Ripple Rejection
Low-power Mode up to 1 KHz
∆VLPFP
Overshoot Voltage
Voltage drop from Low-power to
Full-power
∆VFPLP
Undershoot Voltage
Voltage drop from Low-power to
Full-power
3
11
40
45
0
-15
0
dB
10
mV
mV
11
6014A–PMGMT–10/03
LDO2
Table 5. LDO2 Electrical Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VINB
Operating Supply Voltage
5.5
V
VOUT2
Output Voltage
DVA = 0
2.65
2.70
2.75
V
VOUT2
Output Voltage
DVA = 1
2.75
2.80
2.85
V
VINT
Internal Supply Voltage
2.6
V
IOUT2
Output Current
80
130
mA
IQC
Quiescent Current
195
236
µA
DVOUT
Line Regulation
VBAT: 3V to 3.4V, IOUT = 130 mA
3
mV
DVPEAK
Line Regulation Transient
Same as above, TR = TF = 5 µs
4
mV
DVOUT
Load Regulation
10% - 90% IOUT, VBAT = 3V
10
mV
10% - 90%IOUT, VBAT = 5.0V
15
mV
10% - 90% IOUT, VBAT = 5.5V
15
mV
3
2.4
DVPEAK
Load Regulation Transient
Same as above, TR = TF = 5 µs
15
mV
PSRR
Ripple rejection
F = 217Hz – VBAT = 3.6V
70
dB
VN
Output Noise
BW: 10 Hz to 100 kHz
29
µVRMS
TR
Rise Time
100% IOUT, 10% - 90% VOUT
ISD
Shut Down Current
12
50
µs
1
µA
AT73C204
6014A–PMGMT–10/03
AT73C204
LDO1
Table 6. LDO1 Electrical Characteristics
Symbol
Parameter
Conditions
Min
VINB
Operating Supply Voltage
VOUT1
Output Voltage Full Power Mode
IOUT1
Output Current Full Power Mode
IOUT
Output Current Low Power Mode
IQC
Quiescent Current FP Mode
25
IQC
Quiescent Current LP Mode
9.75
DVOUT
Line Regulation FP Mode
DVPEAK
Typ
Max
Unit
5.5
V
2.80
2.86
V
50
80
mA
10
mA
30
36
µA
11.5
13.75
µA
1
mV
Line Regulation Transient FP Mode VBAT: from 5V to 5.4V and from 3.4V
to 3V, IOUT = 80 mA,
TR = TF = 5 µs
3
mV
DVOUT
Line Regulation LP Mode
3
mV
DVPEAK
Line Regulation Transient LP Mode VBAT: from 5V to 5.4V and from 3.4V
to 3V, IOUT = 5 mA,
TR = TF = 5 µs
4
mV
DVOUT
Load Regulation FP Mode
3
(4 at 5.5V)
mV
DVPEAK
Load Regulation Transient FP Mode From 0 to IOUT(MAX) and from 90% to
10% IOUT(MAX), TR = TF = 5 µs,
VBAT = 3.4V
23
mV
DVOUT
Load Regulation LP Mode
From 0 to 80mA and from 90% to
10% IOUT(MAX), VBAT = 3.4V
5
(10 at 5.5V)
mV
PSRR
Ripple Rejection
F = 217Hz
VN
Output Noise FP mode
BW: 10 Hz to 100 kHz
80
µVRMS
VN
Output Noise LP Mode
BW: 10 Hz to 100 kHz
300
µVRMS
TR
Rise Time FP
IOUT = IOUT(MAX)
70
130
µs
TR
Rise Time LP
IOUT = IOUT(MAX)
50
170
µs
ISD
Shut Down Current
1
µA
VBAT
Operating Supply Voltage
5.5
V
VSAUV
Internal Operating Supply Voltage
2.8
2.86
V
ISC
Short Circuit Current
50
80
mA
3
2.74
VBAT: 3.4V to 3V, IOUT = 80 mA
VBAT: 3.4V to 3V, IOUT = 5 mA
From 0 to 80mA and from 90% to
10% IOUT(MAX), VBAT = 3.4V
40
45
3
2.74
dB
13
6014A–PMGMT–10/03
LDO3
Table 7. LDO3 Electrical Characteristics
Symbol
Parameter
Conditions
Min
VINB
Operating Supply Voltage
VOUT3
Output Voltage
BB1 = 0
2.4
VOUT3
Output Voltage
BB1 = 1
2.65
IOUT3
Output Current
VDROP
Dropout Voltage
IQC
Quiescent Current
PSRR
Ripple Rejection
TR
Rise Time
Typ
Max
Unit
5.5
V
2.45
2.50
V
2.70
2.75
V
2
5
mA
50
mV
9.7
µA
3
4.8
6.6
40
110
dB
320
µs
Buffered Voltage Reference
Table 8. Buffered Voltage Reference Electrical Characteristics
Symbol
Parameter
VREF
Output Voltage
IREF
Min
Typ
Max
Unit
1.45
1.50
1.55
V
Output Current
0.5
mA
VDROP
Dropout Voltage
50
mV
IQC
Quiescent Current
6.6
9.7
µA
ISD
Shutdown Current
0.1
1
µA
PSRR
Ripple Rejection
40
TR
Rise time
14
Conditions
4.8
110
dB
320
µs
AT73C204
6014A–PMGMT–10/03
AT73C204
LDO4, LDO5, LDO6
Table 9. LDO4, LDO5, LDO6 Electrical Characteristics
Symbol
Parameter
Conditions
Min
VINC
Operating Supply Voltage
VINT
Operating Internal Supply Voltage
2.4
VOUT
Output Voltage
2.74
IOUT
Typ
Max
Unit
5.5
V
2.5
2.6
V
2.8
2.86
V
Output Current
80
130
mA
IQC
Quiescent Current
195
236
µA
DVOUT
Line Regulation
VBAT: 3V to 3.4V, IOUT = 130 mA
3
2
mV
DVPEAK
Line Regulation Transient
Same as above, TR = TF = 5 µs
4
2.85
mV
DVOUT
Load Regulation
10% - 90% IOUT, VBAT = 3V
10
1
mV
10% - 90% IOUT, VBAT = 5.0V
15
1
mV
10% - 90% IOUT, VBAT = 5.5V
15
1
mV
1.2
2.4
mV
3
DVPEAK
Load Regulation Transient
Same as above, TR = TF = 5 µs
PSRR
Ripple Rejection
F=217Hz – VBAT = 3.6V
VN
Output Noise
BW: 10 Hz to 100 kHz
TR
Rise Time
100% IOUT, 10% - 90% VOUT
ISD
Shut Down Current
70
73
29
dB
37
µVRMS
50
µs
1
µA
Max
Unit
0.4
V
Open Drain Switch
Table 10. Open Drain Switch Electrical Characteristics
Symbol
Parameter
Conditions
Min
Typ
VOL
Low Output Voltage
IOL = 100 mA
IOL
Low Output Current
100
mA
TON
Turn-on Time
10
µs
TOFF
Turn-off Time
10
µs
15
6014A–PMGMT–10/03
LDO7
Conditions are VINE = 1.8V or 2.8V, tA = -40°C to +85°C, CDVCC = 100 nF, CSIM-VCC = 100 nF
Table 11. LDO7 Electrical Characteristics.
Symbol
Parameter
Conditions
Min
VINE
Operating Supply Voltage
VOUT0 or VOUT1
1.65
VOUT7
Output Voltage
IOUT7 < 10 mA
EN7 = 1
DVB = 1
VOUT7
Output Voltage
IOUT7 < 10mA
EN7 = 1
DVB = 0
ISD
Total Shutdown Current
EN7 = 0
IQC
Quiescent Current
Low-power Mode
IQC
Quiescent Current
Full-power Mode
IOUT7
Output Current
ISC
Short Circuit Current
16
Typ
Max
Unit
1.71
1.8
1.89
V
2.74
2.8
2.86
V
0.1
1
µA
8
9.5
µA
60
µA
10
mA
40
mA
AT73C204
6014A–PMGMT–10/03
AT73C204
Packaging Information
Figure 10. Mechanical Package Drawing for 49-ball Ball Grid Array
0.65
0.26
0.30
0.53
17
6014A–PMGMT–10/03
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6014A–PMGMT–10/03
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