ATWILC1000-MR1100A - Complete

ATWILC1000-MR1100A DATASHEET
IEEE 802.11 b/g/n Link Controller SoC
Datasheet
Description
The Atmel® ATWILC1000-MR1100A is a low-power consumption 802.11 b/g/n
IoT (Internet of Things) module which is specifically optimized for low power IoT
applications. The highly integrated module features small form factor (14.48 x
13.46 x 3.35mm) while fully integrating Power Amplifier, LNA, Switch, and Power
Management. With seamless roaming capabilities and advanced security, it
could be interoperable with various vendors’ 802.11b/g/n Access Points in
wireless LAN. The module provides SPI and SDIO to interface to host controller.
Features
 IEEE® 802.11 b/g/n 20MHz (1x1) solution
 Single spatial stream in 2.4GHz ISM band
 Integrated PA and T/R Switch
 Superior Sensitivity and Range via advanced PHY signal processing
 Advanced Equalization and Channel Estimation
 Advanced Carrier and Timing Synchronization
 Wi-Fi Direct® and Soft-AP support
 Supports IEEE 802.11 WEP, WPA, WPA2 Security
 Supports China WAPI security
 Superior MAC throughput via hardware accelerated two-level A-MSDU/AMPDU frame aggregation and block acknowledgement
 On-chip memory management engine to reduce host load
 SPI, SDIO, UART, and I2C host interfaces
 2-/3-wire Bluetooth® coexistence interface
 Operating temperature range of -40 to +85°C
 Power save modes:
– <1µA Deep Power Down mode typical @3.3V I/O
– 280µA Doze mode with chip settings preserved (used for beacon monitoring)
– On-chip low power sleep oscillator
– Fast host wake-up from Doze mode by a pin or host I/O transaction
Atmel-42432A-WILC1000-MR1100PA-SmartConnect-Datasheet_032015
Ta bl e of Conte nts
1
Ordering Information and Module Marking ................................................................ 4
2
Block Diagram ............................................................................................................. 5
3
Pin-out and Package Information ............................................................................... 5
3.1
3.2
4
Electrical Specifications ............................................................................................. 9
4.1
4.2
5
6.2
6.3
7.2
7.3
7.4
7.5
SPI Interface ....................................................................................................................................... 14
7.1.1 Overview................................................................................................................................. 14
7.1.2 SPI Timing .............................................................................................................................. 14
UART Interface ................................................................................................................................... 16
SDIO Interface .................................................................................................................................... 16
7.3.1 Overview................................................................................................................................. 16
7.3.2 Features ................................................................................................................................. 17
7.3.3 SDIO Timing ........................................................................................................................... 17
I2C Interface ........................................................................................................................................ 18
7.4.1 Overview................................................................................................................................. 18
7.4.2 I2C Timing ............................................................................................................................... 18
Wi-Fi/Bluetooth Coexistence ............................................................................................................... 19
Description of Device States ............................................................................................................... 20
Controlling the Device States .............................................................................................................. 20
Restrictions for Power States .............................................................................................................. 20
Power-Up/Down Sequence ................................................................................................................. 20
Digital I/O Pin Behavior during Power-up Sequences ......................................................................... 22
Notes on Interfacing to the ATWILC1000-MR1100 .................................................. 23
9.1
2
.............................................................................................................................................. 11
Features ................................................................................................................................. 11
Description.............................................................................................................................. 11
.............................................................................................................................................. 12
Features ................................................................................................................................. 12
Description.............................................................................................................................. 12
.............................................................................................................................................. 12
Power Consumption .................................................................................................. 20
8.1
8.2
8.3
8.4
8.5
9
MAC
6.1.1
6.1.2
PHY
6.2.1
6.2.2
Radio
External Interfaces .................................................................................................... 14
7.1
8
Processor ............................................................................................................................................ 10
Memory Subsystem............................................................................................................................. 10
Non-Volatile Memory (eFuse) ............................................................................................................. 10
WLAN Subsystem ...................................................................................................... 11
6.1
7
Absolute Ratings ................................................................................................................................... 9
Recommended Operating Ratings ........................................................................................................ 9
CPU and Memory Subsystems ................................................................................. 10
5.1
5.2
5.3
6
Pin Description ...................................................................................................................................... 5
Module Outline Drawings ...................................................................................................................... 8
Programmable Pull-up Resistors ......................................................................................................... 23
ATWILC1000-MR1100A
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10 Recommended Footprint .......................................................................................... 23
11 RF Performance Placement Guidelines ................................................................... 24
12 Recommended Reflow Profile .................................................................................. 25
13 Module Schematics ................................................................................................... 26
14 Module Bill of Materials (BOM) ................................................................................. 27
15 Application Reference Design .................................................................................. 28
16 Reference Documentation and Support................................................................... 30
16.1 Reference Documents......................................................................................................................... 30
17 Revision History ........................................................................................................ 31
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1
Ordering Information and Module Marking
Table 1-1.
Ordering Details
Ordering Code
Package
Description
ATWILC1000-MR1100A
14.48 x 13.46 x 3.35mm
Certified module with ATWILC1000A-Mu chip
Figure 1-2.
Marking Information
ATWILC1000MR 1 1 0 0 A A
Blank = Tray Packing
MR = Industrial
0 = No OTA/ No Shield
1 = No OTA with Shield
2 = OTA with Shield
7 = OTA/ No Shield
1 = 2.4GHz
4
Revision Letter
0 = No FEM
1 = FEM
ATWILC1000-MR1100A
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0 = No Antenna
P = PCB Antenna
C = Chip Antenna
2
Block Diagram
Figure 2-1.
Block Diagram
VBAT
VDDIO
I2C
RX/TX
SDIO~_SPI_CFG
SPI/SDIO
GPIO3
GPIO4
ATWILC1000A
802.11 B,G,N SOC
GPIO5
GPIO6
IRQN
26 Mhz Crystal
Chip_En
WAKE
RESET
GND
3
Pin-out and Package Information
3.1
Pin Description
Figure 3-1.
Pin Assignment
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Table 3-1.
NO
1
2
3
Name
GPIO_6
I2C_SCL
I2C_SDA
Type
Description
Programmable
Pull-up Resistor
I/O
General purpose I/O.
Yes
I/O
I2C Slave Clock. Can be configured as either master or slave. I2C interface is only used for test purposes. This pin should be brought to a test point
only. Do not add a pull-up resistor.
Yes
I/O
I2C Slave Data. Can be configured as either master or slave. I2C interface is only used for test purposes. This pin should be brought to a test point
only. Do not add a pull-up resistor.
Yes
No
4
RESET_N
I
Active-Low Hard Reset. When asserted to a low
level, the module will be placed in a reset state.
When asserted to a high level, the module will run
normally. Connect to a host output that defaults
low at power up. If the output floats, add a 1MΩ
pull-down resistor if necessary to ensure a low
level at power up.
5
NC
-
No connect
6
NC
-
No connect
7
NC
-
No connect
8
GND
-
GND
9
NC
-
No connect
10
GND
-
GND
11
RF_IN
I
RF Input
12
GND
-
GND
13
SDIO_SPI_CFG
I
Tie to VDDIO through a 1MΩ resistor to enable
the SPI interface. Connect to ground to enable
SDIO interface.
No
14
WAKE
I
Host Wake control. Can be used to wake up the
module from Doze mode. Connect to a host
GPIO.
No
15
GND
-
GND
16
IRQN
O
ATWINC1000 Device Interrupt.
No
SDIO Data Line 3 from ATWILC1000-MR1100A
when module is configured for SDIO. UART
Transmit Output from ATWILC1000 when module
is configured for SPI.
Yes
17
6
Pin Description
SD_DAT3/UART_TXD
SDIO=I/O
UART=O
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NO
18
19
20
21
Name
Type
Programmable
Pull-up Resistor
Description
SD_DAT2/SPI_RXD
SDIO=I/O
SPI=I
SDIO Data Line 2 signal from ATWILC1000MR1100A when module is configured for SDIO.
SPI MOSI (Master Out Slave In) pin when module
is configured for SPI.
Yes
SD_DAT1/SPI_SSN
SDIO=I/O
SPI=I
SDIO Data Line 1 from ATWILC1000-MR1100A
when module is configured for SDIO. Active Low
SPI Slave Select from ATWILC1000 when module
is configured for SPI.
Yes
SD_DAT0/SPI_TXD
SDIO=I/O
SPI=O
SDIO Data Line 0 from ATWILC1000-MR1100A
when module is configured for SDIO. SPI MISO
(Master In Slave Out) pin from ATWILC1000 when
module is configured for SPI.
Yes
SD_CMD/SPI_SCK
SDIO=I/O
SPI=I
SDIO CMD Line from ATWILC1000-MR1100A
when module is configured for SDIO. SPI Clock
from ATWILC1000 when module is configured for
SPI.
Yes
SDIO=I
UART=I
SDIO Clock Line from ATWILC1000-MR1100A
when module is configured for SDIO. UART Receive input to ATWILC1000 when module is configured for SPI.
Yes
22
SD_CLK/UART_RXD
23
VBATT
-
Battery power supply
24
GPIO_1
I
General Purpose I/O.
Yes
No
25
CHIP_EN
I
Module enable. High level enables module, low
level places module in Power Down mode. Connect to a host Output that defaults low at power
up. If the output floats, add a 1MΩ pull-down resistor if necessary to ensure a low level at power
up.
26
VDDIO
-
I/O Power Supply. Must match host I/O voltage.
27
1P3V_TP
-
1.3V VDD Core Test Point
28
GPIO_3
-
General purpose I/O.
Yes
29
GPIO_4
I/O
General purpose I/O.
Yes
30
GPIO_5
I/O
General purpose I/O.
Yes
31
GND
-
GND
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3.2
Module Outline Drawings
Figure 3-2.
8
Module Drawings
ATWILC1000-MR1100A
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Electrical Specifications
4.1
Absolute Ratings
Table 4-1.
4.2
Voltages
Symbol
Description
Min.
Max.
Unit
VBAT
Input supply Voltage
-0.3
5.5
V
VDDIO
SPI, SDIO, GPIO Voltage
-0.3
3.6
V
Recommended Operating Ratings
Table 4-2.
Pin Recommended Operating Ratings
Test Conditions: -40ºC - +85ºC
Symbol
Min.
Typ.
Max.
Unit
VBAT
3.0
3.6
4.2
V
VDDIO
1.8
3.3
3.6
V
Note:
The voltage of VDDIO is dependent on system I/O voltage.
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5
CPU and Memory Subsystems
5.1
Processor
ATWILC1000A has a Cortus APS3 32-bit processor. This processor performs many of the MAC functions,
including but not limited to association, authentication, power management, security key management, and
MSDU aggregation/de-aggregation. In addition, the processor provides flexibility for various modes of
operation, such as STA and AP modes.
5.2
Memory Subsystem
The APS3 core uses a 128KB instruction/boot ROM along with a 128KB instruction RAM and a 64KB data
RAM. In addition, the device uses a 128KB shared RAM, accessible by the processor and MAC, which allows
the APS3 core to perform various data management tasks on the TX and RX data packets.
5.3
Non-Volatile Memory (eFuse)
ATWILC1000A has 768 bits of non-volatile eFuse memory that can be read by the CPU after device reset. This
non-volatile one-time-programmable (OTP) memory can be used to store customer-specific parameters, such
as MAC address; various calibration information, such as TX power, crystal frequency offset, etc.; and other
software-specific configuration parameters. The eFuse is partitioned into six 128-bit banks. Each bank has the
same bit map, which is shown in Figure 5-1. The purpose of the first 80 bits in each bank is fixed, and the
remaining 48 bits are general-purpose software dependent bits, or reserved for future use. Since each bank
can be programmed independently, this allows for several updates of the device parameters following the initial
programming, e.g. updating MAC address. Refer to ATWILC1000A Programming Guide for the eFuse
programming instructions.
Flags
8
Bank 0
F
48
MAC ADDR
8
G
16
FO
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
128 Bits
10
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0
1
15
Freq.
Offset
7
Used
1
TX
Gain
Correc
tion
1
Used
4
MAC ADDR
Used
3
Reserved
1
Invalid
Used
1
eFuse Bit Map
Version
Figure 5-1.
6
WLAN Subsystem
The WLAN subsystem is composed of the Media Access Controller (MAC) and the Physical Layer (PHY). The
following two subsections describe the MAC and PHY in detail.
6.1
MAC
6.1.1
Features
The ATWILC1000A IEEE802.11 MAC supports the following functions:

IEEE 802.11b/g/n

IEEE 802.11e WMM QoS EDCA/PCF multiple access categories traffic scheduling

Advanced IEEE 802.11n features:

6.1.2
–
Transmission and reception of aggregated MPDUs (A-MPDU)
–
Transmission and reception of aggregated MSDUs (A-MSDU)
–
Immediate Block Acknowledgement
–
Reduced Interframe Spacing (RIFS)
Support for IEEE802.11i and WFA security with key management
–
WEP 64/128
–
WPA-TKIP
–
128-bit WPA2 CCMP (AES)

Support for WAPI security

Advanced power management
–
Standard 802.11 Power Save Mode
–
Wi-Fi Alliance WMM-PS (U-APSD)

RTS-CTS and CTS-self support

Supports either STA or AP mode in the infrastructure basic service set mode

Supports independent basic service set (IBSS)
Description
The ATWILC1000A MAC is designed to operate at low power while providing high data throughput. The IEEE
802.11 MAC functions are implemented with a combination of dedicated datapath engines, hardwired control
logic, and a low-power, high-efficiency microprocessor. The combination of dedicated logic with a
programmable processor provides optimal power efficiency and real-time response while providing the
flexibility to accommodate evolving standards and future feature enhancements.
Dedicated datapath engines are used to implement data path functions with heavy computational. For
example, an FCS engine checks the CRC of the transmitting and receiving packets, and a cipher engine
performs all the required encryption and decryption operations for the WEP, WPA-TKIP, WPA2 CCMP-AES,
and WAPI security requirements.
Control functions which have real-time requirements are implemented using hardwired control logic modules.
These logic modules offer real-time response while maintaining configurability via the processor. Examples of
hardwired control logic modules are the channel access control module (implements EDCA/HCCA, Beacon TX
control, interframe spacing, etc.), protocol timer module (responsible for the Network Access Vector, back-off
timing, timing synchronization function, and slot management), MPDU handling module, aggregation/deaggregation module, block ACK controller (implements the protocol requirements for burst block
communication), and TX/RX control FSMs (coordinate data movement between PHY-MAC interface, cipher
engine, and the DMA interface to the TX/RX FIFOs).
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1
The MAC functions implemented solely in software on the microprocessor have the following characteristics:

Functions with high memory requirements or complex data structures. Examples are association table
management and power save queuing.

Functions with low computational load or without critical real-time requirements. Examples are
authentication and association.

Functions which need flexibility and upgradeability. Examples are beacon frame processing and QoS
scheduling.
6.2
PHY
6.2.1
Features
The ATWILC1000A IEEE802.11 PHY supports the following functions:
6.2.2

Single antenna 1x1 stream in 20MHz channels

Supports IEEE 802.11b DSSS-CCK modulation: 1, 2, 5.5, 11Mbps

Supports IEEE 802.11g OFDM modulation: 6, 9, 12,18, 24, 36, 48, 54Mbps

Supports IEEE 802.11n HT modulations MCS0-7, 20MHz, 800 and 400ns guard interval: 6.5, 7.2, 13.0,
14.4, 19.5, 21.7, 26.0, 28.9, 39.0, 43.3, 52.0, 57.8, 58.5, 65.0, 72.2Mbps

IEEE 802.11n mixed mode operation

Per packet TX power control

Advanced channel estimation/equalization, automatic gain control, CCA, carrier/symbol recovery, and
frame detection
Description
The ATWILC1000A WLAN PHY is designed to achieve reliable and power-efficient physical layer
communication specified by IEEE 802.11 b/g/n in single stream mode with 20MHz bandwidth. Advanced
algorithms have been employed to achieve maximum throughput in a real world communication environment
with impairments and interference. The PHY implements all the required functions such as FFT, filtering, FEC
(Viterbi decoder), frequency and timing acquisition and tracking, channel estimation and equalization, carrier
sensing and clear channel assessment, as well as the automatic gain control.
6.3
Radio
Table 6-1.
Radio Performance under Typical Conditions: VBAT=3.6V; VDDIO=3.3V; Temp.: 25ºC
Feature
Description
Module Part Number
ATWILC1000-MR1100A
WLAN Standard
IEEE 802.11b/g/n, Wi-Fi compliant
Host Interface
SPI, SDIO
Dimension
L x W x H: 14.48 x 13.46 x 3.35 (typical) mm
Frequency Range
2.412GHz ~ 2.4835GHz (2.4GHz ISM Band)
Number of Channels
11 for North America, 13 for Europe, and 14 for Japan
Modulation
802.11b: DQPSK, DBPSK, CCK
802.11g/n: OFDM/64-QAM,16-QAM, QPSK, BPSK
802.11b/11Mbps: 19dBm ±1.5dB @ EVM -9dB
Output Power1
802.11g/54Mbps: 14.5dBm ±2dB @ EVM -25dB
12
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Feature
Description
802.11n/65Mbps: 13dBm ±2dB @ EVM -28dB
Receive Sensitivity
(11n,20MHz)
@10% PER
Receive Sensitivity (11g)
@10% PER
Receive Sensitivity (11b)
@8% PER
- MCS=0
PER @ -90 ±1dBm, typical
- MCS=1
PER @ -86 ±1dBm, typical
- MCS=2
PER @ -84 ±1dBm, typical
- MCS=3
PER @ -81.5 ±1dBm, typical
- MCS=4
PER @ -78 ±1dBm, typical
- MCS=5
PER @ -74 ±1dBm, typical
- MCS=6
PER @ -72.5 ±1dBm, typical
- MCS=7
PER @ -71.5 ±1dBm, typical
- 6Mbps
PER @ -91 ±1dBm, typical
- 9Mbps
PER @ -89 ±1dBm, typical
- 12Mbps
PER @ -88.5 ±1dBm, typical
- 18Mbps
PER @ -86.5 ±1dBm, typical
- 24Mbps
PER @ -84 ±1dBm, typical
- 36Mbps
PER @ -78.5 ±1dBm, typical
- 48Mbps
PER @ -77 ±1dBm, typical
- 54Mbps
PER @ -75 ±1dBm, typical
- 1Mbps
PER @ -98 ±1dBm, typical
- 2Mbps
PER @ -95 ±1dBm, typical
- 5.5Mbps
PER @ -93 ±1dBm, typical
- 11Mbps
PER @ -89 ±1dBm, typical
802.11b: 1, 2, 5.5, 11Mbps
Data Rate
802.11g: 6, 9, 12, 18, 24, 36, 48, 54Mbps
Data Rate
802.11n: 6.5, 13, 19.5, 26, 39, 52, 58.5, 65Mbps
Data Rate
(20MHz ,short GI,400ns)
802.11n: 7.2, 14.4, 21.7, 28.9, 43.3, 57.8, 65,72.2Mbps
802.11b: 0dBm typical
Maximum Input Level
802.11g/n: -5dBm typical
Operating
temperature2
-40°C to 85°C
Storage temperature
-40°C to 85°C
Humidity
Operating Humidity 10% to 95% Non-Condensing
Storage Humidity 5% to 95% Non-Condensing
Notes:
1.
2.
Measured at 802.11 spec compliant EVM/Spectral Mask.
RF performance guaranteed for temperature range -30 to 85ºC. 1dB derating in performance at -40ºC.
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7
External Interfaces
7.1
SPI Interface
7.1.1
Overview
When the module is configured for SPI mode by connecting the SDIO~_SPI_CFG pin to VDDIO, the
ATWILC1000-MR1100 has a Serial Peripheral Interface (SPI) that operates as a SPI slave. The SPI interface
can be used for control and for serial I/O of 802.11 data. The SPI pins are mapped as shown in Table 7-1. The
SPI is a full-duplex slave-synchronous serial interface that is available immediately following reset when pin 10
(SPI_CFG) is tied to VDDIO.
Table 7-1.
SPI Interface Pin Mapping
Pin #
SPI Function
10
CFG: Must be tied to VDDIO
16
SSN: Active Low Slave Select
15
MOSI: Serial Data Receive
18
SCK: Serial Clock
17
MISO: Serial Data Transmit
When the SPI is not selected, i.e., when SSN is high, the SPI interface will not interfere with data transfers
between the serial-master and other serial-slave devices. When the serial slave is not selected, its transmitted
data output is buffered, resulting in a high impedance drive onto the MISO line.
The SPI interface responds to a protocol that allows an external host to read or write any register in the chip as
well as initiate DMA transfers.
The SPI SSN, MOSI, MISO and SCK pins of the ATWILC1000-MR1100 have internal programmable pull-up
resistors (see Section 8.1). These resistors should be programmed to be disabled. Otherwise, if any of the SPI
pins are driven to a low level while the ATWILC1000-MR1100 is in the low power sleep state, current will flow
from the VDDIO supply through the pull-up resistors, increasing the current consumption of the module.
7.1.2
SPI Timing
The SPI timing is provided in Figure 7-1 and Table 7-2.
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Figure 7-1.
SPI Timing Diagram (SPI Mode CPOL=0, CPHA=0)
Table 7-2.
SPI Slave Timing Parameters
Parameter
Symbol
Min.
Max.
Unit
Clock Input Frequency
fSCK
48
MHz
Clock Low Pulse Width
tWL
15
Clock High Pulse Width
tWH
15
Clock Rise Time
tLH
10
Clock Fall Time
tHL
10
Input Setup Time
tISU
5
Input Hold Time
tIHD
5
Output Delay
tODLY
0
Slave Select Setup Time
tSUSSN
5
Slave Select Hold Time
tHDSSN
5
Remarks
ns
20
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7.2
UART Interface
When the module is configured for SPI mode by connecting the SDIO~_SPI_CFG pin to VDDIO, the
ATWILC1000-MR1100 has a Universal Asynchronous Receiver/Transmitter (UART) interface available on pins
J14 and J19. It can be used for control or data transfer if the baud rate is sufficient for a given application. The
UART is compatible with the RS-232 standard, where NMC1000 operates as Data Terminal Equipment (DTE).
It has a two-pin RXD/TXD interface.
The UART features programmable baud rate generation with fractional clock division, which allows
transmission and reception at a wide variety of standard and non-standard baud rates. The UART input clock is
selectable between 10MHz, 5MHz, 2.5MHz, and 1.25MHz. The clock divider value is programmable as 13
integer bits and three fractional bits (with 8.0 being the smallest recommended value for normal operation).
This results in the maximum supported baud rate of 10MHz/8.0 = 1.25MBd.
The UART can be configured for seven or eight bit operation, with or without parity, with four different parity
types (odd, even, mark, or space), and with one or two stop bits. It also has RX and TX FIFOs, which ensure
reliable high speed reception and low software overhead transmission. FIFO size is 4x8 for both RX and TX
direction. The UART also has status registers showing the number of received characters available in the FIFO
and various error conditions, as well the ability to generate interrupts based on these status bits.
An example of UART receiving or transmitting a single packet is shown in Figure 7-2. This example shows 7-bit
data (0x45), odd parity, and two stop bits.
See the ATWILC1000-MR1100 Programming Guide for information on configuring the UART.
Figure 7-2.
Example of UART RX or TX Packet
7.3
SDIO Interface
7.3.1
Overview
When the module is configured for SDIO mode by connecting the SDIO~_SPI_CFG pin to Ground, the
ATWILC1000-MR1100 has a SDIO interface. The SDIO interface can be used for control and for serial I/O of
802.11 data. The SDIO pins are mapped as shown in 0. The SDIO interface is available immediately following
reset when pin 10 (SPI_CFG) is tied to ground.
The ATWILC1000-MR1100 SDIO is a full speed interface. The interface supports the 1-bit/4-bit SD transfer
mode at the clock range of 0 - 50MHz. The Host can use this interface to read and write from any register
within the chip as well as configure the ATWILC1000-MR1100 for data DMA.
16
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Table 7-3.
ATWILC1000 SDIO Interface Pin Mapping
Pin #
SDIO Function
10
CFG: Must be tied to ground
14
DAT3: Data 3
15
DAT2: Data 2
16
DAT1: Data 1
17
DAT0: Data 0
18
CMD: Command
19
CLK: Clock
When the SDIO card is inserted into an SDIO aware host, the detection of the card will be via the means
described in SDIO specification. During the normal initialization and interrogation of the card by the host, the
card will identify itself as an SDIO device. The host software will obtain the card information in a tuple (linked
list) format and determine if that card’s I/O function(s) are acceptable to activate. If the card is acceptable, it will
be allowed to power up fully and start the I/O function(s) built into it.
The SD memory card communication is based on an advanced 9-pin interface (Clock, Command, four data
and three power lines) designed to operate at maximum operating frequency of 50MHz.
7.3.2
7.3.3
Features

Meets SDIO card specification version 2.0

Host clock rate variable between 0 and 50MHz

1-bit/4-bit SD bus modes supported

Allows card to interrupt host

Responds to Direct read/write (IO52) and Extended read/write (IO53) transactions

Supports Suspend/Resume operation
SDIO Timing
Figure 7-3.
SDIO Timing Diagram
fpp
tWL
SD_CLK
tHL
tWH
tLH
tISU
tIH
Inputs
tODLY(MAX)
tODLY(MIN)
Outputs
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Table 7-4.
SDIO Timing Parameters
Parameter
Symbol
Min.
Max.
Unit
Clock Input Frequency
fPP
0
50
MHz
Clock Low Pulse Width
tWL
10
Clock High Pulse Width
tWH
10
Clock Rise Time
tLH
10
Clock Fall Time
tHL
10
Input Setup Time
tISU
5
Input Hold Time
tIH
5
Output Delay
tODLY
0
7.4
I2C Interface
7.4.1
Overview
ns
14
ATWILC1000-MR1100 provides an I2C bus slave that allows the host processor to read or write any register in
the chip. ATWILC1000-MR1100 supports I2C bus Version 2.1 – 2000.
The I2C interface, used primarily for debug, is a two-wire serial interface consisting of a serial data line (SDA,
Pin 17) and a serial clock (SCL, Pin 18). It responds to the seven bit address value 0x60. The ATWILC1000MR1100 I2C interface can operate in standard mode (with data rates up to 100Kb/s) and fast mode (with data
rates up to 400Kb/s).
The I2C is a synchronous serial interface. The SDA line is a bidirectional signal and changes only while the
SCL line is low, except for STOP, START, and RESTART conditions. The output drivers are open-drain to
perform wire-AND functions on the bus. The maximum number of devices on the bus is limited by only the
maximum capacitance specification of 400pF. Data is transmitted in byte packages.
For specific information, refer to the Philips Specification entitled “The I2C -Bus Specification, Version 2.1”.
7.4.2
I2C Timing
The I2C timing is provided in Figure 7-4 and Table 7-5.
Figure 7-4.
I2C Timing Diagram
tPR
tSUDAT
tHDDAT
tBUF
tSUSTO
SDA
tHL
tLH
tWL
SCL
tHDSTA
tLH
tHL
tWH
tPR
fSCL
18
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tPR
tSUSTA
Table 7-5.
I2C Timing Parameters
Parameter
Symbol
Min.
Max.
Unit
SCL Clock Frequency
fSCL
0
400
kHz
SCL Low Pulse Width
tWL
1.3
SCL High Pulse Width
tWH
0.6
SCL, SDA Fall Time
tHL
300
SCL, SDA Rise Time
tLH
300
START Setup Time
tSUSTA
0.6
START Hold Time
tHDSTA
0.6
SDA Setup Time
tSUDAT
100
SDA Hold Time
tHDDAT
0
40
STOP Setup time
tSUSTO
0.6
Bus Free Time Between
STOP and START
tBUF
1.3
Glitch Pulse Reject
tPR
0
Remarks
µs
ns
This is dictated by external
components
µs
7.5
ns
Slave and Master Default
Master Programming Option
µs
50
ns
Wi-Fi/Bluetooth Coexistence
ATWILC1000A supports 2- and 3-wire Wi-Fi/Bluetooth Coexistence signaling conforming to the IEEE 802.15.22003 standard, Part 15.2. The type of coexistence interface used (2- or 3-wire) is chosen to be compatible with
the specific Bluetooth device used in a given application. Table 7-6 shows a usage example of the 2-wire
interface using the GPIO3 and GPIO4 pins; 3-wire interface using the GPIO3, GPIO4, and GPIO5 pins; for
more specific instructions on configuring Coexistence refer to ATWILC1000A Programming Guide.
Table 7-6.
Coexistence Pin Assignment Example
Pin Name
Function
Target
Pin #
2-wire
3-wire
GPIO3
BT_Req
BT is requesting to access the medium to transmit or receive. Goes high on TX or RX slot.
28
Used
Used
GPIO4
BT_Pri
Priority of the BT packets in the requested slot.
High to indicate high priority and low for normal.
29
Not Used
Used
GPIO5
WL_Act
Device response to the BT request.
High - BT_req is denied and BT slot blocked.
30
Used
Used
GPIO6
Ant_SW
Direct control on Antenna (coex bypass).
31
Not Used
Optional
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8
Power Consumption
8.1
Description of Device States
ATWILC1000A has several Devices States:
8.2

ON_Transmit
– Device is actively transmitting an 802.11 signal

ON_Receive
– Device is actively receiving an 802.11 signal

ON_Doze
– Device is on but is neither transmitting nor receiving

Power_Down
– Device core supply off (Leakage)
Controlling the Device States
Table 8-1 shows how to switch between the device states using the following:

CHIP_EN
– Device pin (pin #23) used to enable DC/DC Converter

VDDIO
– I/O supply voltage from external supply
Table 8-1.
Device States
Power Consumption1
Device State
VDDIO
IVBATT
IVDDIO
ON_Transmit
VDDIO
On
230mA @ 18dBm
29mA
ON_Receive
VDDIO
On
68mA
29mA
ON_Doze
VDDIO
On
280µA
<10µA
Power_Down
GND
On
<0.5µA
<0.2µA
Note:
8.3
CHIP_EN
1.
Conditions: VBAT @ 3.6V, I/O @ 1.8V.
Restrictions for Power States
When no power supplied to the device, i.e., the DC/DC Converter output and VDDIO are both off (at ground
potential). In this case, a voltage cannot be applied to the device pins because each pin contains an ESD diode
from the pin to supply. This diode will turn on when voltage higher than one diode-drop is supplied to the pin.
If a voltage must be applied to the signal pads while the chip is in a low power state, the VDDIO supply must
be on, so the SLEEP or Power_Down state must be used.
Similarly, to prevent the pin-to-ground diode from turning on, do not apply a voltage that is more than one
diode-drop below ground to any pin.
8.4
Power-Up/Down Sequence
The power-up/down sequence for ATWILC1000A is shown in Figure 8-1. The timing parameters are provided
in Table 8-2.
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Figure 8-1.
Power Up/Down Sequence
VBATT
tA
t A'
VDDIO
tB
t B'
CHIP_EN
tC
t C'
RESETN
XO Clock
Table 8-2.
Parameter
Power-Up/Down Sequence Timing
Min.
Max.
Unit
Description
Notes
tA
0
VBATT rise to VDDIO rise
VBATT and VDDIO can rise simultaneously
or can be tied together. VDDIO must not rise
before VBATT.
tB
0
VDDIO rise to CHIP_EN rise
CHIP_EN must not rise before VDDIO.
CHIP_EN must be driven high or low, not
left floating.
CHIP_EN rise to RESETN rise
This delay is needed because XO clock
must stabilize before RESETN removal. RESETN must be driven high or low, not left
floating.
tC
5
ms
tA’
0
VDDIO fall to VBATT fall
VBATT and VDDIO can fall simultaneously
or can be tied together. VBATT must not fall
before VDDIO.
tB’
0
CHIP_EN fall to VDDIO fall
VDDIO must not fall before CHIP_EN.
CHIP_EN and RESETN can fall simultaneously.
tC’
0
RESETN fall to VDDIO fall
VDDIO must not fall before RESETN. RESETN and CHIP_EN can fall simultaneously.
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8.5
Digital I/O Pin Behavior during Power-up Sequences
Table 8-3 represents digital IO Pin states corresponding to device power modes.
Table 8-3.
Digital I/O Pin Behavior in Different Device States
Device State
VDDIO
CHIP_EN
RESETN
Output
Driver
Input
Driver
Pull Up/Down
Resistor (96Ω)
Power_Down:
core supply off
High
Low
Low
Disabled (Hi-Z)
Disabled
Disabled
Power-On Reset:
core supply on, hard reset on
High
High
Low
Disabled (Hi-Z)
Disabled
Enabled
Power-On Default:
core supply on, device out of
reset but not programmed
yet
High
High
High
Disabled (Hi-Z)
Disabled
Enabled
High
Programmed by
firmware for
each pin:
Enabled or Disabled
Opposite
of Output
Driver
state
Programmed by
firmware for
each pin: Enabled or Disabled
On_Doze/
On_Transmit/
On_Receive:
core supply on, device
programmed by firmware
22
High
High
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9
Notes on Interfacing to the ATWILC1000-MR1100
9.1
Programmable Pull-up Resistors
The ATWILC1000-MR1100 provides programmable pull-up resistors on various pins. The purpose of these
resistors is to keep any unused input pins from floating which can cause excess current to flow through the
input buffer from the VDDIO supply. Any unused module pin on the ATWILC1000-MR1100 should leave these
pull-up resistors enabled so the pin will not float. The default state at power up is for the pull-up resistor to be
enabled. However, any pin which is used should have the pull-up resistor disabled. The reason for this is that if
any pins are driven to a low level while the ATWILC1000-MR1100 is in the low power sleep state, current will
flow from the VDDIO supply through the pull-up resistors, increasing the current consumption of the module.
Since the value of the pull-up resistor is approximately 100KΩ, the current through any pull-up resistor that is
being driven low will be VDDIO/100K. For VDDIO = 3.3V, the current through each pull-up resistor that is
driven low would be approximately 3.3V/100K = 33µA. Pins which are used and have had the programmable
pull-up resistor disabled should always be actively driven to either a high or low level and not be allowed to
float.
See the ATWILC1000-MR1100 Programming Guide for information on enabling/disabling the programmable
pull up resistors.
10
Recommended Footprint
Figure 10-1.
Footprint Drawing (unit = mm)
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11
RF Performance Placement Guidelines
It is critical to follow the recommendations listed below to achieve the best RF performance:
24

Module must be placed on main board - printed antenna area must overlap with the carrier board. The
portion of the module containing the antenna should not stick out over the edge of the main board. The
antenna is designed to work properly when it is sitting directly on top of a 1.5mm thick printed circuit
board.

If the module is placed at the edge of the main board, a minimum 22mm by 5mm area directly under the
antenna must be clear of all metal on all layers of the board. “In-land” placement is acceptable; however
deepness of keep-out area must grove to: module edge to main board edge plus 5mm. DO NOT PLACE
MODULE IN THE MIDDLE OF THE MAIN BOARD OR FAR AWAY FROM THE MAIN BOARD EDGE.

Keep away from antenna, as far as possible, large metal objects to avoid electromagnetic field blocking

Do not enclose the antenna within a metal shield

Keep any components which may radiate noise or signals within the 2.4GHz – 2.5GHz frequency band
far away from the antenna or better yet, shield those components. Any noise radiated from the main
board in this frequency band will degrade the sensitivity of the module.

Contact Atmel for assistance if any other placement is required.
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12
Recommended Reflow Profile
Refer to IPC/JEDEC standard. Peak temperature: <250°C.
Number of Times: Two times maximum.
Figure 12-1.
Typical Reflow Profile
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13
Module Schematics
Figure 13-1.
26
ATWILC1000-MR1100A Schematic
ATWILC1000-MR1100A
[DATASHEET]
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14
Module Bill of Materials (BOM)
Table 14-1.
ATWILC1000-MR1100 BOM
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15
Application Reference Design
The ATWILC1000-MR1100A reference design schematic is shown in Figure 15-1.
Figure 15-1.
28
WILC1000-MR1100A SDIO
ATWILC1000-MR1100A
[DATASHEET]
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Figure 15-2.
WILC1000-MR1100A SPI
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16
Reference Documentation and Support
16.1
Reference Documents
Atmel offers a set of collateral documentation to ease integration and device ramp.
The following list of documents available on Atmel web or integrated into development tools.
To enable fast development contact your local FAE or visit the http://www.atmel.com/.
Title
Content
Datasheet
This Document
Design Files
Package
User Guide, Schematic, PCB layout, Gerber, BOM, and System notes on: RF/Radio Full Test Report, radiation pattern, design guidelines, temperature performance, ESD.
Platform Getting
Started Guide
How to use package: Out of the Box starting guide, HW limitations and notes, SW Quick start
guidelines.
HW Design
Guide
Best practices and recommendations to design a board with the product.
Including: Antenna Design for Wi-Fi (layout recommendations, types of antennas, impedance
matching, using a power amplifier etc.), SPI/UART protocol between Wi-Fi SoC and the Host MCU.
SW Design
Guide
Integration guide with clear description of: High level Arch, overview on how to write a networking
application, list all API, parameters and structures.
Features of the device, SPI/handshake protocol between device and host MCU, with flow/sequence/state diagram, timing.
SW Programmer Guide
Explain in details the flow chart and how to use each API to implement all generic use cases (e.g.
start AP, start STA, provisioning, UDP, TCP, http, TLS, p2p, errors management, connection/transfer recovery mechanism/state diagram) - usage and sample App note
For a complete listing of development-support tools and documentation, visit http://www.atmel.com/, or contact
the nearest Atmel field representative.
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17
Revision History
Doc Rev.
Date
42432A
03/2015
Comments
Initial document release.
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