AT93C46D - Complete

AT93C46D
3-wire Serial EEPROM
1K (128 x 8 or 64 x 16)
DATASHEET
Features

Low-voltage Operation
̶
VCC = 1.8V to 5.5V

User-selectable Internal Organization

3-wire Serial Interface
2MHz Clock Rate (5V)
Self-timed Write Cycle (5ms Max)
High Reliability
̶



̶
1K: 128 x 8 or 64 x 16
̶

Endurance: 1,000,000 Write Cycles
Data Retention: 100 Years
8-lead JEDEC SOIC, 8-lead TSSOP, 8-pad UDFN, 8-lead PDIP, and
8-ball VFBGA Packages
Description
The Atmel® AT93C46D provides 1,024 bits of Serial Electrically Erasable
Programmable Read-Only Memory (EEPROM) organized as 64 words of 16 bits
each (when the ORG pin is connected to VCC) and 128 words of 8 bits each (when
the ORG pin is tied to ground). The device is optimized for use in many industrial
and commercial applications where low-power and low-voltage operations are
essential. The AT93C46D is available in space-saving 8-lead JEDEC SOIC,
8-lead TSSOP, 8-pad UDFN, 8-lead PDIP, and 8-ball VFBGA packages.
The AT93C46D is enabled through the Chip Select pin (CS) and accessed via a
3-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift
Clock (SK). Upon receiving a Read instruction at DI, the address is decoded, and
the data is clocked out serially on the DO pin. The write cycle is completely
self-timed, and no separate erase cycle is required before Write. The write cycle is
only enabled when the part is in the Erase/Write Enable state. When CS is
brought high following the initiation of a write cycle, the DO pin outputs the
Ready/Busy status of the part.
The AT93C46D operates from 1.8V to 5.5V.
Atmel-5193H-SEEPROM-AT93C46D-Datasheet_012015
1.
Pin Configurations and Pinouts
Table 1-1.
Pin Configurations
8-lead SOIC
8-lead TSSOP
(Top View)
(Top View)
Pin Name
Function
CS
Chip Select
CS
1
8
VCC
SK
Serial Data Clock
SK
2
7
NC
DI
3
6
ORG
DI
Serial Data Input
DO
4
5
GND
DO
Serial Data Output
GND
Ground
VCC
Power Supply
ORG
Internal Organization
NC
No Connect
CS
SK
DI
DO
CS
SK
DI
DO
1
2
3
4
8-pad UDFN
8-lead PDIP
(Top View)
(Top View)
1
2
3
4
8
7
6
5
VCC
NC
ORG
GND
VCC
NC
ORG
GND
8
7
6
5
CS
1
8
VCC
SK
2
7
NC
DI
3
6
ORG
DO
4
5
GND
8-ball VFBGA
(Top View)
Note:
2.
1
8
VCC
SK
2
7
NC
DI
3
6
ORG
DO
4
5
GND
Drawings are not to scale.
Absolute Maximum Ratings*
Operating Temperature . . . . . . . . . . .-55C to +125C
Storage Temperature . . . . . . . . . . . . .-65C to +150C
Voltage on any pin
with respect to ground . . . . . . . . . . . . . -1.0V to +7.0V
Maximum Operating Voltage . . . . . . . . . . . . . . . 6.25V
DC Output Current . . . . . . . . . . . . . . . . . . . . . . .5.0mA
2
CS
AT93C46D [DATASHEET]
Atmel-5193H-SEEPROM-AT93C46D-Datasheet_012015
*Notice: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage
to the device. This is a stress rating only, and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
3.
Block Diagram
Figure 3-1.
Block Diagram
VCC
GND
Memory Array
ORG
128 x 8
or
64 x 16
Address
Decoder
Data
Register
Output
Buffer
DI
CS
SK
Notes:
1.
2.
Mode Decode
Logic
Clock
Generator
DO
When the ORG pin is connected to VCC, the x16 organization is selected. When it is connected to ground,
the x8 organization is selected. If the ORG pin is left unconnected and the application does not load the input
beyond the capability of the internal 1M pull-up resistor, then the x16 organization is selected.
If the x16 organization is the mode of choice and pin 6 (ORG) is left unconnected, Atmel recommends using
AT93C46E device. For more details, see the AT93C46E datasheet.
AT93C46D [DATASHEET]
Atmel-5193H-SEEPROM-AT93C46D-Datasheet_012015
3
4.
Memory Organization
4.1
Pin Capacitance
Table 4-1.
Pin Capacitance(1)
Applicable over recommended operating range from TA = 25C, f = 1.0MHz, VCC = 1.8V (unless otherwise noted).
Symbol
Test Conditions
COUT
CIN
Note:
4.2
1.
Max
Units
Conditions
Output Capacitance (DO)
5
pF
VOUT = 0V
Input Capacitance (CS, SK, DI)
5
pF
VIN = 0V
This parameter is characterized, and is not 100% tested.
DC Characteristics
Table 4-2.
DC Characteristics
Applicable over recommended operating range from TAI = -40°C to +85°C, VCC = 1.8V to 5.5V (unless otherwise noted).
Symbol
Parameter
VCC1
Supply Voltage
VCC2
Max
Unit
1.8
5.5
V
Supply Voltage
2.7
5.5
V
VCC3
Supply Voltage
4.5
5.5
V
ICC
Supply Current
VCC = 5.0V
Min
Typ
ISB1
Standby Current
ISB2
Read at 1.0MHz
0.5
2.0
mA
Write at 1.0MHz
0.5
2.0
mA
VCC = 1.8V
CS = 0V
0.4
1.0
μA
Standby Current
VCC = 2.7V
CS = 0V
6.0
10.0
μA
ISB3
Standby Current
VCC = 5.0V
CS = 0V
10.0
15.0
μA
IIL
Input Leakage
VIN = 0V to VCC
0.1
1.0
μA
IOL
Output Leakage
VIN = 0V to VCC
0.1
1.0
μA
VIL1(1)
Input Low Voltage
2.7V VCC  5.5V
0.6
0.8
V
VIH1(1)
Input High Voltage
2.7V VCC  5.5V
2.0
VCC + 1
V
VIL2(1)
Input Low Voltage
1.8V  VCC  2.7V
0.6
VCC x 0.3
V
VIH2(1)
Input High Voltage
1.8V  VCC  2.7V
VCC x 0.7
VCC + 1
V
VOL1
Output Low Voltage
2.7V  VCC  5.5V
IOL = 2.1mA
0.4
V
VOH1
Output High Voltage
2.7V  VCC  5.5V
IOH = 0.4mA
VOL2
Output Low Voltage
1.8V  VCC  2.7V
IOL = 0.15mA
VOH2
Output High Voltage
1.8V  VCC  2.7V
IOH = 100μA
Note:
4
Test Condition
1.
VIL min and VIH max are reference only, and are not tested.
AT93C46D [DATASHEET]
Atmel-5193H-SEEPROM-AT93C46D-Datasheet_012015
2.4
V
0.2
VCC  0.2
V
V
4.3
AC Characteristics
Table 4-3.
AC Characteristics
Applicable over recommended operating range from TAI = 40°C to + 85°C, VCC = as specified,
CL = 1 TTL gate and 100pF (unless otherwise noted).
Symbol
Parameter
fSK
SK Clock Frequency
tSKH
SK High Time
tSKL
SK Low Time
tCS
Minimum CS Low Time
tCSS
CS Setup Time
tDIS
DI Setup Time
tCSH
CS Hold Time
tDIH
DI Hold Time
Test Condition
Min
Typ
Max
Units
4.5V  VCC  5.5V
0
2
MHz
2.7V  VCC  5.5V
0
1
MHz
1.8V  VCC  5.5V
0
250
kHz
4.5V  VCC  5.5V
250
ns
2.7V  VCC  5.5V
250
ns
1.8V  VCC  5.5V
1000
ns
4.5V  VCC  5.5V
250
ns
2.7V  VCC  5.5V
250
ns
1.8V  VCC  5.5V
1000
ns
4.5V  VCC  5.5V
250
ns
2.7V  VCC  5.5V
250
ns
1.8V  VCC  5.5V
1000
ns
4.5V  VCC  5.5V
50
ns
2.7V  VCC  5.5V
50
ns
1.8V  VCC  5.5V
200
ns
4.5V  VCC  5.5V
100
ns
2.7V  VCC  5.5V
100
ns
1.8V  VCC  5.5V
400
ns
0
ns
4.5V  VCC  5.5V
100
ns
2.7V  VCC  5.5V
400
ns
Relative to SK
Relative to SK
Relative to SK
Relative to SK
1.8V  VCC  5.5V
ns
4.5V  VCC  5.5V
tPD1
Output Delay to 1
tPD0
Output Delay to 0
tSV
CS to Status Valid
CS to DO in
High-impedance
tDF
tWP
Write Cycle Time
(1)
Endurance
Note:
1.
AC Test
AC Test
AC Test
AC Test
CS = VIL
250
ns
2.7V  VCC  5.5V
250
ns
1.8V  VCC  5.5V
1000
ns
4.5V  VCC  5.5V
250
ns
2.7V  VCC  5.5V
250
ns
1.8V  VCC  5.5V
1000
ns
4.5V  VCC  5.5V
250
ns
2.7V  VCC  5.5V
250
ns
1.8V  VCC  5.5V
1000
ns
4.5V  VCC  5.5V
100
ns
2.7V  VCC  5.5V
250
ns
1.8V  VCC  5.5V
400
ns
5
ms
1.8V  VCC  5.5V
5.0V, 25°C
0.1
3
1,000,000
Write Cycles
This parameter is characterized, and is not 100% tested.
AT93C46D [DATASHEET]
Atmel-5193H-SEEPROM-AT93C46D-Datasheet_012015
5
5.
Functional Description
The AT93C46D is accessed via a simple and versatile 3-wire serial communication interface. Device operation
is controlled by seven instructions issued by the Host processor. A valid instruction starts with a rising edge of
CS and consists of a Start bit (Logic 1), followed by the appropriate opcode, and the desired memory address
location.
Table 5-1.
AT93C46D Instruction Set
Address
Instruction
Data
Opcode
READ
1
10
A6 – A0
A5 – A0
EWEN
1
00
11XXXXXXX
11XXXXXX
ERASE
1
11
A6 – A0
A5 – A0
WRITE
1
01
A6 – A0
A5 – A0
ERAL
1
00
10XXXXXXX
10XXXXXX
WRAL
1
00
01XXXXXXX
01XXXXXX
EWDS
1
00
00XXXXXXX
00XXXXXX
1.
x16
(1)
SB
Note:
x8
(1)
x8
x16
Comments
Reads data stored in memory at
specified address.
Write Enable must precede all
programming modes.
Erases memory location AN – A0.
D7 – D0
D15 – D0
Writes memory location AN – A0.
Erases all memory locations.
Valid only at VCC3 (Section 4.2, “DC
Characteristics” on page 4).
D7 – D0
D15 – D0
Writes all memory locations.
Valid only at VCC3 (Section 4.2).
Disables all programming
instructions.
The ‘X’ in the address field represent don’t care values, and must be clocked.
READ: The READ instruction contains the address code for the memory location to be read. After the
instruction and address are decoded, data from the selected memory location is available at the Serial Output
pin, DO. Output data changes are synchronized with the rising edges of the Serial Clock pin, SK. It should be
noted that a dummy bit (Logic 0) precedes the 8-bit or 16-bit data output string.
Erase/Write Enable (EWEN): To ensure data integrity, the part automatically goes into the Erase/Write Disable
(EWDS) state when power is first applied. An Erase/Write Enable (EWEN) instruction must be executed first
before any programming instructions can be carried out.
Note:
Once in the EWEN state, programming remains enabled until an EWDS instruction is executed, or
VCC power is removed from the part.
ERASE: The ERASE instruction programs all bits in the specified memory location to the Logic 1 state. The
self-timed erase cycle starts once the ERASE instruction and address are decoded. The DO pin outputs the
Ready/Busy status of the part if CS is brought high after being kept low for a minimum of tCS. A Logic 1 at the
DO pin indicates that the selected memory location has been erased, and the part is ready for another
instruction.
6
AT93C46D [DATASHEET]
Atmel-5193H-SEEPROM-AT93C46D-Datasheet_012015
WRITE: The WRITE instruction contains the 8-bits or 16-bits of data to be written into the specified memory
location. The self-timed programming cycle, tWP, starts after the last bit of data is received at Serial Data Input
pin DI. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a
minimum of tCS. A Logic 0 at DO indicates that programming is still in progress. A Logic 1 indicates that the
memory location at the specified address has been written with the data pattern contained in the instruction, and
the part is ready for further instructions. A Ready/Busy status cannot be obtained if CS is brought high after the
end of the self-timed programming cycle, tWP.
Erase All (ERAL): The Erase All (ERAL) instruction programs every bit in the Memory Array to the Logic 1 state
and is primarily used for testing purposes. The DO pin outputs the Ready/Busy status of the part if CS is brought
high after being kept low for a minimum of tCS. The ERAL instruction is valid only at VCC = 5.0V ± 10% (Section 4.2,
“DC Characteristics” on page 4).
Write All (WRAL): The Write All (WRAL) instruction programs all memory locations with the data patterns
specified in the instruction. The DO pin outputs the Ready/Busy status of the part if CS is brought high after
being kept low for a minimum of tCS. The WRAL instruction is valid only at VCC = 5.0V ± 10% (Section 4.2).
Erase/Write Disable (EWDS): To protect against accidental data disturbance, the Erase/Write Disable (EWDS)
instruction disables all programming modes and should be executed after all programming operations. The
operation of the Read instruction is independent of both the EWEN and EWDS instructions and can be
executed at any time.
AT93C46D [DATASHEET]
Atmel-5193H-SEEPROM-AT93C46D-Datasheet_012015
7
6.
Timing Diagrams
Figure 6-1.
Synchronous Data Timing
CS
SK
VIH
1µs (1)
VIL
tSKH
tCSS
VIL
tDIH
VIH
VIL
tPD0
DO (Read)
tPD1
VOL
tDF
VOH
Status Valid
VOL
Note:
1.
This is the minimum SK period.
Table 6-1.
Organization Key for Timing Diagrams
AT93C46D (1K)
8
tDF
VOH
tSV
DO (Program)
tCSH
VIH
tDIS
DI
tSKL
I/O
x8
x16
AN
A6
A5
DN
D7
D15
AT93C46D [DATASHEET]
Atmel-5193H-SEEPROM-AT93C46D-Datasheet_012015
Figure 6-2.
READ Timing
tCS
CS
SK
DI
DO
Figure 6-3.
1
1
0
AN
A0
High-impedance
0
DN
D0
EWEN Timing
tCS
CS
SK
DI
Figure 6-4.
1
0
0
1
1
...
EWDS Timing
tCS
CS
SK
DI
1
0
0
0
0
...
AT93C46D [DATASHEET]
Atmel-5193H-SEEPROM-AT93C46D-Datasheet_012015
9
Figure 6-5.
WRITE Timing
tCS
CS
SK
1
DI
0
1
AN
...
A0
DN
...
D0
High-impedance
DO
Busy
Ready
tWP
Figure 6-6.
WRAL Timing(1)
tCS
CS
SK
1
DI
0
0
0
1
...
DN
...
D0
High-impedance
DO
Busy
tWP
Note:
10
1.
Valid only at VCC3 (Section 4.2, “DC Characteristics” on page 4).
AT93C46D [DATASHEET]
Atmel-5193H-SEEPROM-AT93C46D-Datasheet_012015
Ready
Figure 6-7.
ERASE Timing
tCS
Standby
Check
Status
CS
SK
1
DI
1
1
AN
AN-1 AN-2
...
A0
tDF
tSV
High-impedance
DO
High-impedance
Busy
Ready
tWP
Figure 6-8.
ERAL Timing(1)
tCS
Standby
Check
Status
CS
SK
1
DI
0
0
1
0
tDF
tSV
High-impedance
DO
High-impedance
Busy
Ready
tWP
Note:
1.
Valid only at VCC3 (Section 4.2, “DC Characteristics” on page 4).
AT93C46D [DATASHEET]
Atmel-5193H-SEEPROM-AT93C46D-Datasheet_012015
11
7.
Ordering Code Detail
AT9 3 C 4 6 D N - S H - B
Atmel Designator
Product Family
Shipping Carrier Option
B = Bulk
T = Tape and Reel, Standard Quantity Option
E = Tape and Reel, Expanded Quantity Option
93C = Microwire-compatible
3-Wire Serial EEPROM
Device Density
46 = 1-Kilobit
Device Revision
Package Variation (if applicable)
N
Y6
U3
= 0.150” Wide JEDEC SOIC
= 2.0x3.0mm Body UDFN
= 1.5x2.0mm Body VFBGA
Package Device Grade or
Wafer/Die Thickness
H = Green, NiPdAu Lead Finish
Industrial Temperature Range
(-40°C to +85°C)
U = Green, Matte Tin Lead Finish
or SnAgCu Ball
Industrial Temperature Range
(-40°C to +85°C)
11 = 11mil Wafer Thickness
Package Option
S
= SOIC
T
= TSSOP
Y
= UDFN
P
= PDIP
U
= VFBGA
WWU = Wafer Unsawn
12
AT93C46D [DATASHEET]
Atmel-5193H-SEEPROM-AT93C46D-Datasheet_012015
8.
Ordering Information
Delivery Information
Atmel Ordering Code
Lead Finish
Package
Form
Quantity
Bulk (Tubes)
100 per Tube
Tape and Reel
4,000 per Reel
Bulk (Tubes)
100 per Tube
AT93C46D-TH-T
Tape and Reel
5,000 per Reel
AT93C46DY6-YH-T
Tape and Reel
5,000 per Reel
Tape and Reel
15,000 per Reel
8P3
Bulk (Tubes)
50 per Tube
8U3-1
Tape and Reel
5,000 per Reel
AT93C46DN-SH-B
Operation
Range
8S1
AT93C46DN-SH-T
AT93C46D-TH-B
NiPdAu
(Lead-free/Halogen-free)
8X
8MA2
AT93C46DY6-YH-E
AT93C46D-PU
AT93C46DU3-UU-T
AT93C46D-W-11(1)
Note:
1.
Matte Tin
(Lead-free/Halogen free)
SnAgCu
(Lead-free/Halogen-free)
N/A
Wafer Sale
Industrial
Temperature
(-40C to 85C)
Note 1
For wafer sales, please contact Atmel sales. Bumped die available upon request.
Package Type
8S1
8-lead, 0.150” wide, Plastic Gull Wing, Small Outline (JEDEC SOIC)
8X
8-lead, 0.170” wide, Thin Shrink Small Outline (TSSOP)
8MA2
8P3
8U3-1
8-pad, 2.00mm x 3.00mm body, 0.50mm pitch, Ultra Thin Dual No Lead (UDFN)
8-lead, 0.300” wide body, Plastic Dual In-line Package (PDIP)
8-ball, 1.50mm x 2.00mm body, 0.50mm pitch, Small Die Ball Grid Array (VFBGA)
AT93C46D [DATASHEET]
Atmel-5193H-SEEPROM-AT93C46D-Datasheet_012015
13
9.
Part Markings
AT93C46D: Package Marking Information
8-lead TSSOP
8-lead SOIC
8-pad UDFN
2.0 x 3.0 mm Body
ATMLHYWW
### %
AAAAAAAA
HYWW
###%
###
H%
YXX
Note: Lot Number and location of assembly
and on the bottom side of the package.
8-ball VFBGA
8-lead PDIP
1.5 x 2.0 mm Body
ATMLUYWW
### %
AAAAAAAA
###U
YMXX
PIN 1
Note 1:
designates pin 1
Note 2: Package drawings are not to scale
Catalog Number Truncation
AT93C46D
Truncation Code ###: 46D
Date Codes
Y = Year
4: 2014
5: 2015
6: 2016
7: 2017
Voltages
8: 2018
9: 2019
0: 2020
1: 2021
M = Month
A: January
B: February
...
L: December
WW = Work Week of Assembly
02: Week 2
04: Week 4
...
52: Week 52
Country of Assembly
Lot Number
@ = Country of Assembly
AAA...A = Atmel Wafer Lot Number
Trace Code
% = Minimum Voltage
1: 1.8V min
Grade/Lead Finish Material
H: Industrial/NiPdAu
U: Industrial/Matte Tin/SnAgCu
Atmel Truncation
XX = Trace Code (Atmel Lot Numbers Correspond to Code)
Example: AA, AB.... YZ, ZZ
AT: Atmel
ATM: Atmel
ATML: Atmel
6/11/14
TITLE
DRAWING NO.
REV.
93C46DSM
A
93C46DSM, AT93C46D Package Marking Information
Package Mark Contact:
[email protected]
14
AT93C46D [DATASHEET]
Atmel-5193H-SEEPROM-AT93C46D-Datasheet_012015
10.
Packaging Information
10.1
8S1 — 8-lead JEDEC SOIC
C
1
E
E1
L
N
Ø
TOP VIEW
END VIEW
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
A1
D
SIDE VIEW
Notes: This drawing is for general information only.
Refer to JEDEC Drawing MS-012, Variation AA
for proper dimensions, tolerances, datums, etc.
SYMBOL MIN
A
1.35
NOM
MAX
–
1.75
A1
0.10
–
0.25
b
0.31
–
0.51
C
0.17
–
0.25
D
4.80
–
5.05
E1
3.81
–
3.99
E
5.79
–
6.20
e
NOTE
1.27 BSC
L
0.40
–
1.27
Ø
0°
–
8°
6/22/11
Package Drawing Contact:
[email protected]
TITLE
8S1, 8-lead (0.150” Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)
GPC
SWB
DRAWING NO.
REV.
8S1
G
AT93C46D [DATASHEET]
Atmel-5193H-SEEPROM-AT93C46D-Datasheet_012015
15
10.2
8X — 8-lead TSSOP
C
1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
A
b
A1
e
A2
SYMBOL
D
Side View
Notes:
COMMON DIMENSIONS
(Unit of Measure = mm)
1. This drawing is for general information only.
Refer to JEDEC Drawing MO-153, Variation AA, for proper
dimensions, tolerances, datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate
burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15mm (0.006in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions.
Inter-lead Flash and protrusions shall not exceed 0.25mm
(0.010in) per side.
4. Dimension b does not include Dambar protrusion.
Allowable Dambar protrusion shall be 0.08mm total in excess
of the b dimension at maximum material condition. Dambar
cannot be located on the lower radius of the foot. Minimum
space between protrusion and adjacent lead is 0.07mm.
5. Dimension D and E1 to be determined at Datum Plane H.
MIN
NOM
MAX
A
-
-
1.20
A1
0.05
-
0.15
A2
0.80
1.00
1.05
D
2.90
3.00
3.10
2, 5
E
NOTE
6.40 BSC
E1
4.30
4.40
4.50
3, 5
b
0.19
0.25
0.30
4
e
L
0.65 BSC
0.45
L1
C
0.60
0.75
1.00 REF
0.09
-
0.20
2/27/14
TITLE
Package Drawing Contact:
[email protected]
16
8X, 8-lead 4.4mm Body, Plastic Thin
Shrink Small Outline Package (TSSOP)
AT93C46D [DATASHEET]
Atmel-5193H-SEEPROM-AT93C46D-Datasheet_012015
GPC
TNR
DRAWING NO.
8X
REV.
E
10.3
8MA2 — 8-pad UDFN
E
1
8
Pin 1 ID
2
7
3
6
4
5
D
C
TOP VIEW
A2
SIDE VIEW
A
A1
E2
b (8x)
8
7
1
D2
6
3
5
4
e (6x)
K
L (8x)
BOTTOM VIEW
Notes:
COMMON DIMENSIONS
(Unit of Measure = mm)
2
Pin#1 ID
1. This drawing is for general information only. Refer to
Drawing MO-229, for proper dimensions, tolerances,
datums, etc.
2. The Pin #1 ID is a laser-marked feature on Top View.
3. Dimensions b applies to metallized terminal and is
measured between 0.15 mm and 0.30 mm from the
terminal tip. If the terminal has the optional radius on
the other end of the terminal, the dimension should
not be measured in that radius area.
4. The Pin #1 ID on the Bottom View is an orientation
feature on the thermal pad.
SYMBOL
MIN
NOM
MAX
A
0.50
0.55
0.60
A1
0.0
0.02
0.05
A2
-
-
0.55
D
1.90
2.00
2.10
D2
1.40
1.50
1.60
E
2.90
3.00
3.10
E2
1.20
1.30
1.40
b
0.18
0.25
0.30
C
L
3
1.52 REF
0.30
e
K
NOTE
0.35
0.40
0.50 BSC
0.20
-
-
11/26/14
Package Drawing Contact:
[email protected]
TITLE
8MA2, 8-pad 2 x 3 x 0.6mm Body, Thermally
Enhanced Plastic Ultra Thin Dual Flat No-Lead
Package (UDFN)
GPC
DRAWING NO.
REV.
YNZ
8MA2
G
AT93C46D [DATASHEET]
Atmel-5193H-SEEPROM-AT93C46D-Datasheet_012015
17
10.4
8P3 — 8-lead PDIP
E
1
E1
.381
Gage Plane
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
D
e
D1
A2 A
A1
b2
b3
b v
4 PLCS
Side View
L
0.254 m C
MIN
NOM
MAX
A
-
-
5.334
A1
0.381
-
-
SYMBOL
2
A2
2.921
3.302
4.953
b
0.356
0.457
0.559
5
b2
1.143
1.524
1.778
6
b3
0.762
0.991
1.143
6
c
0.203
0.254
0.356
D
9.017
9.271
10.160
D1
0.127
0.000
0.000
3
E
7.620
7.874
8.255
4
E1
6.096
6.350
7.112
3
e
2.540 BSC
eA
7.620 BSC
L
Notes:
NOTE
2.921
3.302
3
4
3.810
2
1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
07/31/14
Package Drawing Contact:
[email protected]
18
TITLE
GPC
DRAWING NO.
8P3, 8-lead, 0.300” Wide Body, Plastic Dual
In-line Package (PDIP)
PTC
8P3
AT93C46D [DATASHEET]
Atmel-5193H-SEEPROM-AT93C46D-Datasheet_012015
REV.
E
10.5
8U3-1 — 8-ball VFBGA
E
D
2. b
PIN 1 BALL PAD CORNER
A1
A2
TOP VIEW
A
SIDE VIEW
PIN 1 BALL PAD CORNER
3
1
2
4
d
(d1)
8
7
6
5
COMMON DIMENSIONS
(Unit of Measure - mm)
e
(e1)
SYMBOL
MIN
NOM
MAX
BOTTOM VIEW
A
0.73
0.79
0.85
8 SOLDER BALLS
A1
0.09
0.14
0.19
A2
0.40
0.45
0.50
Notes:
b
0.20
0.25
0.30
1. This drawing is for general information only.
D
2. Dimension ‘b’ is measured at maximum solder ball diameter.
3. Solder ball composition shall be 95.5Sn-4.0Ag-.5Cu.
NOTE
2
1.50 BSC
E
2.0 BSC
e
0.50 BSC
e1
0.25 REF
d
1.00 BSC
d1
0.25 REF
6/11/13
Package Drawing Contact:
[email protected]
TITLE
GPC
DRAWING NO.
8U3-1, 8-ball, 1.50mm x 2.00mm body, 0.50mm pitch,
Very Thin, Fine-Pitch Ball Grid Array Package (VFBGA)
GXU
8U3-1
AT93C46D [DATASHEET]
Atmel-5193H-SEEPROM-AT93C46D-Datasheet_012015
REV.
F
19
11.
Revision History
Revision No.
Date
Comments
5193H
01/2015
5193G
08/2014
Updated package drawings, template, logos, and disclaimer page.
5193F
01/2008
Removed the ‘preliminary’ status.
5193E
11/2007
Modified the ‘max’ value in AC Characteristics table.
Added the UDFN expanded quantity option and the ordering information section.
Updated the 8MA2 and 8P3 package drawings.
Moved Pinout figure.
5193D
08/2007
Added new feature for Die Sales.
Modified Ordering Information table layout.
Modified Park Marking Schemes.
Updated to new template.
5193C
06/2007
Added Product Markup Scheme.
Added Technical email contact.
Corrected Figures 4 and 5.
20
5193B
02/2007
Added ‘Ultra Thin’ description to 8-lead Mini-MAP package.
5193A
01/2007
Initial document release.
AT93C46D [DATASHEET]
Atmel-5193H-SEEPROM-AT93C46D-Datasheet_012015
XXXXXX
Atmel Corporation
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© 2015 Atmel Corporation. / Rev.: Atmel-5193H-SEEPROM-AT93C46D-Datasheet_012015.
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