ATA6623C/ATA6625C - Complete

ATA6623C/ATA6625C
LIN Bus Transceiver with Integrated Voltage Regulator
DATASHEET
Features
● Supply voltage up to 40V
● Operating voltage VS = 5V to 27V
● Typically 10µA supply current during sleep mode
● Typically 57µA Supply current in silent mode
● Linear low-drop voltage regulator, 85mA current capability:
●
●
●
●
Normal, fail-safe, and silent mode
Atmel® ATA6623C: VCC = 3.3V ±2%
Atmel ATA6625C: VCC = 5.0V ±2%
Sleep mode: VCC is switched off
● VCC undervoltage detection with reset open drain output NRES (4ms reset time)
● Voltage regulator is short-circuit and over-temperature protected
● LIN physical layer according to LIN 2.0, 2.1 and SAEJ2602-2
● Wake-up capability via LIN bus (90µs dominant)
● TXD time-out timer
● Bus pin is overtemperature and short-circuit protected versus GND and battery
● Advanced EMC and ESD performance
● Fulfills the OEM “Hardware Requirements for LIN in Automotive Applications
Rev1.0”
● Interference and damage protection according to ISO7637
● Package: SO8
4957L-AUTO-09/14
1.
Description
The Atmel® ATA6623C/ATA6625C is a fully integrated LIN transceiver, designed according to the LIN specification 2.0 and
2.1, with a low-drop voltage regulator (3.3V/5V/85mA). The combination of voltage regulator and bus transceiver makes it
possible to develop simple, but powerful, slave nodes in LIN Bus systems. The Atmel ATA6623C/ATA6625C is designed to
handle the low-speed data communication in vehicles (for example, in convenience electronics). Improved slope control at
the LIN driver ensures secure data communication up to 20kBaud with an RC oscillator for the protocol handling. The bus
output is designed to withstand high voltage. Sleep mode (voltage regulator switched off) and silent mode (communication
off; VCC voltage on) guarantee minimized current consumption.
Figure 1-1. Block Diagram
ATA6623C/ATA6625C
1
VS
4
LIN
8
VCC
7
NRES
VCC
RXD
Normal
Mode
Receiver
5
+
RF-filter
VCC
Wake-up bus timer
TXD
EN
6
TXD
Time-out
timer
Slew rate control
2
Control
unit
GND
3
Short circuit and
overtemperature
protection
Sleep
mode
VCC
switched
off
Normal/Silent/
Fail-safe Mode
3.3V/5V
Undervoltage reset
2
ATA6623C/ATA6625C [DATASHEET]
4957L–AUTO–09/14
2.
Pin Configuration
Figure 2-1. Pinning SO8
VS
EN
GND
LIN
Table 2-1.
1
2
3
4
8
7
6
5
VCC
NRES
TXD
RXD
Pin Description
Pin
Symbol
Function
1
VS
Battery supply
2
EN
Enables normal mode if the input is high
3
GND
4
LIN
LIN bus line input/output
5
RXD
Receive data output
6
TXD
Transmit data input
7
NRES
Output undervoltage reset, low at reset
8
VCC
Output voltage regulator 3.3V/5V/85mA
Ground, heat sink
ATA6623C/ATA6625C [DATASHEET]
4957L–AUTO–09/14
3
3.
Functional Description
3.1
Physical Layer Compatibility
Since the LIN physical layer is independent from higher LIN layers (e.g., LIN protocol layer), all nodes with a LIN physical
layer according to revision 2.x can be mixed with LIN physical layer nodes, which are according to older versions (i.e., LIN
1.0, LIN 1.1, LIN 1.2, LIN 1.3) without any restrictions.
3.2
Supply Pin (VS)
LIN operating voltage is VS = 5V to 27V. An undervoltage detection is implemented to disable transmission if VS falls below
5V, in order to avoid false bus messages. After switching on VS, the IC starts with the fail-safe mode and the voltage
regulator is switched on.
The supply current in sleep mode is typically 10µA and 57µA in silent mode.
3.3
Ground Pin (GND)
The IC does not affect the LIN Bus in the event of GND disconnection. It is able to handle a ground shift up to 11.5% of VS.
3.4
Voltage Regulator Output Pin (VCC)
The internal 3.3V/5V voltage regulator is capable of driving loads up to 85mA, supplying the microcontroller and other ICs on
the PCB and is protected against overload by means of current limitation and overtemperature shut-down. Furthermore, the
output voltage is monitored and will cause a reset signal at the NRES output pin if it drops below a defined threshold Vthun.
3.5
Undervoltage Reset Output (NRES)
If the VCC voltage falls below the undervoltage detection threshold of Vthun, NRES switches to low after tres_f (Figure 6-1 on
page 11). Even if VCC = 0V the NRES stays low, because it is internally driven from the VS voltage. If VS voltage ramps down,
NRES stays low until VS < 1.5V and then becomes highly resistant.
The implemented undervoltage delay keeps NRES low for tReset = 4ms after VCC reaches its nominal value.
3.6
Bus Pin (LIN)
A low-side driver with internal current limitation and thermal shutdown as well as an internal pull-up resistor according to LIN
specification 2.x is implemented. The voltage range is from –27V to +40V. This pin exhibits no reverse current from the LIN
bus to VS, even in the event of a GND shift or VBatt disconnection. The LIN receiver thresholds are compatible with the LIN
protocol specification.
The fall time (from recessive to dominant) and the rise time (from dominant to recessive) are slope controlled.
3.7
Input Pin (TXD)
In normal mode the TXD pin is the microcontroller interface to control the state of the LIN output. TXD must be pulled to
ground in order to drive the LIN bus low. If TXD is high or unconnected (internal pull-up resistor), the LIN output transistor is
turned off and the bus is in the recessive state.
3.8
Dominant Time-out Function (TXD)
The TXD input has an internal pull-up resistor. An internal timer prevents the bus line from being driven permanently in the
dominant state. If TXD is forced to low longer than tdom > 6ms, the LIN bus driver is switched to the recessive state.
To reactivate the LIN bus driver, switch TXD to high (> 10µs).
3.9
Output Pin (RXD)
This output pin reports the state of the LIN-bus to the microcontroller. LIN high (recessive state) is reported by a high level at
RXD; LIN low (dominant state) is reported by a low level at RXD. The output has an internal pull-up resistor with typically
5kΩ to VCC. The AC characteristics are measured with an external load capacitor of 20pF.
The output is short-circuit protected. In unpowered mode (that is, VS = 0V), RXD is switched off.
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ATA6623C/ATA6625C [DATASHEET]
4957L–AUTO–09/14
3.10
Enable Input Pin (EN)
The Enable Input pin controls the operation mode of the device. If EN is high, the circuit is in normal mode, with transmission
paths from TXD to LIN and from LIN to RXD both active. The VCC voltage regulator operates with 3.3V/5V/85mA output
capability.
If EN is switched to low while TXD is still high, the device is forced to silent mode. No data transmission is then possible, and
the current consumption is reduced to IVS typ. 57µA. The VCC regulator has its full functionality.
If EN is switched to low while TXD is low, the device is forced to sleep mode. No data transmission is possible, and the
voltage regulator is switched off.
4.
Modes of Operation
Figure 4-1. Modes of Operation
a: VS > 5V
Unpowered Mode
VBatt = 0V
b: VS < 3.7V
c: Bus wake-up event
d: NRES switches to low
a
b
Fail-safe Mode
b
b
VCC: 3.3V/5V
with undervoltage monitoring
Communication: OFF
d
EN = 1
c+d
EN = 1
c
Go to silent command
b
EN = 0
Silent Mode
TXD = 1
VCC: 3.3V/5V
with undervoltage monitoring
Communication: OFF
Local wake-up event
Normal Mode
EN = 1
VCC: 3.3V/5V
with undervoltage
monitoring
Go to sleep command
EN = 0
Communication: ON
Sleep Mode
TXD = 0
VCC: switched off
Communication: OFF
Table 4-1.
Modes of Operation
Mode of Operation
Transceiver
VCC
RXD
LIN
Fail safe
OFF
3.3V/5V
High,
Except after wake-up
Recessive
Normal
ON
3.3V/5V
LIN depending
TXD depending
Silent
OFF
3.3V/5V
High
Recessive
Sleep
OFF
0V
0V
Recessive
ATA6623C/ATA6625C [DATASHEET]
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4.1
Normal Mode
This is the normal transmitting and receiving mode of the LIN Interface, in accordance with LIN specification 2.x. The VCC
voltage regulator operates with a 3.3V/5V output voltage, with a low tolerance of ±2% and a maximum output current of
85mA.
If an undervoltage condition occurs, NRES is switched to low and the IC changes its state to fail-safe mode.
4.2
Silent Mode
A falling edge at EN while TXD is high switches the IC into silent mode. The TXD Signal has to be logic high during the mode
select window (Figure 4-2 on page 6). The transmission path is disabled in silent mode. The overall supply current from VBatt
is a combination of the IVSsi = 57µA plus the VCC regulator output current IVCC.
In silent mode the internal slave termination between pin LIN and pin VS is disabled, and only a weak pull-up current
(typically 10µA) between pin LIN and pin VS is present. The silent mode can be activated independently from the current
level on pin LIN.
If an undervoltage condition occurs, NRES is switched to low and the IC changes its state to fail-safe mode.
A voltage less than the LIN Pre-wake detection VLINL at pin LIN activates the internal LIN receiver and switches on the
internal slave termination between the LIN pin and the VS pin.
A falling edge at the LIN pin followed by a dominant bus level maintained for a certain time period (> tbus) and the following
rising edge at pin LIN (see Figure 4-3 on page 7) results in a remote wake-up request.
The device switches from silent mode to fail-safe mode, and the remote wake-up request is indicated by a low level at pin
RXD to interrupt the microcontroller (Figure 4-3 on page 7). EN high can be used to switch directly to normal mode.
Figure 4-2. Switch to Silent Mode
Normal Mode
Silent Mode
EN
TXD
Mode select window
td = 3.2μs
NRES
VCC
Delay time silent mode
td_silent maximum 20μs
LIN
LIN switches directly to recessive mode
6
ATA6623C/ATA6625C [DATASHEET]
4957L–AUTO–09/14
Figure 4-3. LIN Wake-up Waveform Diagram from Silent Mode
Bus wake-up filtering time
tbus
Fail-safe mode
Normal mode
LIN bus
RXD
VCC
High
Low
Silent mode 3.3V/5V
Fail-safe mode 3.3V/5V
Normal mode
EN High
EN
NRES
Undervoltage detection active
ATA6623C/ATA6625C [DATASHEET]
4957L–AUTO–09/14
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4.3
Sleep Mode
A falling edge at EN while TXD is low switches the IC into sleep mode. The TXD Signal has to be logic low during the mode
select window (Figure 4-4 on page 8). To avoid influencing the LIN-pin during the switch to sleep mode, it is possible to
switch the EN up to 3.2µs earlier to LOW than the TXD. Even if the two falling edges at TXD and EN occur at the same time,
the LIN line will remain uninfluenced.
In sleep mode the transmission path is disabled. The supply current IVSsleep from VBatt is typically 10µA. The VCC regulator is
switched off, NRES and RXD are low. The internal slave termination between pin LIN and pin VS is disabled, only a weak
pull-up current (typically 10µA) between pin LIN and pin VS is present. sleep mode can be activated independently from the
current level on pin LIN.
A voltage less than the LIN Pre-wake detection VLINL at pin LIN activates the internal LIN receiver and switches on the
internal slave termination between the LIN pin and the VS pin.
A falling edge at the LIN pin followed by a dominant bus level maintained for a certain time period (> tbus) and a following
rising edge at pin LIN results in a remote wake-up request. The device switches from sleep mode to fail-safe mode.
The VCC regulator is activated, and the remote wake-up request is indicated by a low level at the RXD pin to interrupt the
microcontroller (Figure 4-5 on page 9).
EN high can be used to switch directly from sleep to fail-safe mode. If EN is still high after VCC ramp up and undervoltage
reset time, the IC switches to normal mode.
Figure 4-4. Switch to Sleep Mode
Normal Mode
Sleep Mode
EN
Mode select window
TXD
td = 3.2μs
NRES
VCC
Delay time sleep mode
td_sleep = maximum 20μs
LIN
LIN switches directly to recessive mode
8
ATA6623C/ATA6625C [DATASHEET]
4957L–AUTO–09/14
Figure 4-5. LIN Wake-up Diagram from Sleep Mode
Bus wake-up filtering time
tbus
Fail-safe Mode
Low
Low
Normal Mode
LIN bus
RXD
VCC
voltage
regulator
On state
Off state
Regulator wake-up time
EN High
EN
Reset
time
NRES
Low
Microcontroller
start-up time delay
4.4
Fail-safe Mode
At system power-up the device automatically switches to fail-safe mode. The voltage regulator is switched on (see Figure 61 on page 11). The NRES output switches to low for tres = 4ms and gives a reset to the microcontroller. LIN communication is
switched off. The IC stays in this mode until EN is switched to high, and changes then to the normal mode. A power down of
VBatt (VS < 3.7V) during silent or sleep mode switches the IC into the fail-safe mode after power up. A logic low at NRES
switches the IC into fail-safe mode directly.
4.5
Unpowered Mode
If you connect battery voltage to the application circuit, the voltage at the VS pin increases according to the block capacitor
(see Figure 6-1 on page 11). After VS is higher than the VS undervoltage threshold VSth, the IC mode changes from
unpowered mode to fail-safe mode. The VCC output voltage reaches its nominal value after tVCC. This time, tVCC, depends
on the VCC capacitor and the load.
NRES is low for the reset time delay tReset; no mode change is possible during this time.
ATA6623C/ATA6625C [DATASHEET]
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5.
10
Fail-safe Features
●
During a short-circuit at LIN to VBattery, the output limits the output current to IBUS_lim. Due to the power dissipation, the
chip temperature exceeds TLINoff and the LIN output is switched off. The chip cools down and after a hysteresis of Thys,
switches the output on again. RXD stays on high because LIN is high. During LIN overtemperature switch-off, the VCC
regulator is working independently.
●
During a short-circuit from LIN to GND the IC can be switched into sleep or silent mode. If the short-circuit disappears,
the IC starts with a remote wake-up.
●
The reverse current is very low < 2µA at pin LIN during loss of VBatt. This is optimal behavior for bus systems where
some slave nodes are supplied from battery or ignition.
●
During a short circuit at VCC, the output limits the output current to IVCClim. Because of undervoltage, NRES switches
to low and sends a reset to the microcontroller. The IC switches into fail-safe mode. If the chip temperature exceeds
the value TVCCoff, the VCC output switches off. The chip cools down and after a hysteresis of Thys, switches the output
on again. Because of fail-safe mode, the VCC voltage will switch on again although EN is switched off from the
microcontroller. The microcontroller can then start with normal operation.
●
●
●
●
Pin EN provides a pull-down resistor to force the transceiver into recessive mode if EN is disconnected.
Pin RXD is set floating if VBatt is disconnected.
Pin TXD provides a pull-up resistor to force the transceiver into recessive mode if TXD is disconnected.
If TXD is short-circuited to GND, it is possible to switch to sleep mode via ENABLE after tdom > 20ms.
ATA6623C/ATA6625C [DATASHEET]
4957L–AUTO–09/14
Voltage Regulator
Figure 6-1. VCC Voltage Regulator: Ramp Up and Undervoltage
VS
12V
5.5V/3.8V
VCC
5V/3.3V
Vthun
tVCC
tReset
tres_f
NRES
5V/3.3V
The voltage regulator needs an external capacitor for compensation and to smooth the disturbances from the
microcontroller. It is recommended to use an electrolythic capacitor with C > 1.8µF and a ceramic capacitor with C = 100nF.
The values of these capacitors can be varied by the customer, depending on the application.
With this special SO8 package (fused lead frame to pin 3) an Rthja of 80K/W is achieved.
Therefore, it is recommended to connect pin 3 with a wide GND plate on the printed board to get a good heat sink.
The main power dissipation of the IC is created from the VCC output current IVCC, which is needed for the application.
Figure 6-2 shows the safe operating area of the Atmel® ATA6625C.
Figure 6-2. Power Dissipation: Safe Operating Area: VCC Output Current versus Supply Voltage VS at Different
Ambient Temperatures Due to Rthja = 80K/W
90
80
70
IVCC (mA)
6.
60
Tamb = 85°C
50
40
Tamb = 95°C
30
Tamb = 105°C
Tamb = 115°C
20
10
0
5
6
7
8
9
10
11
12
13
14
15
16
17
18
VS (V)
To program the microcontroller it may be necessary to supply the VCC output via an external power supply while the VS Pin
of the system basis chip is disconnected. This will not affect the system basis chip.
ATA6623C/ATA6625C [DATASHEET]
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7.
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
Min.
Supply voltage VS
VS
–0.3
Pulse time ≤ 500ms
Ta = 25°C
Output current IVCC ≤ 85mA
Pulse time ≤ 2min
Ta = 25°C
Output current IVCC ≤ 85mA
Max.
Unit
+40
V
VS
+40
V
VS
27
V
+5.5
V
+2
mA
Logic pins (RxD, TxD, EN, NRES)
Typ.
–0.3
Output current NRES
INRES
LIN
- DC voltage
–27
+40
V
VCC
- DC voltage
–0.3
+5.5
V
ESD according to IBEE LIN EMC
Test specification 1.0 following IEC 61000-4-2
- Pin VS, LIN to GND
±6
KV
ESD HBM following STM5.1
with 1.5kΩ/100pF
- Pin VS, LIN to GND
±6
KV
±3
KV
CDM ESD STM 5.3.1
±750
V
Machine Model ESD
AEC-Q100-RevF(003)
±200
V
HBM ESD
ANSI/ESD-STM5.1
JESD22-A114
AEC-Q100 (002)
Junction temperature
Tj
–40
+150
°C
Storage temperature
Ts
–55
+150
°C
Max.
Unit
145
K/W
8.
Thermal Characteristics
Parameters
Symbol
Thermal resistance junction to ambient
(free air)
Rthja
Special heat sink at GND (pin 3) on PCB
Rthja
Min.
Typ.
80
K/W
Thermal shutdown of VCC regulator
TVCCoff
150
160
170
°C
Thermal shutdown of LIN output
TLINoff
150
160
170
°C
Thermal shutdown hysteresis
12
ATA6623C/ATA6625C [DATASHEET]
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Thys
10
°C
9.
Electrical Characteristics
5V < VS < 27V, –40°C < Tj < 150°C; unless otherwise specified all values refer to GND pins.
No.
1
1.1
1.2
1.3
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
VS
VS
5
13.5
27
V
A
Sleep mode
VLIN > VS – 0.5V
VS < 14V (Tj = 25°C)
VS
IVSsleep
3
10
14
µA
B
Sleep mode
VLIN > VS – 0.5V
VS < 14V (Tj = 125°C)
VS
IVSsleep
5
11
16
µA
A
Bus recessive
VS < 14V (Tj = 25°C)
Without load at VCC
VS
IVSsi
47
57
67
µA
B
Bus recessive
VS < 14V (Tj = 125°C)
Without load at VCC
VS
IVSsi
56
66
76
µA
A
VS Pin
Nominal DC voltage
range
Supply current in sleep
mode
Supply current in silent
mode
1.4
Supply current in
normal mode
Bus recessive
VS < 14V
Without load at VCC
VS
IVSrec
0.3
0.8
mA
A
1.5
Supply current in
normal mode
Bus dominant
VS < 14V
VCC load current 50mA
VS
IVSdom
50
53
mA
A
1.6
Supply current in
fail-safe mode
Bus recessive
VS < 14V
Without load at VCC
VS
IVSspeed
200
500
µA
A
1.7
VS undervoltage
threshold
VS
VSth
3.7
5
V
A
1.8
VS undervoltage
threshold hysteresis
VS
VSth_hys
V
A
RXD
IRXD
8
mA
A
0.4
V
A
7
kΩ
A
2
4.4
0.2
RXD Output Pin
Normal mode
VLIN = 0V
VRXD = 0.4V
2.1
Low level output sink
current
2.2
Low level output voltage IRXD = 1mA
RXD
VRXDL
2.3
Internal resistor to VCC
RXD
RRXD
3
TXD
VTXDL
–0.3
+0.8
V
A
VCC +
0.3V
V
A
400
kΩ
A
+3
µA
A
3
3.1
1.3
2.5
5
TXD Input Pin
Low level voltage input
3.2
High level voltage input
3.3
Pull-up resistor
3.4
High level leakage
current
TXD
VTXDH
2
VTXD = 0V
TXD
RTXD
125
VTXD = VCC
TXD
ITXD
–3
250
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
ATA6623C/ATA6625C [DATASHEET]
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13
9.
Electrical Characteristics (Continued)
5V < VS < 27V, –40°C < Tj < 150°C; unless otherwise specified all values refer to GND pins.
No.
Parameters
4
EN Input Pin
4.1
Low level voltage input
4.2
High level voltage input
4.3
Pull-down resistor
4.4
Low level input current
5
Test Conditions
Pin
Symbol
Min.
EN
VENL
Max.
Unit
Type*
–0.3
+0.8
V
A
VCC +
0.3V
V
A
200
kΩ
A
+3
µA
A
VNRESL
0.14
V
A
0.14
V
A
6
ms
A
EN
VENH
2
VEN = VCC
EN
REN
50
VEN = 0V
EN
IEN
–3
Typ.
125
NRES Open Drain Output Pin
5.1
Low level output voltage
VS ≥ 5.5V
INRES = 1mA
NRES
5.2
Low level output low
10kΩ to 5V
VCC = 0V
NRES
VNRESLL
5.3
Undervoltage reset time
VS ≥ 5.5V
CNRES = 20pF
NRES
tReset
2
5.4
Reset debounce time
for falling edge
VS ≥ 5.5V
CNRES = 20pF
NRES
tres_f
1.5
10
µs
A
4V < VS < 18V
(0mA to 50mA)
VCC
VCCnor
3.234
3.366
V
A
4.5V < VS < 18V
(0mA to 85mA)
VCC
VCCnor
3.234
3.366
V
C
VS –
VDrop
3.366
V
A
200
mV
A
6
6.1
4
VCC Voltage Regulator Atmel ATA6623C
Output voltage VCC
6.2
Output voltage VCC at
low VS
3V < VS < 4V
VCC
VCClow
6.3
Regulator drop voltage
VS > 3V, IVCC = –15mA
VCC
VD1
6.4
Regulator drop voltage
VS > 3V, IVCC = –50mA
VCC
VD2
500
700
mV
A
6.5
Line regulation
4V < VS < 18V
VCC
VCCline
0.1
0.2
%
A
6.6
Load regulation
5mA < IVCC < 50mA
VCC
VCCload
0.1
0.5
%
A
6.7
Power supply ripple
rejection
10Hz to 100kHz
CVCC = 10µF
VS = 14V, IVCC = –15mA
VCC
dB
D
6.8
Output current limitation VS > 4V
mA
A
µF
D
V
A
mV
A
µs
A
0.2Ω < ESR < 5Ω at 100kHz
for phase margin ≥ 60°
50
VCC
IVCClim
–240
–160
VCC
Cload
1.8
10
2.8
6.9
External load capacity
6.10
VCC undervoltage
threshold
Referred to VCC
VS > 4V
VCC
VthunN
6.11
Hysteresis of
undervoltage threshold
Referred to VCC
VS > 4V
VCC
Vhysthun
150
6.12
Ramp up time VS > 4V CVCC = 2.2µF
to VCC = 3.3V
Iload = –5mA at VCC
VCC
tVCC
100
ESR < 0.2Ω at 100kHz
for phase margin ≥ 30°
–85
3.2
250
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
14
ATA6623C/ATA6625C [DATASHEET]
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9.
Electrical Characteristics (Continued)
5V < VS < 27V, –40°C < Tj < 150°C; unless otherwise specified all values refer to GND pins.
No.
7
7.1
Parameters
Test Conditions
Pin
Symbol
Min.
5.5V < VS < 18V
(0mA to 50mA)
VCC
VCCnor
6V < VS < 18V
(0mA to 85mA)
VCC
Typ.
Max.
Unit
Type*
4.9
5.1
V
A
VCCnor
4.9
5.1
V
C
VS – VD
5.1
V
A
250
mV
A
600
mV
A
VCC Voltage Regulator Atmel ATA6625C
Output voltage VCC
7.2
Output voltage VCC at
low VS
4V < VS < 5.5V
VCC
VCClow
7.3
Regulator drop voltage
VS > 4V, IVCC = –20mA
VCC
VD1
7.4
Regulator drop voltage
VS > 4V, IVCC = –50mA
VCC
VD2
7.5
Regulator drop voltage
VS > 3.3V, IVCC = –15mA
VCC
VD3
200
mV
A
7.6
Line regulation
5.5V < VS < 18V
VCC
VCCline
0.1
0.2
%
A
7.7
Load regulation
5mA < IVCC < 50mA
VCC
VCCload
0.1
0.5
%
A
7.8
Power supply ripple
rejection
10Hz to 100kHz
CVCC = 10µF
VS = 14V, IVCC = –15mA
VCC
dB
D
7.9
Output current limitation VS > 5.5V
mA
A
µF
D
V
A
mV
A
µs
A
0.2Ω < ESR < 5Ω at 100kHz
for phase margin ≥ 60°
400
50
VCC
IVCClim
–240
–160
VCC
Cload
1.8
10
4.2
7.10
External load capacity
7.11
VCC undervoltage
threshold
Referred to VCC
VS > 5.5V
VCC
VthunN
7.12
Hysteresis of
undervoltage threshold
Referred to VCC
VS > 5.5V
VCC
Vhysthun
250
7.13
Ramp up time
CVCC = 2.2µF
VS > 5.5V to VCC = 5V Iload = –5mA at VCC
VCC
tVCC
130
8
ESR < 0.2Ω at 100kHz
for phase margin ≥ 30°
–85
4.8
300
LIN Bus Driver: Bus Load Conditions:
Load 1 (Small): 1nF, 1kΩ, Load 2 (Large): 10nF, 500Ω, Internal Pull-up RRXD = 5kΩ, CRXD = 20pF,
Load 3 (Medium): 6.8nF, 660Ω, Characterized on Samples
10.6 and 10.7 Specifies the Timing Parameters for Proper Operation at 20kBit/s and 10.8 and 10.9 at 10.4kBit/s
8.1
Driver recessive output
Load1/Load2
voltage
LIN
VBUSrec
8.2
Driver dominant voltage VVS = 7V, Rload = 500Ω
LIN
V_LoSUP
8.3
Driver dominant voltage VVS = 18V, Rload = 500Ω
LIN
V_HiSUP
8.4
Driver dominant voltage VVS = 7V, Rload = 1000Ω
LIN
V_LoSUP_1k
0.6
8.5
Driver dominant voltage VVS = 18V, Rload = 1000Ω
LIN
V_HiSUP_1k
0.8
8.6
Pull–up resistor to VS
The serial diode is
mandatory
LIN
RLIN
20
8.7
Voltage drop at the
serial diodes
In pull-up path with Rslave
ISerDiode = 10mA
LIN
VSerDiode
0.4
8.8
LIN current limitation
VBUS = VBatt_max
LIN
IBUS_lim
40
0.9 × VS
30
120
VS
V
A
1.2
V
A
2
V
A
V
A
V
A
60
kΩ
A
1.0
V
D
200
mA
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
ATA6623C/ATA6625C [DATASHEET]
4957L–AUTO–09/14
15
9.
Electrical Characteristics (Continued)
5V < VS < 27V, –40°C < Tj < 150°C; unless otherwise specified all values refer to GND pins.
No.
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
8.9
Input leakage current at
the receiver including
pull-up resistor as
specified
Input Leakage current
Driver off
VBUS = 0V
VBatt = 12V
LIN
IBUS_PAS_do
–1
–0.35
8.10
Leakage current LIN
recessive
Driver off
8V < VBatt < 18V
8V < VBUS < 18V
VBUS ≥ VBatt
LIN
IBUS_PAS_rec
8.11
Leakage current when
control unit
disconnected from
ground. Loss of local
ground must not affect
communication in the
residual network
GNDDevice = VS
VBatt = 12V
0V < VBUS < 18V
LIN
IBUS_NO_gnd
8.12
Leakage current at
disconnected battery.
Node has to sustain the
VBatt disconnected
current that can flow
VSUP_Device = GND
under this condition.
0V < VBUS < 18V
Bus must remain
operational under this
condition.
LIN
IBUS_NO_bat
8.13
Capacitance on Pin LIN
to GND
LIN
CLIN
LIN
VBUS_CNT
0.475 ×
VS
Max.
Unit
Type*
mA
A
m
–10
10
20
µA
A
+0.5
+10
µA
A
0.1
2
µA
A
20
pF
D
0.525 ×
VS
V
A
9
LIN Bus Receiver
9.1
Center of receiver
threshold
9.2
Receiver dominant state VEN = 5V
LIN
VBUSdom
–27
0.4 × VS
V
A
9.3
Receiver recessive
state
VEN = 5V
LIN
VBUSrec
0.6 × VS
40
V
A
9.4
Receiver input
hysteresis
Vhys = Vth_rec – Vth_dom
LIN
VBUShys
0.028 ×
VS
0.175 ×
VS
V
A
9.5
Pre-wake detection LIN
High level input voltage
LIN
VLINH
VS – 2V
VS +
0.3V
V
A
9.6
Pre-wake detection LIN
Activates the LIN receiver
Low level input voltage
LIN
VLINL
–27
VS –
3.3V
V
A
10
Internal Timers
150
µs
A
20
µs
A
15
µs
A
VBUS_CNT =
(Vth_dom + Vth_rec)/2
10.1
Dominant time for
wake–up via LIN bus
VLIN = 0V
LIN
tbus
30
10.2
Time delay for mode
change from Fail-safe
into normal mode via
pin EN
VEN = 5V
EN
tnorm
5
10.3
Time delay for mode
change from normal
V = 0V
mode to sleep mode via EN
pin EN
EN
tsleep
2
0.5 ×
VS
0.1 x VS
90
7
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
16
ATA6623C/ATA6625C [DATASHEET]
4957L–AUTO–09/14
9.
Electrical Characteristics (Continued)
5V < VS < 27V, –40°C < Tj < 150°C; unless otherwise specified all values refer to GND pins.
No.
Parameters
10.4
10.5
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
TXD dominant time out
VTXD = 0V
time
TXD
tdom
6
13
20
ms
A
Time delay for mode
change from silent
V = 5V
mode into normal mode EN
via EN
EN
ts_n
5
15
40
µs
A
Duty cycle 1
THRec(max) = 0.744 × VS
THDom(max) = 0.581 × VS
VS = 7.0V to 18V
tBit = 50µs
D1 = tbus_rec(min)/(2 × tBit)
LIN
D1
0.396
Duty cycle 2
THRec(min) = 0.422 × VS
THDom(min) = 0.284 × VS
VS = 7.6V to 18V
tBit = 50µs
D2 = tbus_rec(max)/(2 × tBit)
LIN
D2
Duty cycle 3
THRec(max) = 0.778 × VS
THDom(max) = 0.616 × VS
VS = 7.0V to 18V
tBit = 96µs
D3 = tbus_rec(min)/(2 × tBit)
LIN
D3
10.9
Duty cycle 4
THRec(min) = 0.389 × VS
THDom(min) = 0.251 × VS
VS = 7.6V to 18V
tBit = 96µs
D4 = tbus_rec(max)/(2 × tBit)
LIN
D4
10.10
Slope time falling and
rising edge at LIN
VS = 7.0V to 18V
LIN
tSLOPE_fall
tSLOPE_rise
10.6
10.7
10.8
11
Test Conditions
A
0.581
A
0.417
A
0.590
3.5
A
22.5
µs
A
6
µs
A
+2
µs
A
Receiver Electrical AC Parameters of the LIN Physical Layer
LIN Receiver, RXD Load Conditions: CRXD = 20pF
11.1
Propagation delay of
receiver Figure 9-1
VS = 7.0V to 18V
trx_pd = max(trx_pdr , trx_pdf)
11.2
Symmetry of receiver
V = 7.0V to 18V
propagation delay rising S
trx_sym = trx_pdr – trx_pdf
edge minus falling edge
RXD
trx_pd
RXD
trx_sym
–2
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
ATA6623C/ATA6625C [DATASHEET]
4957L–AUTO–09/14
17
Figure 9-1. Definition of Bus Timing Characteristics
tBit
tBit
tBit
TXD
(Input to transmitting node)
tBus_dom(max)
tBus_rec(min)
Thresholds of
THRec(max)
VS
(Transceiver supply
of transmitting node)
receiving node1
THDom(max)
LIN Bus Signal
Thresholds of
receiving node2
THRec(min)
THDom(min)
tBus_dom(min)
tBus_rec(max)
RXD
(Output of receiving node1)
trx_pdf(1)
trx_pdr(1)
RXD
(Output of receiving node2)
trx_pdr(2)
18
ATA6623C/ATA6625C [DATASHEET]
4957L–AUTO–09/14
trx_pdf(2)
Figure 9-2. Application Circuit
VCC
1
ATA6623/25
VBAT
VS
VCC
RXD 5
Master
node
pull-up
Normal
Mode
Receiver
+
100nF
22μF
1kΩ
+
4
LIN-BUS
RF filter
LIN
220pF
VCC
Microcontroller
Wake-up bus timer
TXD
EN
6
TXD
Time-out
timer
Slew rate control
2
Control
unit
GND
3
Short circuit and
overtemperature
protection
Sleep
mode
VCC
switched
off
Normal/Silent/
Fail-safe Mode
3.3V/5V
8
VCC
7
NRES
10kΩ
Undervoltage reset
100nF
10μF
GND
ATA6623C/ATA6625C [DATASHEET]
4957L–AUTO–09/14
19
10.
Ordering Information
Extended Type Number
Package
Remarks
ATA6623C-GAQW
SO8
3.3V LIN system basis chip, Pb-free, 4k, taped and reeled
ATA6625C-GAQW
SO8
5V LIN system basis chip, Pb-free, 4k, taped and reeled
11.
Package Information
E1
L
A
b
A2
A1
C
D
e
8
E
5
technical drawings
according to DIN
specifications
Dimensions in mm
1
4
COMMON DIMENSIONS
Pin 1 identity
(Unit of Measure = mm)
Symbol
MIN
NOM
MAX
A
1.5
1.65
1.8
A1
A2
0.1
1.4
0.15
1.47
0.25
1.55
D
4.8
4.9
5
E
5.8
6
6.2
E1
3.8
3.9
4
L
0.4
0.65
0.9
C
0.15
0.2
0.25
b
e
0.3
0.4
1.27 BSC
0.5
NOTE
05/08/14
TITLE
Package Drawing Contact:
[email protected]
20
Package: SO8
ATA6623C/ATA6625C [DATASHEET]
4957L–AUTO–09/14
GPC
DRAWING NO.
REV.
6.543-5185.01-4
1
12.
Revision History
Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this
document.
Revision No.
History
4957L-AUTO-09/14
• Section 10 “Ordering Information” on page 20 updated
4957K-AUTO-02/13
• Section 10 “Ordering Information” on page 20 updated
4957J-AUTO-11/12
• Section 10 “Ordering Information” on page 20 updated
• Features on page 1 changed
• Section 1 “Description” on pages 1 to 2 changed
• Table 2-1 “Pin Description” on page 2 changed
4957I-AUTO-03/11
• Section 3 “Functional Description” on pages 3 to 4 changed
• Section 4 “Modes of Operation” on pages 5 to 9 changed
• Section 6 “Voltage Regulator” on pages 11 to 12 changed
• Section 7 “Absolute Maximum Ratings” on page 13 changed
• Section 8 “Electrical Characteristics” on pages 14 to 16 changed
• New Part numbers ATA6623C and ATA6625C added
• Features on page 1 changed
• Text under heading 3.3 on page 3 changed
4957H-AUTO-05/10
• Text under heading 3.9 on page 4 changed
• Abs.Max.Rat.Table -> Values in row “ESD HBM following....” changed
• El.Char.Table -> rows changed: 5.1, 5.2, 6.5, 6.6, 6.7, 6.8, 7.6, 7.7, 7.8,7.9, 10.2
• El.Char.Table -> row 8.13 added
• Ord.Info.Table -> Part numbers ATA6623C and ATA6625C added
• Figures changed: 1-1, 4-2, 4-3, 4-4, 4-5, 6-2, 9-2
• Sections changed: 3.1, 3.6, 3.8, 3.9, 3.10, 4.1, 4.2, 4.3, 5
4957G-AUTO-09/09
• Description Text changed
• Table 4-1 changed
• Abs. Max. Ratings table changed
• El. Characteristics table changed
• “Pre-normal Mode” in “Fail-safe Mode” changed
4957F-AUTO-02/08
• Section 7 “Absolute Maximum Ratings” on page 13 changed
• Section 8 “Electrical Characteristics” numbers 10.5 to 10.10 on pages 17 to 18 changed
4957E-AUTO-10/07
• Section 9 “Ordering Information” on page 20 changed
• Features changed
• Block diagram changed
• Application diagram changed
4957D-AUTO-07/07
• Text changed under the headings:
3.2, 3.3, 3.4, 3.6, 3.7, 3.8, 3.9, 4, 4.1, 4.2, 4.3, 4.4, 4.5, 5.5, 5.6, 6
• Figure 4-2, 4-3, 4-4, 4-5, 8-2: changed
• Figure title 6-1: text changed
• Abs. Max. Ratings: row “Output current NRES” added
• El. Char. table: values changed in the following rows:
1.3, 5.1, 5.3, 5.4, 6.9, 6.12, 7.9, 11.1
ATA6623C/ATA6625C [DATASHEET]
4957L–AUTO–09/14
21
XXXXXX
Atmel Corporation
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© 2014 Atmel Corporation. / Rev.: Rev.: 4957L–AUTO–09/14
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