ATA6625 LIN Bus Transceiver with Integrated Voltage Regulator DATASHEET Features ● Supply voltage up to 40V ● Operating voltage VS = 5V to 28V ● Typically 9µA supply current during sleep mode ● Typically 47µA Supply current in silent mode ● Very low current consumption at low supply voltages (2V < VS < 5.5V): typically 130µA ● Linear low-drop voltage regulator, 85mA current capability: ● MLC (multi-layer ceramic) capacitor with 0 ESR ● Normal, fail-safe, and silent mode: ● VCC = 5.0V ±2% ● Sleep mode: VCC is switched off ● VCC undervoltage detection with reset open drain output NRES (4ms reset time) ● Voltage regulator is short-circuit and over-temperature protected ● LIN physical layer according to LIN 2.0, 2.1, 2.2, 2.2A and SAEJ2602-2 ● Wake-up capability via LIN bus (100µs dominant) ● TXD time-out timer ● Bus pin is overtemperature and short-circuit protected versus GND and battery ● Advanced EMC and ESD performance ● Fulfills the OEM “Hardware Requirements for LIN in Automotive Applications Rev1.3” ● Interference and damage protection according to ISO7637 ● Qualified according to AEC-Q100 ● Package: SO8 9376A-AUTO-01/16 1. Description The Atmel® ATA6625 is a fully integrated LIN transceiver, designed according to the LIN specification 2.0 and 2.1, with a low-drop voltage regulator (5V/85mA). The combination of voltage regulator and bus transceiver makes it possible to develop simple, but powerful, slave nodes in LIN Bus systems. The Atmel ATA6625 is designed to handle the low-speed data communication in vehicles (for example, in convenience electronics). Improved slope control at the LIN driver ensures secure data communication up to 20kBaud. The bus output is designed to withstand high voltage. Sleep mode (voltage regulator switched off) and silent mode (communication off; VCC voltage on) guarantee minimized current consumption. Figure 1-1. Block Diagram ATA6625 VCC - 5 VS 4 LIN 8 VCC 7 NRES Normal and Fail-safe Mode Receiver RXD 1 + RF-filter VCC Wake-up bus timer TXD EN 6 TXD Time-out timer Slew rate control 2 Control unit GND 3 Short circuit and overtemperature protection Sleep mode VCC switched off Normal/Silent/ Fail-safe Mode 5V Undervoltage reset 2 ATA6625 [DATASHEET] 9376A–AUTO–01/16 2. Pin Configuration Figure 2-1. Pinning VS EN GND LIN Table 2-1. 1 2 3 4 8 7 SO8 6 5 VCC NRES TXD RXD Pin Description Pin Symbol Function 1 VS Battery supply 2 EN Enables normal mode if the input is high 3 GND 4 LIN LIN bus line input/output 5 RXD Receive data output 6 TXD Transmit data input 7 NRES 8 VCC Ground, heat sink Output undervoltage reset, low at reset Output voltage regulator 5V/85mA 3. Functional Description 3.1 Physical Layer Compatibility Since the LIN physical layer is independent from higher LIN layers (e.g., LIN protocol layer), all nodes with a LIN physical layer according to revision 2.x can be mixed with LIN physical layer nodes, which are according to older versions (i.e., LIN 1.0, LIN 1.1, LIN 1.2, LIN 1.3) without any restrictions. 3.2 Supply Pin (VS) LIN operating voltage is VS = 5V to 28V. An undervoltage detection is implemented to disable transmission if VS falls below 5V, in order to avoid false bus messages. After switching on VS, the IC starts with the fail-safe mode and the voltage regulator is switched on. The supply current in sleep mode is typically 9µA and 47µA in silent mode. 3.3 Ground Pin (GND) The IC does not affect the LIN Bus in the event of GND disconnection. It is able to handle a ground shift up to 11.5% of VS. 3.4 Voltage Regulator Output Pin (VCC) The internal 5V voltage regulator is capable of driving loads up to 85mA, supplying the microcontroller and other ICs on the PCB and is protected against overload by means of current limitation and overtemperature shut-down. Furthermore, the output voltage is monitored and will cause a reset signal at the NRES output pin if it drops below a defined threshold Vthun. ATA6625 [DATASHEET] 9376A–AUTO–01/16 3 3.5 Undervoltage Reset Output (NRES) If the VCC voltage falls below the undervoltage detection threshold of Vthun, NRES switches to low after tres_f (Figure 6-1 on page 11). Even if VCC = 0V the NRES stays low, because it is internally driven from the VS voltage. If VS voltage ramps down, NRES stays low until VS < 1.5V and then becomes highly resistant. The implemented undervoltage delay keeps NRES low for tReset = 4ms after VCC reaches its nominal value. 3.6 Bus Pin (LIN) A low-side driver with internal current limitation and thermal shutdown as well as an internal pull-up resistor according to LIN specification 2.x is implemented. The voltage range is from –27V to +40V. This pin exhibits no reverse current from the LIN bus to VS, even in the event of a GND shift or VBatt disconnection. The LIN receiver thresholds are compatible with the LIN protocol specification. The fall time (from recessive to dominant) and the rise time (from dominant to recessive) are slope controlled. 3.7 Input Pin (TXD) In normal mode the TXD pin is the microcontroller interface to control the state of the LIN output. TXD must be pulled to ground in order to drive the LIN bus low. If TXD is high or unconnected (internal pull-up resistor), the LIN output transistor is turned off and the bus is in the recessive state. 3.8 Dominant Time-out Function (TXD) The TXD input has an internal pull-up resistor. An internal timer prevents the bus line from being driven permanently in the dominant state. If TXD is forced to low longer than tdom (typ. 40ms), the LIN bus driver is switched to the recessive state. To reactivate the LIN bus driver, switch TXD to high (> 10µs). 3.9 Output Pin (RXD) In normal mode this pin reports the state of the LIN bus to the microcontroller. LIN high (recessive state) is indicated by a high level at RXD; LIN low (dominant state) is indicated by a low level at RXD. The output is a push-pull stage switching between VCC and GND. The AC characteristics are measured by an external load capacitor of 20pF. In silent mode the RXD output switches to high. 3.10 Enable Input Pin (EN) The Enable Input pin controls the operation mode of the device. If EN is high, the circuit is in normal mode, with transmission paths from TXD to LIN and from LIN to RXD both active. The VCC voltage regulator operates with 5V/85mA output capability. If EN is switched to low while TXD is still high, the device is forced to silent mode. No data transmission is then possible, and the current consumption is reduced to IVS typ. 47µA. The VCC regulator has its full functionality. If EN is switched to low while TXD is low, the device is forced to sleep mode. No data transmission is possible, and the voltage regulator is switched off. 4 ATA6625 [DATASHEET] 9376A–AUTO–01/16 4. Modes of Operation Figure 4-1. Modes of Operation a: VS > 2.4V Unpowered Mode VBatt = 0V b: VS < 1.9V c: Bus wake-up event d: NRES switches to low e: VS < 3.9V a b Fail-safe Mode b b VCC: 5V with undervoltage monitoring Communication: OFF d, e EN = 1 c+d EN = 1 c Go to silent command b EN = 0 Silent Mode TXD = 1 VCC: 5V with undervoltage monitoring Communication: OFF Local wake-up event Normal Mode EN = 1 VCC: 5V with undervoltage monitoring Go to sleep command EN = 0 Communication: ON Sleep Mode TXD = 0 VCC: switched off Communication: OFF Table 4-1. Modes of Operation Mode of Operation 4.1 Transceiver VCC RXD LIN Recessive Fail safe OFF 5V High, Except after wake-up Normal ON 5V LIN depending TXD depending Silent OFF 5V High Recessive Sleep OFF 0V 0V Recessive Normal Mode This is the normal transmitting and receiving mode of the LIN Interface, in accordance with LIN specification 2.x. The VCC voltage regulator operates with a 5V output voltage, with a low tolerance of ±2% and a maximum output current of 85mA. If an undervoltage condition occurs, NRES is switched to low and the IC changes its state to fail-safe mode. ATA6625 [DATASHEET] 9376A–AUTO–01/16 5 4.2 Silent Mode A falling edge at EN while TXD is high switches the IC into silent mode. The TXD Signal has to be logic high during the mode select window (Figure 4-2 on page 6). The transmission path is disabled in silent mode. The overall supply current from VBatt is a combination of the IVSsi = 47µA plus the VCC regulator output current IVCC. In silent mode the internal slave termination between pin LIN and pin VS is disabled, and only a weak pull-up current (typically 9µA) between pin LIN and pin VS is present. The silent mode can be activated independently from the current level on pin LIN. If an undervoltage condition occurs, NRES is switched to low and the IC changes its state to fail-safe mode. A voltage less than the LIN Pre-wake detection VLINL at pin LIN activates the internal LIN receiver and starts the wake-up detection timer. A falling edge at the LIN pin followed by a dominant bus level maintained for a certain time period (> tbus) and the following rising edge at pin LIN (see Figure 4-3 on page 7) results in a remote wake-up request. The device switches from silent mode to fail-safe mode, the voltage regulator remains on and the internal LIN slave termination resistor between the LIN pin and the VS pin is switched on. The remote wake-up request is indicated by a low level at pin RXD to interrupt the microcontroller (Figure 4-3 on page 7). EN high can be used to switch directly to normal mode. Figure 4-2. Switch to Silent Mode Normal Mode Silent Mode EN TXD Mode select window td = 3.2μs NRES VCC Delay time silent mode td_silent maximum 20μs LIN LIN switches directly to recessive mode 6 ATA6625 [DATASHEET] 9376A–AUTO–01/16 Figure 4-3. LIN Wake-up Waveform Diagram from Silent Mode Bus wake-up filtering time tbus Fail-safe mode Normal mode LIN bus RXD VCC High Low Silent mode 5V Fail-safe mode 5V Normal mode EN High EN NRES 4.3 Undervoltage detection active Sleep Mode A falling edge at EN while TXD is low switches the IC into sleep mode. The TXD Signal has to be logic low during the mode select window (Figure 4-4 on page 8). To avoid influencing the LIN-pin during the switch to sleep mode, it is possible to switch the EN up to 3.2µs earlier to LOW than the TXD. Even if the two falling edges at TXD and EN occur at the same time, the LIN line will remain uninfluenced. In sleep mode the transmission path is disabled. The supply current IVSsleep from VBatt is typically 9µA. The VCC regulator is switched off, NRES and RXD are low. The internal slave termination between pin LIN and pin VS is disabled, only a weak pull-up current (typically 10µA) between pin LIN and pin VS is present. sleep mode can be activated independently from the current level on pin LIN. A voltage less than the LIN Pre-wake detection VLINL at pin LIN activates the internal LIN receiver and starts the wake-up detection timer. A falling edge at the LIN pin followed by a dominant bus level maintained for a certain time period (> tbus) and a following rising edge at pin LIN results in a remote wake-up request. The device switches from sleep mode to fail-safe mode. The VCC regulator is activated and the internal LIN slave termination resistor between the LIN pin and the VS pin is switched on. The remote wake-up request is indicated by a low level at the RXD pin to interrupt the microcontroller (Figure 4-5 on page 8). EN high can be used to switch directly from sleep to fail-safe mode. If EN is still high after VCC ramp up and undervoltage reset time, the IC switches to normal mode. ATA6625 [DATASHEET] 9376A–AUTO–01/16 7 Figure 4-4. Switch to Sleep Mode Normal Mode Sleep Mode EN Mode select window TXD td = 3.2μs NRES VCC Delay time sleep mode td_sleep = maximum 20μs LIN LIN switches directly to recessive mode Figure 4-5. LIN Wake-up Diagram from Sleep Mode Bus wake-up filtering time tbus Fail-safe Mode Low Low Normal Mode LIN bus RXD VCC voltage regulator On state Off state Regulator wake-up time EN High EN Reset time NRES Low Microcontroller start-up time delay 8 ATA6625 [DATASHEET] 9376A–AUTO–01/16 4.4 Fail-safe Mode At system power-up the device automatically switches to fail-safe mode. The voltage regulator is switched on (see Figure 61 on page 11). The NRES output switches to low for tres = 4ms and gives a reset to the microcontroller. LIN communication is switched off. The IC stays in this mode until EN is switched to high, and changes then to the normal mode. A power down of VBatt (VS < 1.9V) during silent or sleep mode switches the IC into the unpowered mode after power up. A logic low at NRES switches the IC into fail-safe mode directly. 4.5 Unpowered Mode If you connect battery voltage to the application circuit, the voltage at the VS pin increases according to the block capacitor (see Figure 6-1 on page 11). After VS is higher than 2.4V, the IC mode changes from unpowered mode to fail-safe mode. The VCC output voltage reaches its nominal value after tVCC. This time, tVCC, depends on the VCC capacitor and the load. NRES is low for the reset time delay tReset; no mode change is possible during this time. ATA6625 [DATASHEET] 9376A–AUTO–01/16 9 5. 10 Fail-safe Features ● During a short-circuit at LIN to VBattery, the output limits the output current to IBUS_lim. Due to the power dissipation, the chip temperature exceeds TLINoff and the LIN output is switched off. The chip cools down and after a hysteresis of Thys, switches the output on again. RXD stays on high because LIN is high. During LIN overtemperature switch-off, the VCC regulator is working independently. ● During a short-circuit from LIN to GND the IC can be switched into sleep or silent mode. If the short-circuit disappears, the IC starts with a remote wake-up. ● The reverse current is very low < 2µA at pin LIN during loss of VBatt. This is optimal behavior for bus systems where some slave nodes are supplied from battery or ignition. ● During a short circuit at VCC, the output limits the output current to IVCClim. Because of undervoltage, NRES switches to low and sends a reset to the microcontroller. The IC switches into fail-safe mode. If the chip temperature exceeds the value TVCCoff, the VCC output switches off. The chip cools down and after a hysteresis of Thys, switches the output on again. Because of fail-safe mode, the VCC voltage will switch on again although EN is switched off from the microcontroller. The microcontroller can then start with normal operation. ● ● ● ● ● Pin EN provides a pull-down resistor to force the transceiver into recessive mode if EN is disconnected. Pin RXD is set floating if VBatt is disconnected. Pin TXD provides a pull-up resistor to force the transceiver into recessive mode if TXD is disconnected. If TXD is short-circuited to GND, it is possible to switch to sleep mode via ENABLE after tdom > 20ms. If the TXD pin stays at GND level while switching into normal mode, it must be pulled to high level longer than 10µs before the LIN driver can be activated. This feature prevents the bus line from being accidentally driven to dominant state after normal mode has been activated (e.g., in the case of a short circuit at TXD to GND). ATA6625 [DATASHEET] 9376A–AUTO–01/16 Voltage Regulator Figure 6-1. VCC Voltage Regulator: Ramp Up and Undervoltage VS 12V 5.5V VCC 5V Vthun tVCC tReset tres_f NRES 5V The voltage regulator needs an external capacitor for compensation and to smooth the disturbances from the microcontroller. It is recommended to use an MLC capacitor with C > 1.8µF and a ceramic capacitor with C = 100nF. The values of these capacitors can be varied by the customer, depending on the application. With this special SO8 package (fused lead frame to pin 3) an Rthja of 80K/W is achieved. Therefore, it is recommended to connect pin 3 with a wide GND plate on the printed board to get a good heat sink. The main power dissipation of the IC is created from the VCC output current IVCC, which is needed for the application. Figure 6-2 shows the safe operating area of the Atmel® ATA6625 in the SO8 package. Figure 6-2. SO8 Package Power Dissipation: Safe Operating Area: VCC Output Current versus Supply Voltage VS at Different Ambient Temperatures Due to Rthja = 80K/W 90 80 70 IVCC (mA) 6. 60 Tamb = 85°C 50 40 Tamb = 95°C 30 Tamb = 105°C Tamb = 115°C 20 10 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 VS (V) To program the microcontroller it may be necessary to supply the VCC output via an external power supply while the VS Pin of the system basis chip is disconnected. This will not affect the system basis chip. ATA6625 [DATASHEET] 9376A–AUTO–01/16 11 7. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol Min. Supply voltage VS VS –0.3 Pulse time ≤ 500ms Ta = 25°C Output current IVCC ≤ 85mA Pulse time ≤ 2min Ta = 25°C Output current IVCC ≤ 85mA Max. Unit +40 V VS +43.5 V VS 28 V +5.5 V +2 mA –27 +40 +43.5 V V –0.3 +5.5 +200 V mA Logic pins (RxD, TxD, EN, NRES) Typ. –0.3 Output current NRES INRES LIN - DC voltage - Pulse time < 500ms VLIN VCC - DC voltage - DC input current ESD according to IBEE LIN EMC Test specification 1.0 following IEC 61000-4-2 - Pin VS, LIN to GND ±6 KV ESD HBM following STM5.1 with 1.5k/100pF - Pin VS, LIN to GND ±6 KV ±3 KV CDM ESD STM 5.3.1 ±750 V Machine Model ESD AEC-Q100-RevF(003) ±200 V HBM ESD ANSI/ESD-STM5.1 JESD22-A114 AEC-Q100 (002) Junction temperature Tj –40 +150 °C Storage temperature Ts –55 +150 °C 8. Thermal Characteristics Parameters Package Symbol Heat sink at GND (pin 3) on PCB SO8 Rthja Thermal shutdown of VCC regulator SO8 TVCCoff 150 165 180 °C Thermal shutdown of LIN output SO8 TLINoff 150 165 180 °C Thermal shutdown hysteresis SO8 Thys 12 ATA6625 [DATASHEET] 9376A–AUTO–01/16 Min. Typ. Max. 80 10 Unit K/W °C 9. Electrical Characteristics 5V < VS < 28V, –40°C < Tj < 150°C; unless otherwise specified all values refer to GND pins. No. 1 1.1 Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* VS VS 5 13.5 28 V A VS IVSsleep 6 9 12 µA B VS IVSsleep 3 10 15 µA A Sleep mode, VLIN = 0V bus shorted to GND VS < 14V VS IVSsleep_short 20 50 100 µA A Bus recessive 5.5V< VS < 14V without load at VCC T = 27°C VS IVSsilent 30 47 58 µA B Bus recessive 5.5V< VS < 14V without load at VCC VS IVSsilent 30 50 64 µA A Bus recessive 2.0V< VS < 5,5V without load at VCC VS IVSsilent 50 130 170 µA A Silent mode 5.5V< VS < 14V bus shorted to GND without load at VCC VS IVSsilent_short 50 80 120 µA A VS Pin Nominal DC voltage range Sleep mode VLIN > VS – 0.5V VS < 14V, T = 27°C 1.2 1.3 Sleep mode Supply current in sleep VLIN > VS – 0.5V mode VS < 14V Supply current in silent mode (SBC) / Active mode (voltage regulator) 1.4 Supply current in normal mode Bus recessive VS < 14V without load at VCC VS IVSrec 150 230 300 µA A 1.5 Supply current in normal mode Bus dominant (internal LIN pull-up resistor active) VS < 14V without load at VCC VS IVSdom 200 700 950 µA A Bus recessive 5.5V < VS < 14V without load at VCC VS IVSfail 40 55 80 µA A Bus recessive 2.0V < VS < 5.5V without load at VCC VS IVSfail 50 130 170 µA A 1.7 VS undervoltage threshold (switching from normal to fail-safe mode) VS VSth 3.9 4.4 4.9 V A 1.8 VS undervoltage threshold hysteresis VS VSth_hys 0.1 0.25 0.4 V A 1.6 Supply current in fail-safe mode *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter ATA6625 [DATASHEET] 9376A–AUTO–01/16 13 9. Electrical Characteristics (Continued) 5V < VS < 28V, –40°C < Tj < 150°C; unless otherwise specified all values refer to GND pins. No. Parameters 1.9 1.10 2 Test Conditions Pin Symbol Min. Typ. Max. Unit Type* VS operation threshold (switching to unpowered mode) VS VSth_U 1.9 2.15 2.4 V A VS undervoltage threshold hysteresis VS VSth_hys_U 0.1 0.2 0.3 V A 0.2 0.4 V A V A RXD Output Pin 2.1 Low level output sink capability Normal mode VLIN = 0V IRXD = 2mA RXD VRXDL 2.2 Normal mode High level output source VLIN = VS capability IRXD = –2mA RXD VRXDH VCC – 0.4V TXD VTXDL –0.3 +0.8 V A VCC + 0.3V V A 100 k A 3 3.1 TXD Input Pin Low level voltage input 3.2 High level voltage input 3.3 Pull-up resistor 3.4 High level leakage current 4 VCC – 0.2V TXD VTXDH 2 VTXD = 0V TXD RTXD 40 VTXD = VCC TXD ITXD –3 +3 µA A 70 EN Input Pin 4.1 Low level voltage input EN VENL –0.3 +0.8 V A 4.2 High level voltage input EN VENH 2 VCC + 0.3V V A 4.3 Pull-down resistor VEN = VCC EN REN 50 200 k A 4.4 Low level input current VEN = 0V EN IEN –3 +3 µA A VNRESL 0.25 V A 0.14 V D 6 ms A 5 125 NRES Open Drain Output Pin 5.1 Low level output voltage VS ≥ 5.5V INRES = 2mA NRES 5.2 Low level output low 10k to 5V VCC = 0V NRES VNRESLL 5.3 Undervoltage reset time VS ≥ 5.5V CNRES = 20pF NRES tReset 2 5.4 Reset debounce time for falling edge VS ≥ 5.5V CNRES = 20pF NRES tres_f 1.5 10 µs A 5.5 Switch off leakage current VNRES = 5.5V NRES INRES_Lf –3 +3 µA A 5.5V < VS < 18V (0mA to 50mA) VCC VCCnor 4.9 5.1 V A 6V < VS < 18V (0mA to 85mA) VCC VCCnor 4.9 5.1 V C VS – VD 5.1 V A 200 mV A 7 7.1 4 VCC Voltage Regulator Output voltage VCC 7.2 Output voltage VCC at low VS 4V < VS < 5.5V VCC VCClow 7.3 Regulator drop voltage VS > 4V, IVCC = –20mA VCC VD1 100 *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 14 ATA6625 [DATASHEET] 9376A–AUTO–01/16 9. Electrical Characteristics (Continued) 5V < VS < 28V, –40°C < Tj < 150°C; unless otherwise specified all values refer to GND pins. No. Parameters Test Conditions Pin Symbol 7.4 Regulator drop voltage VS > 4V, IVCC = –50mA VCC VD2 7.5 Regulator drop voltage VS > 3.3V, IVCC = –15mA VCC VD3 7.6 Line regulation 5.5V < VS < 18V VCC VCCline 0.1 7.7 Load regulation 5mA < IVCC < 50mA VCC VCCload 0.1 7.8 Power supply ripple rejection 10Hz to 100kHz CVCC = 10µF VS = 14V, IVCC = –15mA VCC 7.9 Output current limitation VS > 5.5V VCC IVCClim 7.10 External load capacity MLC capacitor VCC Cload 1.8 7.11 VCC undervoltage threshold Referred to VCC VS > 5.5V VCC VthunN 4.2 7.12 Hysteresis of undervoltage threshold Referred to VCC VS > 5.5V VCC Vhysthun 250 7.13 Ramp up time CVCC = 2.2µF VS > 5.5V to VCC = 5V Iload = –5mA at VCC VCC tVCC 1 8 Min. Typ. Max. Unit Type* 300 500 mV A 150 mV A 0.2 % A 0.5 % A dB D mA A µF D V A mV A ms A 50 –180 –120 10 4.8 1.5 LIN Bus Driver: Bus Load Conditions: Load 1 (Small): 1nF, 1k, Load 2 (Large): 10nF, 500, CRXD = 20pF, Load 3 (Medium): 6.8nF, 660, Characterized on Samples 10.6 and 10.7 Specifies the Timing Parameters for Proper Operation at 20kBit/s and 10.8 and 10.9 at 10.4kBit/s 8.1 Driver recessive output Load1/Load2 voltage LIN VBUSrec 8.2 Driver dominant voltage VVS = 7V, Rload = 500 LIN 8.3 Driver dominant voltage VVS = 18V, Rload = 500 LIN 8.4 Driver dominant voltage VVS = 7V, Rload = 1000 LIN V_LoSUP_1k 8.5 Driver dominant voltage VVS = 18V, Rload = 1000 LIN 8.6 Pull–up resistor to VS The serial diode is mandatory 8.7 Voltage drop at the serial diodes In pull-up path with Rslave ISerDiode = 10mA 8.8 LIN current limitation VBUS = VBatt_max 8.9 Input leakage current at the receiver including pull-up resistor as specified 0.9 VS VS V A V_LoSUP 1.2 V A V_HiSUP 2 V A 0.6 V A V_HiSUP_1k 0.8 V A LIN RLIN 20 47 k A LIN VSerDiode 0.4 1.0 V D LIN IBUS_lim 40 120 200 mA A Input Leakage current Driver off VBUS = 0V VBatt = 12V LIN IBUS_PAS_ –1 –0.35 mA A 8.10 Leakage current LIN recessive Driver off 8V < VBatt < 18V 8V < VBUS < 18V VBUS ≥ VBatt LIN IBUS_PAS_rec 8.11 Leakage current when control unit disconnected from ground. Loss of local ground must not affect communication in the residual network GNDDevice = VS VBatt = 12V 0V < VBUS < 18V LIN IBUS_NO_gnd 30 dom –10 10 20 µA A +0.5 +10 µA A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter ATA6625 [DATASHEET] 9376A–AUTO–01/16 15 9. Electrical Characteristics (Continued) 5V < VS < 28V, –40°C < Tj < 150°C; unless otherwise specified all values refer to GND pins. No. Parameters Test Conditions Pin Symbol Min. 8.12 Leakage current at disconnected battery. Node has to sustain the VBatt disconnected current that can flow VSUP_Device = GND under this condition. 0V < VBUS < 18V Bus must remain operational under this condition. LIN IBUS_NO_bat 8.13 Capacitance on Pin LIN to GND LIN CLIN LIN VBUS_CNT 0.475 VS Typ. Max. Unit Type* 0.1 2 µA A 20 pF D 0.525 VS V A 9 LIN Bus Receiver 9.1 Center of receiver threshold 9.2 Receiver dominant state VEN = 5V LIN VBUSdom –27 0.4 VS V A 9.3 Receiver recessive state VEN = 5V LIN VBUSrec 0.6 VS 40 V A 9.4 Receiver input hysteresis Vhys = Vth_rec – Vth_dom LIN VBUShys 0.028 VS 0.175 VS V A 9.5 Pre-wake detection LIN High level input voltage LIN VLINH VS – 2V VS + 0.3V V A 9.6 Pre-wake detection LIN Activates the LIN receiver Low level input voltage LIN VLINL –27 VS – 3.3V V A 10 Internal Timers 150 µs A 20 µs A VBUS_CNT = (Vth_dom + Vth_rec)/2 0.5 VS 0.1 x VS 10.1 Dominant time for wake–up via LIN bus VLIN = 0V LIN tbus 50 10.2 Time delay for mode change from Fail-safe into normal mode via pin EN VEN = 5V EN tnorm 5 10.3 Time delay for mode change from normal V = 0V mode to sleep mode via EN pin EN EN tsleep 5 15 20 µs A 10.4 TXD dominant time out VTXD = 0V time TXD tdom 20 40 60 ms A 10.5 Time delay for mode change from silent V = 5V mode into normal mode EN via EN EN ts_n 5 15 40 µs A LIN D1 0.396 10.6 Duty cycle 1 THRec(max) = 0.744 VS THDom(max) = 0.581 VS VS = 7.0V to 18V tBit = 50µs D1 = tbus_rec(min)/(2 tBit) 100 *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 16 ATA6625 [DATASHEET] 9376A–AUTO–01/16 A 9. Electrical Characteristics (Continued) 5V < VS < 28V, –40°C < Tj < 150°C; unless otherwise specified all values refer to GND pins. No. Parameters Test Conditions Pin Symbol Duty cycle 2 THRec(min) = 0.422 VS THDom(min) = 0.284 VS VS = 7.6V to 18V tBit = 50µs D2 = tbus_rec(max)/(2 tBit) LIN D2 Duty cycle 3 THRec(max) = 0.778 VS THDom(max) = 0.616 VS VS = 7.0V to 18V tBit = 96µs D3 = tbus_rec(min)/(2 tBit) LIN D3 10.9 Duty cycle 4 THRec(min) = 0.389 VS THDom(min) = 0.251 VS VS = 7.6V to 18V tBit = 96µs D4 = tbus_rec(max)/(2 tBit) LIN D4 10.10 Slope time falling and rising edge at LIN VS = 7.0V to 18V LIN tSLOPE_fall tSLOPE_rise 10.7 10.8 11 Min. Typ. Max. Unit 0.581 A 0.417 A 0.590 3.5 Type* A 22.5 µs A 6 µs A +2 µs A Receiver Electrical AC Parameters of the LIN Physical Layer LIN Receiver, RXD Load Conditions: CRXD = 20pF 11.1 Propagation delay of receiver Figure 9-1 VS = 7.0V to 18V trx_pd = max(trx_pdr , trx_pdf) 11.2 Symmetry of receiver V = 7.0V to 18V propagation delay rising S trx_sym = trx_pdr – trx_pdf edge minus falling edge RXD trx_pd RXD trx_sym –2 *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter ATA6625 [DATASHEET] 9376A–AUTO–01/16 17 Figure 9-1. Definition of Bus Timing Characteristics tBit tBit tBit TXD (Input to transmitting node) tBus_dom(max) tBus_rec(min) Thresholds of receiving node1 THRec(max) VS (Transceiver supply of transmitting node) THDom(max) LIN Bus Signal Thresholds of receiving node2 THRec(min) THDom(min) tBus_dom(min) tBus_rec(max) RXD (Output of receiving node1) trx_pdf(1) trx_pdr(1) RXD (Output of receiving node2) trx_pdr(2) trx_pdf(2) Figure 9-2. Application Circuit VCC 1 ATA6625 VBAT VS Master node pull-up VCC Normal and Fail-safe Mode Receiver - RXD 5 + 100nF 22μF 1kΩ + 4 LIN-BUS RF filter LIN 220pF VCC Microcontroller Wake-up bus timer TXD EN 6 TXD Time-out timer Slew rate control 2 Control unit GND 3 Short circuit and overtemperature protection Sleep mode VCC switched off Normal/Silent/ Fail-safe Mode 5V 8 VCC 7 NRES 10kΩ Undervoltage reset 100nF GND 18 ATA6625 [DATASHEET] 9376A–AUTO–01/16 10μF 10. Ordering Information Extended Type Number Package ATA6625-GAQW 11. SO8 Remarks 5V LIN system basis chip, Pb-free, 4k, taped and reeled Package Information Figure 11-1. SO8 E1 L A b A2 A1 C D e 8 E 5 technical drawings according to DIN specifications Dimensions in mm 1 4 COMMON DIMENSIONS Pin 1 identity (Unit of Measure = mm) Symbol MIN NOM MAX A 1.5 1.65 1.8 A1 0.1 0.15 0.25 A2 1.4 1.47 1.55 D 4.8 4.9 5 E 5.8 6 6.2 E1 3.8 3.9 4 L 0.4 0.65 0.9 C 0.15 0.2 0.25 b 0.3 0.4 0.5 e NOTE 1.27 BSC 05/08/14 TITLE Package Drawing Contact: email@example.com Package: SO8 GPC DRAWING NO. REV. 6.543-5185.01-4 1 ATA6625 [DATASHEET] 9376A–AUTO–01/16 19 XXXXXX Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com © 2016 Atmel Corporation. / Rev.: 9376A–AUTO–01/16 Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®, and others are registered trademarks or trademarks of Atmel Corporation in U.S. and other countries. Other terms and product names may be trademarks of others. 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