ATA663232/ATA663255 - Complete

ATA663232/ATA663255
LIN SBC (1) including LIN Transceiver, Voltage Regulator
and Wake-input
DATASHEET
Features
● Supply voltage up to 40V
● Operating voltage VS = 5V to 28V
● Supply current
● Sleep mode: typically 9µA
● Silent mode: typically 47µA
● Very low current consumption at low supply voltages (2V < VS < 5.5V):
typically 130µA
● Linear low-drop voltage regulator, 85mA current capability:
● MLC (multi-layer ceramic) capacitor with 0 ESR
● Normal, fail-safe, and silent mode
● Atmel ATA663255: VCC = 5.0V ±2%
● Atmel ATA663232: VCC = 3.3V ±2%
● Sleep mode: VCC is switched off
● VCC undervoltage detection with internal reset (NRES_int)
● Voltage regulator is short-circuit and over-temperature protected
● LIN physical layer according to LIN 2.0, 2.1, 2.2, 2.2A and SAEJ2602-2
● Wake-up capability via LIN bus (100µs dominant) and WKin pin (100µs low level)
● Wake-up source recognition
● TXD time-out timer
● Bus pin is over-temperature and short-circuit protected versus GND and battery
● Advanced EMC and ESD performance
● Fulfills the OEM “Hardware Requirements for LIN in Automotive Applications
Rev.1.3”
● Interference and damage protection according to ISO7637
● Qualified according to AEC-Q100
● Package: DFN8 with wettable flanks (Moisture Sensitivity Level 1)
Note:
1. LIN SBC: LIN system basis chip.
9198C-AUTO-09/15
1.
Description
The Atmel ATA663232/55 system basis chip is a fully integrated LIN transceiver, designed according to the LIN specification
2.0, 2.1, 2.2, 2.2A and SAEJ2602-2, with a low-drop voltage regulator (3.3V/5V/85mA) and a high voltage wake-input. The
combination of voltage regulator and bus transceiver makes it possible to develop simple but powerful slave nodes in LIN
bus systems. Atmel ATA663232/55 is designed to handle the low-speed data communication in vehicles (for example, in
convenience electronics). Improved slope control at the LIN driver ensures secure data communication up to 20Kbaud. The
bus output is designed to withstand high voltage. Sleep mode and silent mode guarantee minimized current consumption
even in the case of a floating or a short-circuited LIN bus.
The voltage regulator is a fully integrated low-drop voltage regulator, with 5V/3.3V output voltage and 85mA current
capability. It is especially designed for the automotive environment. A key feature is that the current consumption is always
below 170µA (without load), even if the supply voltage is below the regulator’s nominal output voltage.
Figure 1-1. Block Diagram
Atmel ATA663232/55
VCC
-
1
VS
6
LIN
8
VCC
3
WKin
Normal and
Fail-safe
Mode
Receiver
RXD
7
+
RF-filter
VCC
Wake-up bus timer
TXD
4
EN
2
GND
5
TXD
Time-out
timer
Short-circuit and
overtemperature
protection
Slew rate control
Control
unit
Sleep
mode
VCC
switched
off
Normal/Silent/
Fail-safe Mode
3.3V/5V
Undervoltage Reset
VS
NRES_int
Wake-up
Timer
2
ATA663232/ATA663255 [DATASHEET]
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2.
Pin Configuration
Figure 2-1. Pinning DFN8
RXD
EN
WKin
TXD
Table 2-1.
ATA663232
ATA663255
VCC
VS
LIN
GND
DFN8
3x3
Pin Description
Pin
Symbol
1
RXD
Function
Receive data output
2
EN
3
WKin
High voltage input for local wake-up request. If not needed, connect directly to VS
4
TXD
Transmit data input
5
GND
Ground, heat slug
6
LIN
LIN bus line input/output
7
VS
Supply voltage
8
VCC
Backside
Enables normal mode if the input is high
Output voltage regulator 3.3V/5V/85mA
Heat slug, internally connected to the GND pin
ATA663232/ATA663255 [DATASHEET]
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3.
Pin Description
3.1
Supply Pin (VS)
LIN operating voltage is VS = 5V to 28V. Undervoltage detection is implemented to disable transmission if VS falls below typ.
4.5V, thereby avoiding false bus messages. After switching on VS, the IC starts in fail-safe mode and the voltage regulator is
switched on.
The supply current in sleep mode is typically 9µA and 47µA in silent mode.
3.2
Ground Pin (GND)
The IC does not affect the LIN bus in the event of GND disconnection. It is able to handle a ground shift of up to 11.5% of VS.
3.3
Voltage Regulator Output Pin (VCC)
The internal 3.3V/5V voltage regulator is capable of driving loads up to 85mA, supplying the microcontroller and other ICs on
the PCB and is protected against overload by means of current limitation and overtemperature shutdown. Furthermore, the
output voltage is monitored and causes an internal reset signal NRES_int, if it drops below a defined threshold
VVCC_th_uv_down.
3.4
Wake Input Pin (WKin)
The WKin pin is a high-voltage input used to wake up the device from sleep mode or silent mode. It is usually connected to
an external switch in the application to generate a local wake-up. A pull-up current source with typically 10µA is
implemented. The voltage threshold for a wake-up signal is typically 2V below the VS voltage. If a local wake up is not
needed in the application, the WKin pin can be connected directly to the VS pin.
3.5
Bus Pin (LIN)
A low-side driver with internal current limitation and thermal shutdown as well as an internal pull-up resistor according to LIN
specification 2.x is implemented. The voltage range is from –27V to +40V. This pin exhibits no reverse current from the LIN
bus to VS, even in the event of a GND shift or VBat disconnection. The LIN receiver thresholds comply with the LIN protocol
specification.
The fall time (from recessive to dominant) and the rise time (from dominant to recessive) are slope-controlled.
During a short circuit at LIN to VBat, the output limits the output current to IBUS_LIM. Due to the power dissipation, the chip
temperature exceeds TLINoff and the LIN output is switched off. The chip cools down and after a hysteresis of Thys, switches
the output on again. RXD stays on high because LIN is high. The VCC regulator works independently during LIN
overtemperature switch-off.
During a short circuit from LIN to GND the IC can be switched into sleep or silent mode and even in this case the current
consumption is lower than 100µA in sleep mode and lower than 120µA in silent mode. If the short-circuit disappears, the IC
starts with a remote wake-up.
The reverse current is < 2µA at pin LIN during loss of VBat. This is optimal behavior for bus systems where some slave nodes
are supplied from battery or ignition.
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ATA663232/ATA663255 [DATASHEET]
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3.6
Input/Output (TXD)
In normal mode the TXD pin is the microcontroller interface for controlling the state of the LIN output. TXD must be pulled to
ground in order to drive the LIN bus low. If TXD is high or unconnected (internal pull-up resistor), the LIN output transistor is
turned off and the bus is in the recessive state. If the TXD pin stays at GND level while switching into normal mode, it must
be pulled to high level longer than 10µs before the LIN driver can be activated. This feature prevents the bus line from being
accidentally driven to dominant state after normal mode has been activated (also in case of a short circuit at TXD to GND).
During fail-safe mode, this pin is used as output and signals the fail-safe source.
The TXD input has an internal pull-up resistor.
An internal timer prevents the bus line from being driven permanently in the dominant state. If TXD is forced to low longer
than tdom > 20ms, the LIN bus driver is switched to the recessive state. Nevertheless, when switching to sleep mode, the
actual level at the TXD pin is relevant.
To reactivate the LIN bus driver, switch TXD to high (> 10µs).
3.7
Output Pin (RXD)
In normal mode this pin reports the state of the LIN bus to the microcontroller. LIN high (recessive state) is indicated by a
high level at RXD; LIN low (dominant state) is indicated by a low level at RXD.
The output is a push-pull stage switching between VCC and GND. The AC characteristics are measured by an external load
capacitor of 20pF.
In silent mode the RXD output switches to high.
3.8
Enable Input Pin (EN)
The enable input pin controls the operating mode of the device. If EN is high, the circuit is in normal mode, with transmission
paths from TXD to LIN and from LIN to RXD both active. The VCC voltage regulator operates with 3.3V/5V/85mA output
capability.
If EN is switched to low while TXD is still high, the device is forced to silent mode. No data transmission is then possible, and
current consumption is reduced to IVSsilent typ. 47µA. The VCC regulator retains its full functionality.
If EN is switched to low while TXD is low, the device is forced to sleep mode. No data transmission is possible, and the
voltage regulator is switched off.
The EN pin provides a pull-down resistor to force the transceiver into recessive mode if EN is disconnected.
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4.
Functional Description
4.1
Physical Layer Compatibility
Because the LIN physical layer is independent of higher LIN layers (e.g., LIN protocol layer), all nodes with a LIN physical
layer according to revision 2.x can be mixed with LIN physical layer nodes based on earlier versions (i.e., LIN 1.0, LIN 1.1,
LIN 1.2, LIN 1.3) without any restrictions.
4.2
Operating Modes
Figure 4-1. Operating Modes
a: VS > VVS_th_U_F_up (2.4V)
b: VS < VVS_th_U_down (1.9V)
c: Bus wake-up event (LIN)
d: VCC < VCC_th_uv_down (2.2V/4.2V)
e: VS < VVS_th_N_F_down (3.9V)
f: VS > VVS_th_F_N_up (4.9V)
g: Local wake up (WKin)
Unpowered Mode
All circuitry OFF
a
b
c & f,
g&f
c & f,
g & f,
d
Fail-safe Mode
EN = 0
TXD = 0
&f
VCC: ON
VCC monitor active
Communication: OFF
Wake-up Signaling
Undervoltage Signaling
(1)
EN = 0
TXD = 1
&d&f
(1)
EN = 1
&f
d,
e
b
EN = 1
Sleep Mode
“Go to sleep”
command EN = 0
TXD = 0
Note:
1.
Table 4-1.
6
EN = 1
Normal Mode
&f
VCC: OFF
Communication: OFF
b
VCC: ON
VCC monitor active
Communication: ON
&f
EN = 0
“Go to silent”
command
TXD = 1
Silent Mode
VCC: ON
VCC monitor active
Communication: OFF
Condition f is valid for VS ramp up; at VS ramp down condition e is valid instead of f.
Operating Modes
Operating Mode
Transceiver
VCC
LIN
Fail-safe
OFF
3.3V/5V
Recessive
Signaling fail-safe sources (see
Table 4-2)
Normal
ON
3.3V/5V
TXD-dependent
Follows data transmission
Silent
OFF
3.3V/5V
Recessive
High
High
Sleep/Unpowered
OFF
0V
Recessive
Low
Low
ATA663232/ATA663255 [DATASHEET]
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TXD
RXD
4.2.1
Normal Mode
This is the normal transmitting and receiving mode of the LIN Interface, in accordance with LIN specification 2.x.
The VCC voltage regulator operates with 3.3V/5V output voltage, with a low tolerance of ±2% and a maximum output current
of 85mA. If an undervoltage condition occurs, the internal reset NRES_int switches to low and the IC changes its state to failsafe mode.
4.2.2
Silent Mode
A falling edge at EN while TXD is high switches the IC into silent mode. The TXD signal has to be logic high during the mode
select window. The transmission path is disabled in silent mode. The voltage regulator is active. The overall supply current
from VBat is a combination of the IVSsilent = 47µA plus the VCC regulator output current IVCC.
Figure 4-2. Switching to Silent Mode
Normal Mode
Silent Mode
EN
TXD
Mode select window
td = 3.2µs
NRES_int
VCC
Delay time silent mode
td_silent = maximum 20µs
LIN
LIN switches directly to recessive mode
In silent mode the internal slave termination between the LIN pin and VS pin is disabled to minimize the current consumption
in case the pin LIN is short-circuited to GND. Only a weak pull-up current (typically 10µA) between the LIN pin and VS pin is
present. Silent mode can be activated independently from the current level on pin LIN.
If an undervoltage condition occurs, the internal reset NRES_int switches to low and the Atmel® SBC changes its state to
fail-safe mode.
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4.2.3
Sleep Mode
A falling edge at EN while TXD is low switches the IC into sleep mode. The TXD signal has to be logic low during the mode
select window (Figure 4-5).
Figure 4-3. Switching to Sleep Mode
Sleep Mode
Normal Mode
EN
Mode select window
TXD
td = 3.2µs
NRES_int
VCC
Delay time sleep mode
td_sleep = maximum 20µs
LIN
LIN switches directly to recessive mode
In order to avoid any influence to the LIN pin when switching into sleep mode it is possible to switch the EN up to 3.2µs
earlier to low than the TXD. The easiest and best way to do this is by having two falling edges at TXD and EN at the same
time.
In sleep mode the transmission path is disabled. Supply current from VBat is typically IVSsleep = 9µA. The VCC regulator is
switched off, the internal reset NRES_int and pin RXD are low. The internal slave termination between the LIN pin and VS
pin is disabled to minimize the current consumption in case the LIN pin is short-circuited to GND. Only a weak pull-up current
(typically 10µA) between the LIN pin and the VS pin is present. The sleep mode can be activated independently from the
current level on the LIN pin. Voltage below the LIN pre-wake detection VLINL at the LIN pin activates the internal LIN receiver
and starts the wake-up detection timer.
If the TXD pin is short-circuited to GND, it is possible to switch to sleep mode via EN after t > tdom.
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ATA663232/ATA663255 [DATASHEET]
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4.2.4
Fail-Safe Mode
The device automatically switches to fail-safe mode at system power-up. The voltage regulator is switched on. The internal
reset NRES_int remains low for tres = 4ms and LIN communication is switched off. The IC stays in this mode until EN is
switched to high. The IC then changes to normal mode. A low level at the internal reset NRES_int switches the IC into
fail-safe mode directly. During fail-safe mode the TXD pin is an output and, together with the RXD output pin, signals the failsafe source.
If the device enters fail-safe mode coming from the normal mode (EN=1) due to an VS undervoltage condition
(VS < VVS_th_N_F_down), it is possible to switch into sleep or silent mode by a falling edge at the EN input. With this feature the
current consumption can be further reduced.
A wake-up event switches the IC to fail-safe mode.
A wake-up event from either silent or sleep mode is signalled to the microcontroller using the RXD pin and the TXD pin. A VS
undervoltage condition is also signalled at these two pins. The coding is shown in the table below.
Table 4-2.
Signaling in Fail-safe Mode
Fail-Safe Sources
TXD
RXD
LIN wake-up (LIN pin)
Low
Low
Local wake-up (WKin pin)
Low
High
VSth (battery) undervoltage detection (VS < 3.9V)
High
Low
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4.3
Wake-up Scenarios from Silent Mode or Sleep Mode
4.3.1
Remote Wake-up via LIN Bus
4.3.1.1 Remote Wake-up from Silent Mode
A remote wake-up from silent mode is only possible if TXD is high. A voltage less than the LIN pre-wake detection VLINL at
the LIN pin activates the internal LIN receiver and starts the wake-up detection timer. A falling edge at the LIN pin followed
by a dominant bus level maintained for a certain period of time (> tbus) and the following rising edge at pin LIN (see
Figure 4-4) result in a remote wake-up request. The device switches from silent mode to fail-safe mode, the VCC voltage
regulator remains activated and the internal LIN slave termination resistor is switched on. The remote wake-up request is
indicated by a low level at the RXD pin and TXD pin (strong pull-down at TXD). EN high can be used to switch directly to
normal mode.
Figure 4-4. LIN Wake-up from Silent Mode
Bus wake-up filtering time
tbus
Fail-safe Mode
Normal Mode
LIN bus
RXD
High
TXD
High
VCC
Low
Low (strong pull-down)
Silent mode 3.3V/5V
Fail-safe mode 3.3V/5V
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Normal mode
EN High
EN
NRES_int
High
Undervoltage detection active
4.3.1.2 Remote Wake-up from Sleep Mode
A falling edge at the LIN pin followed by a dominant bus level maintained for a certain period of time (> tbus) and a following
rising edge at the LIN pin result in a remote wake-up request, causing the device to switch from sleep mode to fail-safe
mode.
The VCC regulator is activated, and the internal LIN slave termination resistor is switched on. The remote wake-up request is
indicated by a low level at RXD and TXD (strong pull-down at TXD) (see Figure 4-5).
EN high can be used to switch directly from sleep/silent mode to fail-safe mode. If EN is still high after VCC ramp-up and
undervoltage reset time, the IC switches to normal mode.
Figure 4-5. LIN Wake-up from Sleep Mode
Bus wake-up filtering time
tbus
Fail-safe Mode
LIN bus
RXD
High
Low
High
Low (strong pull-down)
High
Low
TXD
VCC
Normal Mode
On state
Off state
tVCC
EN High
EN
Reset
time
NRES_int
Low
Microcontroller
start-up time delay
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4.3.2
Local Wake-up via WKin Pin
A falling edge at the WKin pin followed by a low level maintained for a given time period (> tWKin) results in a local wake-up
request. The device switches to fail-safe mode. The internal slave termination resistor is switched on. The local wake-up
request is indicated by a low level at the TXD pin to generate an interrupt for the microcontroller. When the WKin pin is low,
it is possible to switch to silent mode or sleep mode via the EN pin. In this case, the wake-up signal has to be switched to
high > 10µs before the negative edge at WKin starts a new local wake-up request.
Figure 4-6. Local Wake-up via WKin pin from Sleep Mode
Fail-safe Mode
Normal Mode
State change
WKin
RXD
High
TXD
Low (strong pull-down)
Wake filtering time
tWKin
VCC
On state
Off state
tVCC
EN High
EN
Reset
time
NRES_int
Low
Microcontroller
start-up time delay
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ATA663232/ATA663255 [DATASHEET]
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Figure 4-7. Local Wake-up via WKin pin from Silent Mode
Fail-safe Mode
WKin
Normal Mode
State change
High
RXD
TXD
Low (strong pull-down)
Wake filtering time
tWKin
VCC
EN High
EN
NRES_int
4.3.3
Wake-up Source Recognition
The device can distinguish between different wake-up sources. The wake-up source can be read on the TXD and RXD pin in
fail-safe mode. These flags are immediately reset if the microcontroller sets the EN pin to high and the IC is in normal mode.
Table 4-3.
Signaling in Fail-safe Mode
Fail-Safe Sources
TXD
RXD
LIN wake-up (LIN pin)
Low
Low
Local wake-up (WKin pin)
Low
High
VSth (battery) undervoltage detection (VS < 3.9V)
High
Low
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4.4
Behavior under Low Supply Voltage Condition
After the battery voltage has been connected to the application circuit, the voltage at the VS pin increases according to the
block capacitor used in the application (see Figure 8-1 on page 25). If VVS is higher than the minimum VS operation
threshold VVS_th_U_F_up, the IC mode changes from unpowered mode to fail-safe mode. As soon as VVS exceeds the
undervoltage threshold VVS_th_F_N_up, the LIN transceiver can be activated.
The VCC output voltage reaches its nominal value after tVCC. This parameter depends on the externally applied VCC
capacitor and the load. The internal reset NRES_int output is low for the reset time delay treset. No mode change is possible
during this time treset.
The behaviour of VCC, the internal reset NRES_int and VS is shown in the following diagrams (ramp-up and ramp-down):
V (V)
Figure 4-8. VCC and the Internal Reset NRES_int versus VS (Ramp-up) for 3.3V
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VS
NRES_int
VCC
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
VS (V)
V (V)
Figure 4-9. VCC and the Internal Reset NRES_int versus VS (Ramp-down) for 3.3V
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VS
NRES_int
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
VS (V)
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ATA663232/ATA663255 [DATASHEET]
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3.0
VCC
2.5
2.0
1.5
1.0
0.5
0.0
V (V)
Figure 4-10. VCC and the Internal Reset NRES_int versus VS (Ramp-up) for 5V
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VS
NRES_int
VCC
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
VS (V)
V (V)
Figure 4-11. VCC and the Internal Reset NRES_int versus VS (Ramp-down) for 5V
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VS
NRES_int
VCC
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VS (V)
Please note that the upper graphs are only valid if the VS ramp-up and ramp-down times are much slower than the VCC
ramp-up time tVcc and the internal reset NRES_int delay time treset.
If during sleep mode the voltage level of VVS drops below the undervoltage detection threshold VVS_th_N_F_down (typ. 4.3V),
the operation mode is not changed and no wake-up is possible. Only if the supply voltage on pin VS drops below the VS
operation threshold VVS_th_U_down (typ. 2.05V), does the IC switch to unpowered mode.
If during silent mode the VCC voltage drops below the VCC undervoltage threshold VVCC_th_uv_down the IC switches into failsafe mode. If the supply voltage on pin VS drops below the VS operation threshold VVS_th_U_down (typ. 2.05V), does the IC
switch to unpowered mode.
If during normal mode the voltage level on the VS pin drops below the VS undervoltage detection threshold VVS_th_N_F_down
(typ. 4.3V), the IC switches to fail-safe mode. This means the LIN transceiver is disabled in order to avoid malfunctions or
false bus messages. The voltage regulator remains active.
For 3.3V SBC: In this undervoltage situation it is possible to switch the device into sleep mode or silent mode by a
falling edge at the EN input. For this feature, switching into these two current saving modes is always guaranteed,
allowing current consumption to be reduced even further.
When the VCC voltage drops below the VCC undervoltage threshold VVCC_th_uv_down (typ. 2.6V) the IC switches into
fail-safe mode.
For 5V SBC: Because of the VCC undervoltage condition in this situation, the IC is in fail-safe mode and can be
switched into sleep mode only.
Only when the supply voltage VVS drops below the operation threshold VVS_th_U_down (typ. 2.05V) does the IC switch
into unpowered mode.
The current consumption of the SBC in silent mode or in fail-safe mode is always below 170µA, even when the supply
voltage VS is lower than the regulator’s nominal output voltage VCC.
ATA663232/ATA663255 [DATASHEET]
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4.5
Voltage Regulator
Figure 4-12. Voltage Regulator: Supply Voltage Ramp-up and Ramp-down
V
VS
12V
VCC
3.3V/5.0V
VVCC_th_uv_up
VVCC_th_uv_down
2.4V
t
tVCC
tReset
tres_f
NRES_int
3.3V/5.0V
t
The voltage regulator needs an external capacitor for compensation and to smooth the disturbances from the
microcontroller. It is recommended to use a MLC capacitor with a minimum capacitance of 3.5µF together with a 100nF
ceramic capacitor. Depending on the application, the values of these capacitors can be modified by the customer.
During a short circuit at VCC, the output limits the output current to IVCClim. Because of undervoltage, the internal reset
NRES_int switches to low. If the chip temperature exceeds the value TVCCoff, the VCC output switches off. The chip cools
down and, after a hysteresis of Thys, switches the output on again.
When the Atmel ATA663232/55 is being soldered onto the PCB it is mandatory to connect the heat slug with a wide GND
plate on the printed board to get a good heat sink.
The main power dissipation of the IC is created from the VCC output current IVCC, which is needed for the application.
“Power Dissipation: Safe Operating Area: Regulator’s Output Current IVcc versus Supply Voltage VS” is shown in Figure 413.
Figure 4-13. Power Dissipation: Safe Operating Area: Regulator’s Output Current IVcc versus Supply Voltage VS at
Different Ambient Temperatures (Rthja = 50K/W assumed)
I_Vcc [mA]
90
80
Tamb = 85°C
70
Tamb = 95°C
60
Tamb = 105°C
50
Tamb = 115°C
40
30
Tamb = 125°C
20
10
0
5
6
7
8
9
10
11
12
VS [V]
16
ATA663232/ATA663255 [DATASHEET]
9198C–AUTO–09/15
13
14
15
16
17
18
5.
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
Min.
Supply voltage VS
VS
–0.3
Pulse time ≤ 500ms
Ta = 25°C
Output current IVCC ≤ 85mA
Pulse time ≤ 2min
Ta = 25°C
Output current IVCC ≤ 85mA
Typ.
Max.
Unit
+40
V
VS
+43.5
V
VS
28
V
Logic pins voltage levels (RxD, TxD, EN)
VLogic
–0.3
+5.5
V
Logic pins output DC currents
ILogic
–5
+5
mA
LIN
- DC voltage
- Pulse time < 500ms
VLIN
–27
+40
+43.5
V
V
WKin voltage levels
- DC voltage
-Transient voltage according to ISO7637
(coupling 1nF), (with 2.7K serial resistor)
VWKin
–0.3
+40
–150
+100
–0.3
+5.5
+200
VCC
- DC voltage
- DC input current
VVCC
IVCC
ESD according to IBEE LIN EMC
Test specification 1.0 following IEC 61000-4-2
- Pin VS, LIN, WKin to GND (with external
circuitry acc. to applications diagram)
V
V
mA
±6
kV
±6
±5
kV
kV
±3
kV
CDM ESD STM 5.3.1
±750
V
Machine Model ESD
AEC-Q100-RevF(003)
±200
V
ESD HBM following STM5.1
with 1.5k/100pF
- Pin VS, LIN to GND
- Pin WKin to GND
HBM ESD
ANSI/ESD-STM5.1
JESD22-A114
AEC-Q100 (002)
Junction temperature
Tj
–40
+150
°C
Storage temperature
Ts
–55
+150
°C
ATA663232/ATA663255 [DATASHEET]
9198C–AUTO–09/15
17
6.
Thermal Characteristics
Parameters
Symbol
Min.
Typ.
Max.
Unit
Thermal resistance junction to heat slug
RthjC
10
K/W
Thermal resistance junction to ambient, where
heat slug is soldered to PCB according to
JEDEC
Rthja
50
K/W
Thermal shutdown of VCC regulator
TVCCoff
150
165
180
°C
Thermal shutdown of LIN output
TLINoff
150
165
180
°C
Thermal shutdown hysteresis
7.
Thys
10
°C
Electrical Characteristics
5V < VS < 28V, –40°C < Tj < 150°C; unless otherwise specified all values refer to GND pins.
No. Parameters
1
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
VS
VS
5
13.5
28
V
A
Sleep mode
VLIN > VS – 0.5V
VS < 14V, T = 27°C
VS
IVSsleep
6
9
15
µA
B
Sleep mode
VLIN > VS – 0.5V
VS < 14V
VS
IVSsleep
3
11
18
µA
A
Sleep mode, VLIN = 0V
bus shorted to GND
VS < 14V
VS
IVSsleep_short
20
50
100
µA
A
Bus recessive
5.5V< VS < 14V
without load at VCC
T = 27°C
VS
IVSsilent
30
47
58
µA
B
Bus recessive
5.5V< VS < 14V
without load at VCC
VS
IVSsilent
30
50
64
µA
A
Bus recessive
2.0V< VS < 5,5V
without load at VCC
VS
IVSsilent
50
130
170
µA
A
Silent mode
5.5V< VS < 14V
bus shorted to GND
without load at VCC
VS
IVSsilent_short
50
80
120
µA
A
Bus recessive
VS < 14V
without load at VCC
VS
IVSrec
150
230
290
µA
A
Bus dominant (internal
LIN pull-up resistor active)
VS < 14V
without load at VCC
VS
IVSdom
200
700
950
µA
A
VS Pin
1.1 Nominal DC voltage range
1.2
Supply current in sleep
mode
Supply current in silent
1.3
mode
1.4
Supply current in normal
mode
Supply current in normal
1.5
mode
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
18
ATA663232/ATA663255 [DATASHEET]
9198C–AUTO–09/15
7.
Electrical Characteristics (Continued)
5V < VS < 28V, –40°C < Tj < 150°C; unless otherwise specified all values refer to GND pins.
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
VS
IVSfail
40
55
80
µA
A
VS
IVSfail
50
130
170
µA
A
VS
VVS_th_N_F_down
3.9
4.3
4.7
V
A
VS
VVS_th_F_N_up
4.1
4.6
4.9
V
A
VS
VVS_hys_F_N
0.1
0.25
0.4
V
A
Switch to unpowered mode
VS
VVS_th_U_down
1.9
2.05
2.3
V
A
Switch from unpowered to
fail-safe mode
VS
VVS_th_U_F_up
2.0
2.25
2.4
V
A
VS
VVS_hys_U
0.1
0.2
0.3
V
A
0.2
0.4
V
A
V
A
Bus recessive
5.5V < VS < 14V
Supply current in fail-safe without load at VCC
1.6
mode
Bus recessive
2.0V < VS < 5.5V
without load at VCC
VS undervoltage threshold Decreasing supply voltage
1.7 (switching from normal to
Increasing supply voltage
fail-safe mode)
1.8
VS undervoltage
hysteresis
VS operation threshold
1.9 (switching to unpowered
mode)
1.10
VS undervoltage
hysteresis
2
RXD Output Pin
2.1
Low-level output sink
capability
Normal mode,
VLIN = 0V, IRXD = 2mA
RXD
VRXDL
2.2
High-level output source
capability
Normal mode
VLIN = VS, IRXD = –2mA
RXD
VRXDH
VCC –
0.4V
3.1 Low-level voltage input
TXD
VTXDL
–0.3
+0.8
V
A
3.2 High-level voltage input
TXD
VTXDH
2
VCC +
0.3V
V
A
100
k
A
+3
µA
A
8
mA
A
3
VCC –
0.2V
TXD Input/Output Pin
3.3 Pull-up resistor
TXD
RTXD
40
3.4 High-level leakage current VTXD = VCC
TXD
ITXD
–3
Low-level output sink
3.7 current at LIN wake-up
request
TXD
ITXD
2
4.1 Low-level voltage input
EN
VENL
–0.3
+0.8
V
A
4.2 High-level voltage input
EN
VENH
2
VCC +
0.3V
V
A
200
k
A
+3
µA
A
6
ms
B
10
µs
D
4
VTXD = 0V
Fail-safe Mode
VLIN = VS
VTXD = 0.4V
2.5
EN Input Pin
4.3 Pull-down resistor
VEN = VCC
EN
REN
50
4.4 Low-level input current
VEN = 0V
EN
IEN
–3
5
70
125
Internal Reset NRES_int
5.1 Undervoltage reset time
VVS ≥ 5.5V
-
tReset
2
Reset debounce time for
5.2
falling edge
VVS ≥ 5.5V
-
tres_f
0.5
4
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
ATA663232/ATA663255 [DATASHEET]
9198C–AUTO–09/15
19
7.
Electrical Characteristics (Continued)
5V < VS < 28V, –40°C < Tj < 150°C; unless otherwise specified all values refer to GND pins.
No. Parameters
6
Test Conditions
Pin
Symbol
Min.
WKin
VWKinH
Max.
Unit
Type*
VS – 1V
VS
+0.3V
V
A
VWKinL
–1
VS 3.3V
V
A
WKin Pin
6.1 High-level input voltage
6.2 Low-level input voltage
Initializes a wake-up signal
WKin
6.3 WKin pull-up current
VS < 28V, VWKin = 0V
WKin
IWKin
–30
6.4 High-level leakage current VS = 28V, VWKin = 28V
WKin
IWKinL
–5
Debounce time of low
6.5 pulse for wake-up via
WKin pin
WKin
tWKL
50
4V < VS < 18V
(0mA to 50mA)
VCC
VCCnor
4.5V < VS < 18V
(0mA to 85mA)
VCC
8
VWKin = 0V
–10
µA
A
+5
µA
A
150
µs
A
3.234
3.366
V
A
VCCnor
3.234
3.366
V
C
VCC
VCClow
VVS – VD
3.366
V
A
100
VCC Voltage Regulator (3.3V)
8.1 Output voltage VCC
8.2
Typ.
Output voltage VCC at low
3V < VS < 4V
VS
8.3 Regulator drop voltage
VS > 3V, IVCC = –15mA
VCC
VD1
100
150
mV
A
8.4 Regulator drop voltage
VS > 3V, IVCC = –50mA
VCC
VD2
300
500
mV
A
8.5 Line regulation maximum 4V < VS < 18V
VCC
VCCline
0.1
0.2
%
A
8.6 Load regulation maximum 5mA < IVCC < 50mA
VCC
VCCload
0.1
0.5
%
A
8.7 Output current limitation
VS > 4V
VCC
IVCClim
–180
–120
mA
A
8.8 Load capacity
MLC capacitor
VCC
Cload
µF
D
3.5
4.7
VCC undervoltage
Referred to VCC
threshold (NRES_int low) VS > 4V
VCC VVCC_th_uv_down
2.2
2.5
2.8
V
A
VCC undervoltage
Referred to VCC
threshold (NRES_int high) VS > 4V
VCC
VVCC_th_uv_up
2.4
2.6
2.9
V
A
8.10
Hysteresis of VCC
undervoltage threshold
VCC
VVCC_hys_uv
100
200
300
mV
A
8.11
Ramp-up time VS > 4V to CVCC = 4.7µF
VCC = 3.3V
Iload = –5mA at VCC
VCC
tVCC
1
1.5
ms
A
5.5V < VS < 18V
(0mA to 50mA)
VCC
VCCnor
4.9
5.1
V
A
6V < VS < 18V
(0mA to 85mA)
VCC
VCCnor
4.9
5.1
V
C
Output voltage VCC at low
4V < VS < 5.5V
VS
VCC
VCClow
VVS – VD
5.1
V
A
8.9
9
VCC Voltage Regulator (5V)
9.1 Output voltage VCC
9.2
Referred to VCC
VS > 4V
9.3 Regulator drop voltage
VS > 4V, IVCC = –20mA
VCC
VD1
100
200
mV
A
9.4 Regulator drop voltage
VS > 4V, IVCC = –50mA
VCC
VD2
300
500
mV
A
9.5 Regulator drop voltage
VS > 3.3V, IVCC = –15mA
VCC
VD3
150
mV
A
9.6 Line regulation maximum 5.5V < VS < 18V
VCC
VCCline
0.1
0.2
%
A
9.7 Load regulation maximum 5mA < IVCC < 50mA
VCC
VCCload
0.1
0.5
%
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
20
ATA663232/ATA663255 [DATASHEET]
9198C–AUTO–09/15
7.
Electrical Characteristics (Continued)
5V < VS < 28V, –40°C < Tj < 150°C; unless otherwise specified all values refer to GND pins.
No. Parameters
Test Conditions
Pin
Symbol
9.8 Output current limitation
VS > 5.5V
VCC
IVCClim
9.9 Load capacity
MLC capacitor
VCC
Cload
Min.
Typ.
Max.
Unit
Type*
–180
–120
mA
A
µF
D
3.5
4.7
VCC VVCC_th_uv_down
4.2
4.4
4.6
V
A
VCC undervoltage
Referred to VCC
threshold (NRES_int high) VS > 4V
VCC
VVCC_th_uv_up
4.3
4.6
4.8
V
A
9.11
Hysteresis of undervoltage Referred to VCC
threshold
VS > 5.5V
VCC
VVCC_hys_uv
100
200
300
mV
A
9.12
Ramp-up time VS > 5.5V CVCC = 4.7µF
to VCC = 5V
Iload = –5mA at VCC
VCC
tVCC
1
1.5
ms
A
9.10
10
10.1
VCC undervoltage
Referred to VCC
threshold (NRES_int low) VS > 4V
LIN Bus Driver: Bus Load Conditions:
Load 1 (small): 1nF, 1k; Load 2 (large): 10nF, 500; CRXD = 20pF, Load 3 (medium): 6.8nF, 660 characterized on samples
12.7 and 12.8 specifies the timing parameters for proper operation at 20kb/s and 12.9 and 12.10 at 10.4kb/s
Driver recessive output
voltage
Load1/Load2
LIN
VBUSrec
10.2 Driver dominant voltage
VVS = 7V
Rload = 500
LIN
10.3 Driver dominant voltage
VVS = 18V
Rload = 500
10.4 Driver dominant voltage
0.9  VS
VS
V
A
V_LoSUP
1.2
V
A
LIN
V_HiSUP
2
V
A
VVS = 7V
Rload = 1000
LIN
V_LoSUP_1k
0.6
V
A
10.5 Driver dominant voltage
VVS = 18V
Rload = 1000
LIN
V_HiSUP_1k
0.8
V
A
10.6 Pull-up resistor to VS
The serial diode is
mandatory
LIN
RLIN
20
47
k
A
1.0
V
D
200
mA
A
mA
A
30
10.7
Voltage drop at the serial In pull-up path with Rslave
ISerDiode = 10mA
diodes
LIN
VSerDiode
0.4
10.8
LIN current limitation
VBUS = VBat_max
LIN
IBUS_LIM
40
120
LIN
IBUS_PAS_dom
–1
–0.35
Driver off
8V < VBat < 18V
8V < VBUS < 18V
VBUS ≥ VBat
LIN
IBUS_PAS_rec
Leakage current when
control unit disconnected
GNDDevice = VS
from ground.
10.11
V = 12V
Loss of local ground must Bat
0V < VBUS < 18V
not affect communication
in the residual network
LIN
IBUS_NO_gnd
Input leakage current
Input leakage current at
driver off
10.9 the receiver including pullVBUS = 0V
up resistor as specified
VBat = 12V
Leakage current LIN
10.10
recessive
–10
10
20
µA
A
+0.5
+10
µA
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
ATA663232/ATA663255 [DATASHEET]
9198C–AUTO–09/15
21
7.
Electrical Characteristics (Continued)
5V < VS < 28V, –40°C < Tj < 150°C; unless otherwise specified all values refer to GND pins.
No. Parameters
Test Conditions
Pin
Symbol
Typ.
Max.
Unit
Type*
LIN
IBUS_NO_bat
0.1
2
µA
A
LIN
CLIN
20
pF
D
VBUS_CNT =
(Vth_dom + Vth_rec)/2
LIN
VBUS_CNT
0.475 
VS
0.525 
VS
V
A
11.2 Receiver dominant state
VEN = 5V/3.3V
LIN
VBUSdom
–27
0.4  VS
V
A
11.3 Receiver recessive state
VEN = 5V/3.3V
LIN
VBUSrec
0.6  VS
40
V
A
LIN
VBUShys
0.028 
0.175 
0.1 x VS
VS
VS
V
A
LIN
VLINH
VS – 2V
VS +
0.3V
V
A
Activates the LIN receiver
LIN
VLINL
–27
VS –
3.3V
V
A
VLIN = 0V
LIN
tbus
50
100
150
µs
A
Time delay for mode
12.2 change from fail-safe into VEN = 5V/3.3V
normal mode via EN pin
EN
tnorm
5
15
20
µs
A
Time delay for mode
12.3 change from normal mode VEN = 0V
to sleep mode via EN pin
EN
tsleep
5
15
20
µs
A
VTXD = 0V
TXD
tdom
20
40
60
ms
A
Time delay for mode
change from silent mode
12.6
into normal mode via EN
pin
VEN = 5V/3.3V
EN
ts_n
5
15
40
µs
A
12.7 Duty cycle 1
THRec(max) = 0.744  VS
THDom(max) = 0.581  VS
VS = 7.0V to 18V
tBit = 50µs
D1 = tbus_rec(min)/(2  tBit)
LIN
D1
0.396
12.8 Duty cycle 2
THRec(min) = 0.422  VS
THDom(min) = 0.284  VS
VS = 7.6V to 18V
tBit = 50µs
D2 = tbus_rec(max)/(2  tBit)
LIN
D2
Leakage current at
disconnected battery.
Node has to sustain the
VBat disconnected
10.12 current that can flow under VSUP_Device = GND
this condition. Bus must 0V < VBUS < 18V
remain operational under
this condition.
10.13
Capacitance on pin LIN to
GND
11
LIN Bus Receiver
11.1
Center of receiver
threshold
11.4 Receiver input hysteresis Vhys = Vth_rec – Vth_dom
11.5
Pre-wake detection LIN
high-level input voltage
11.6
Pre-wake detection LIN
low-level input voltage
12
12.1
12.5
Min.
0.5 
VS
Internal Timers
Dominant time for
wake-up via LIN bus
TXD dominant time-out
time
A
0.581
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
22
ATA663232/ATA663255 [DATASHEET]
9198C–AUTO–09/15
A
7.
Electrical Characteristics (Continued)
5V < VS < 28V, –40°C < Tj < 150°C; unless otherwise specified all values refer to GND pins.
No. Parameters
Test Conditions
Pin
Symbol
Min.
12.9 Duty cycle 3
THRec(max) = 0.778  VS
THDom(max) = 0.616  VS
VS = 7.0V to 18V
tBit = 96µs
D3 = tbus_rec(min)/(2  tBit)
LIN
D3
0.417
12.10 Duty cycle 4
THRec(min) = 0.389  VS
THDom(min) = 0.251  VS
VS = 7.6V to 18V
tBit = 96µs
D4 = tbus_rec(max)/(2  tBit)
LIN
D4
VS = 7.0V to 18V
LIN
tSLOPE_fall
tSLOPE_rise
12.11
13
13.1
Slope time falling and
rising edge at LIN
Typ.
Max.
Unit
A
0.590
3.5
Type*
A
22.5
µs
A
6
µs
A
+2
µs
A
Receiver Electrical AC Parameters of the LIN Physical Layer
LIN Receiver, RXD Load Conditions: CRXD = 20pF
Propagation delay of
receiver
Symmetry of receiver
13.2 propagation delay rising
edge minus falling edge
VS = 7.0V to 18V
trx_pd = max(trx_pdr , trx_pdf)
RXD
trx_pd
VS = 7.0V to 18V
trx_sym = trx_pdr – trx_pdf
RXD
trx_sym
–2
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
ATA663232/ATA663255 [DATASHEET]
9198C–AUTO–09/15
23
Figure 7-1. Definition of Bus Timing Characteristics
tBit
tBit
tBit
TXD
(Input to transmitting node)
tBus_dom(max)
tBus_rec(min)
Thresholds of
receiving node1
THRec(max)
VS
(Transceiver supply
of transmitting node)
THDom(max)
LIN Bus Signal
Thresholds of
receiving node2
THRec(min)
THDom(min)
tBus_dom(min)
tBus_rec(max)
RXD
(Output of receiving node1)
trx_pdf(1)
trx_pdr(1)
RXD
(Output of receiving node2)
trx_pdr(2)
24
ATA663232/ATA663255 [DATASHEET]
9198C–AUTO–09/15
trx_pdf(2)
8.
Application Circuits
Figure 8-1. Typical Application Circuit
D1
VCC
C5
R4
10kΩ
100nF
VCC
RXD
Atmel
ATA663232
ATA663255
R3
WKin
10µF/50V
C4
4.7µF
DFN8
3x3
C2
Note:
LIN
C3
TXD
S1
100nF
LIN
2.7kΩ
GND
Master node
pull up
VCC
VS
EN
Microcontroller
VBAT
C1
220pF
GND
GND
External
Wakeswitch
Heat slug must always be connected to GND.
ATA663232/ATA663255 [DATASHEET]
9198C–AUTO–09/15
25
9.
10.
Ordering Information
Extended Type Number
Package
Remarks
ATA663232-GBQW
DFN8
3.3V LIN system basis chip, Pb-free, 6k, taped and reeled
ATA663255-GBQW
DFN8
5V LIN system basis chip, Pb-free, 6k, taped and reeled
Package Information
Top View
D
8
E
PIN 1 ID
technical drawings
according to DIN
specifications
1
A
A3
A1
Dimensions in mm
Side View
Partially Plated Surface
Bottom View
4
COMMON DIMENSIONS
E2
1
Z
8
(Unit of Measure = mm)
5
e
D2
L
Z 10:1
Symbol
MIN
NOM
MAX
A
0.8
0.85
0.9
A1
A3
0
0.16
0.035
0.21
0.05
0.26
D
2.9
3
3.1
D2
2.3
2.4
2.5
E
2.9
3
3.1
E2
1.5
1.6
1.7
L
0.35
0.4
0.45
b
e
0.25
0.3
0.65
0.35
NOTE
b
10/11/13
TITLE
Package Drawing Contact:
[email protected]
26
Package: VDFN_3x3_8L
Exposed pad 2.4x1.6
ATA663232/ATA663255 [DATASHEET]
9198C–AUTO–09/15
GPC
DRAWING NO.
REV.
6.543-5165.03-4
1
XXXXXX
Atmel Corporation
1600 Technology Drive, San Jose, CA 95110 USA
T: (+1)(408) 441.0311
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