PRELIMINARY W48C111-16 Frequency Generator for Integrated Core Logic Features CPU0:1 Skew: ............................................................ 175 ps • Maximized EMI suppression using Cypress’s Spread Spectrum technology • Power-on default to spread mode • Two copies of CPU output • Six copies of PCI output (synchronous w/CPU outputs) • One copy of 48-MHz USB output • One Buffered copy of 14.318-MHz input reference signal • Supports 100-MHz or 66-MHz CPU operation • Power management control input pins • Low Frequency Test Mode • Available in 28-pin SSOP (209 mil) CPU0:1 Cycle to Cycle Jitter: ..................................... 200 ps PCI_F, PCI1:5 Skew: ...................................................500 ps PCI_F, PCI1:5 Cycle to Cycle Jitter: ............................ 250 ps CPU to PCI Skew: ........................ 1.5 to 4.0 ns (CPU Leads) Output Duty Cycle: .................................................... 45/55% PCI_F, PCI Edge Rate: .............................................. >1 V/ns CPU_STOP#, PWR_DWN#, PCI_STOP#: 250-kΩ pull-up resistor Table 1. Pin Selectable Frequency SEL100/66# CPU(0:1) PCI Spread% Key Specifications 0 66.6 MHz 33.3 ±0.5% Supply Voltages: ....................................... VDDQ3 = 3.3V±5% VDDQ2 = 2.5V±5% 1 100 MHz 33.3 ±0.5% Block Diagram Pin Configuration VDDQ3 REF X1 X2 XTAL OSC PLL Ref Freq CPU_STOP# Stop Clock Control SEL100/66# X1 1 28 GND X2 2 27 VDDQ3 GND 3 26 REF PCI_F 4 25 VDDQ2 PCI1 5 24 CPU0 VDDQ3 6 23 CPU1 VDDQ2 PCI2 7 22 GND CPU0 PCI3 8 21 VDDQ3 CPU1 VDDQ3 9 20 GND PCI4 10 19 PCI_STOP# PCI5 11 18 CPU_STOP# GND 12 17 PWR_DWN# VDDQ3 13 16 48MHz GND 14 15 SEL100/66# PLL 1 ÷2/÷3 VDDQ3 PCI_F PCI1 Stop Clock Control PCI2 PCI3 PCI_STOP# VDDQ3 PCI4 PCI5 Power Down Control PWR_DWN# VDDQ3 PLL 2 Cypress Semiconductor Corporation 48MHz • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 November 2, 1999, rev. ** PRELIMINARY W48C111-16 Pin Definitions Pin No. Pin Type CPU0:1 24, 23 O CPU Clock Outputs 0 and 1: These two CPU clock outputs are controlled by the CPU_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ2. PCI1:5 5, 7, 8, 10, 11 O PCI Bus Clock Outputs 1 through 5: These five PCI clock outputs are controlled by the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ3. PCI_F 4 O Fixed PCI Clock Output: Unlike PCI1:5 outputs, this output is not controlled by the PCI_STOP# control pin; it cannot be forced LOW by PCI_STOP#. Output voltage swing is controlled by voltage applied to VDDQ3. 48MHz 16 O 48-MHz Output: Fixed clock output at 48 MHz. Output voltage swing is controlled by voltage applied to VDDQ3. This output does not have the SS feature CPU_STOP# 18 I CPU_STOP# input: When brought LOW, clock outputs CPU0:1 are stopped LOW after completing a full clock cycle (2–3 CPU clock latency). When brought HIGH, clock outputs CPU0:1 start with a full clock cycle (2–3 CPU clock latency). PCI_STOP# 19 I PCI_STOP# input: The PCI_STOP# input enables the PCI1:5 outputs when HIGH and causes them to remain at logic 0 when LOW. The PCI_STOP signal is latched on the rising edge of PCI_F. Its effect takes place on the next PCI_F clock cycle. REF 26 O Fixed 14.318-MHz Output: Used for various system applications. Output voltage swing is controlled by voltage applied to VDDQ3. SEL100/66# 15 I Frequency Selection Inputs: Select power-up default CPU clock frequency as shown in Table 1 on page 1. X1 1 I Crystal Connection or External Reference Frequency Input: This pin can either be used as a connection to a crystal or to a reference signal. X2 2 I Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. PWR_DWN# 17 I Power-Down Control: When this input is LOW, device goes into a low-power standby condition. All outputs are held LOW. CPU and PCI clock outputs are stopped LOW after completing a full clock cycle (2–3 CPU clock cycle latency). When brought HIGH, CPU and PCI outputs start with a full clock cycle at full operating frequency (3 ms maximum latency). VDDQ3 6, 9, 13, 21, 27 P Power Connection: Connected to 3.3V supply. VDDQ2 25 P Power Connection: Power supply for CPU0:1 output buffer. Connected to 2.5V or 3.3V. 3, 12, 14, 20, 22, 28 G Ground Connection: Connect all ground pins to the common system ground plane. Pin Name GND Pin Description 2 PRELIMINARY W48C111-16 Spread Spectrum Feature Where P is the percentage of deviation and F is the frequency in MHz where the reduction is measured. The device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. By increasing the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 1. The output clock is modulated with a waveform depicted in Figure 2. This waveform, as discussed in “Spread Spectrum Clock Generation for the Reduction of Radiated Emissions” by Bush, Fessler, and Hardin produces the maximum reduction in the amplitude of radiated electromagnetic emissions. The deviation selected for this chip is ±0.5% of the center frequency. Figure 2 details the Cypress spreading pattern. Cypress does offer options with more spread and greater EMI reduction. Contact your local Sales representative for details on these devices. As shown in Figure 1, a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. The reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. The equation for the reduction is: Spread Spectrum clocking is always active on this device. dB = 6.5 + 9*log10(P) + 9*log10(F) 5dB /div Typ ical C lock Amplitude (dB) S SFT G -SS % F requ en cy Sp an (M Hz) +S S% Figure 1. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation MIN (–0.5%) Figure 2. Typical Modulation Profile 3 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% FREQUENCY MAX (+0.5%) PRELIMINARY W48C111-16 Absolute Maximum Ratings above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions Parameter Description Rating Unit V VDD, VIN Voltage on any pin with respect to GND –0.5 to +7.0 –65 to +150 °C 0 to +70 °C –55 to +125 °C 2 (min.) kV TSTG Storage Temperature TA Operating Temperature TB Ambient Temperature under Bias ESDPROT Input ESD Protection DC Electrical Characteristics: TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, VDDQ2 = 2.5V±5%, CPU0:1 = 66.6/100 MHz Parameter Description Test Condition IDD3 Combined 3.3V Supply Current Outputs Loaded[1] IDD2 2.5V Supply Current Min. Typ. Max. Unit 80 mA 40 mA Supply Current Logic Inputs VIL Input Low Voltage GND – 0.3 0.8 V VIH Input High Voltage 2.0 VDD + 0.3 V IIL Input Low Current[2] –25 µA IIH Input High Current[2] 10 µA IIL Input Low Current (SEL100/66#) –5 µA IIH Input High Current (SEL100/66#) 5 µA 50 mV Clock Outputs VOL Output Low Voltage VOH Output High Voltage IOH = –1 mA 3.1 V VOH Output High Voltage CPU0:1 IOH = –1 mA 2.2 V IOL Output Low Current CPU0:1 VOL = 1.25V 55 115 190 mA PCI_F, PCI1:5 VOL = 1.5V 20.5 53 139 mA REF VOL = 1.5V 25 37 76 mA CPU0:1 VOL = 1.25V 50 110 195 mA PCI_F, PCI1:5 VOL = 1.5V 31 55 189 mA REFX VOL = 1.5V 27 44 94 mA IOH Output High Current IOL = 1 mA Crystal Oscillator VTH X1 Input Threshold Voltage[3] CLOAD Load Capacitance, as seen by External Crystal[4] CIN,X1 X1 Input Capacitance[5] VDDQ3 = 3.3V Pin X2 unconnected 1.65 V 14 pF 28 pF Pin Capacitance/Inductance CIN Input Pin Capacitance COUT LIN Except X1 and X2 5 pF Output Pin Capacitance 6 pF Input Pin Inductance 7 nH Notes: 1. All clock outputs loaded with 6" 60Ω transmission lines with 20-pF capacitors. 2. CPU_STOP#, PCI_STOP#, and PWRDWN# logic inputs have internal pull-up resistors (pull-ups not CMOS level). 3. X1 input threshold voltage (typical) is VDDQ3/2. 4. The W48C111-16 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 14 pF; this includes typical stray capacitance of short PCB traces to crystal. 5. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected). 4 PRELIMINARY W48C111-16 AC Electrical Characteristics TA = 0°C to +70°C, VDDQ3 = 3.3V±5%,VDDQ2 = 2.5V± 5%, fXTL = 14.31818 MHz AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output. CPU Clock Outputs, CPU0:1 (Lump Capacitance Test Load = 20 pF) CPU = 66.6 MHz Parameter Description Test Condition/Comments CPU = 100 MHz Min. Typ. Max. Min. Typ. Max. Unit tP Period Measured on rising edge at 1.25V 15 tH High Time Duration of clock cycle above 2.0V 5.2 3.0 ns tL Low Time Duration of clock cycle below 0.4V 5.0 2.8 ns tR Output Rise Time Measured from 0.4V to 2.0V 0.4 1.6 0.4 1.6 V/ns tF Output Fall Time Measured from 2.0V to 0.4V 0.4 1.6 0.4 1.6 V/ns tD Duty Cycle Measured on rising and falling edge at 1.25V 45 55 45 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.25V. Maximum difference of cycle time between two adjacent cycles. 200 250 ps tSK Output Skew Measured on rising edge at 1.25V 175 175 ps fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 15.5 13.5 10 10.5 ns Ω 13.5 PCI Clock Outputs, PCI1:5 and PCI_F (Lump Capacitance Test Load = 30 pF CPU = 66.6/100 MHz Parameter Description Test Condition/Comments Min. Typ. Max. Unit tP Period Measured on rising edge at 1.5V 30 ns tH High Time Duration of clock cycle above 2.4V 12 ns tL Low Time Duration of clock cycle below 0.4V 12 tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1 4 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. 250 ps tSK Output Skew Measured on rising edge at 1.5V 500 ps tO CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on rising edge at 1.5V. CPU leads PCI output. 4 ns fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 5 ns 1.5 30 Ω PRELIMINARY W48C111-16 REF Clock Output (Lump Capacitance Test Load = 20 pF) CPU = 66.6/100 MHz Parameter Description Test Condition/Comments f Frequency, Actual Frequency generated by crystal oscillator Min. Typ. Max. 14.318 Unit MHz tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1 4 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % tJC Jitter, Cycle to Cycle Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. 500 ps fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. Ω 40 48-MHz Clock Output (Lump Capacitance Test Load = 20 pF) CPU = 66.6/100 MHz Parameter Description Test Condition/Comments Min. Typ. Max. Unit f Frequency, Actual Determined by PLL divider ratio (see m/n below) fD Deviation from 48 MHz (48.008 – 48)/48 m/n PLL Ratio (14.31818 MHz x 57/17 = 48.008 MHz) tR Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % tJC Jitter, Cycle to Cycle Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. 500 ps fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. Ordering Information Ordering Code W48C111 Freq. Mask Code Package Name -16 H Package Type 28-pin SSOP (209 mils) Document #: 38-00844 6 48.008 MHz +167 ppm 57/17 40 Ω PRELIMINARY W48C111-16 Package Diagram 28-Pin Small Shrink Outline Package (SSOP, 209 mils) © Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.