S6J3120 Series
32-bit Microcontroller Traveo Family
Fact Sheet
®
®
The Traveo™ family S6J3120, features 32-bit RISC microcontrollers with an ARM Cortex -R5 core and operate at 112MHz.
1 MB of Flash memory is correspond to the software capacity.CAN-FD is introduced as a communication interface anditis compatible
with the conventional CAN and it can shorten the time of re-programming by high-speed communication.Moreover, this microcontroller
has SHE(Secure Hardware Extension) as security function. It will prevent the extraction and alteration of the data or keys. This
microcontroller can control safely and quickly the circumference function of Cluster in which an increase will be expected from now on
.
Features
Product Lineup
32bit ARM® Cortex®-R5 CPU Core
Clock
Part number
Parameter
Maximum clock frequency: 128MHz
DMA controller: 16 channels
External interrupt: 16 channels
Base timer: 30 channels
32-bit free-run timer: 6 channels
32-bit input capture: 12 channels
32-bit output compare: 12 channels
12-bit A/D converter: 50 channels (2 units total)
Real Time Clock
Multi-function serial interface: 10 channels, Selectable from
UART/CSIO/LIN/I2C(Max 100kbps)
CAN-FD(192msb[reception]): 3 channels
LCD Controller: 32seg x 4com
Sound Generator: 3 channels
Stepping Motor Controller: 4 channels
Exclusion access memory
Watchdog timer: 1 channel(SW)+1 channel(HW)
CRC generation: 1 channel
Secure Hardware Extension
General Purpose I/O port: 112
Built-in CR oscillator
Debug interface
JTAG Debug Port
Partial-wakeup function
Low Voltage Detector
Clock Supervisor
Power Supply: 1 power voltage(5V)
S6J312AHxB S6J3129HxB S6J3128HxB
Main Flash(Byte) 1024K+64K
Work Flash(Byte)
112K
RAM(Byte)
80K
Backup RAM(Byte)
8K
768K+64K
112K
64K
8K
512K+64K
112K
48K
8K
Ordering Information
Part number
S6J312AHABSEx0000
S6J3129HABSEx0000
S6J3128HABSEx0000
S6J312AHBBSEx0000
S6J3129HBBSEx0000
S6J3128HBBSEx0000
Package
Plastic
TEQFP(0.5mm pitch),
144pin
Package Example of Reference
Plastic・TEQFP144,144pin
Cypress Semiconductor Corporation
Document Number: 002-08976 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 19, 2016
S6J3120 Series
Block Diagram
Trace I/F(8Pin)
Debug I/F (JTAG/SWD)
Power Domain 2
JTAG_SWCLKTCK
JTAG Wakeup
Debug Group
(CoreSightTM)
Bus Config Group
From/To PPU-SLAVEs
- Bus Performance Counters
- Misc Register Module
DAP
Security
CLK_DBG
CLK_LLPBM2
APB-M
APB-S
AHB-M
PPU Master
CLK_HPM
Debug APB
AHB2APB
(Priviledge
Protection)
APB-32
CLK_HPM
CLK_LLPBM2
Trace Group
CLK_TRC
From/To
CommonPERI#2
From/To
CommonPERI#2
Security
Checker
ETB (Trace Buffer)
16KB
CLK_ATB
CLK_DBG
ATB
Core Group (1-Core)
Power Domain 3
Debug APB
CLK_CPU
Flash Group
SHE Group
CLK_FCLK
CLK_SHE
WorkFlash
TCF
AHB-64
AHB-64
(Reg & Data) (Reg)
CLK_CPU
TCFLASH #0
1MB + 64KB
+
EEFlash #0
112KB
CLK_MEMC
From/To
Memory Config Grp.
ETMTM
#0
TCF
AXI-64
(data)
Procceser
TCRAM #0
(2bank)
64KB
(32KB×2)
CPU #0
B0TCM
MPU
#0
EBI Group
- DMAC 16.ch
- ReloadTimer 4ch
CLK_DMA
ATCM
#0
TCF
ATCM #0
DDRHSSPI Group
DMAC Complex #0
CortexTM -R5
B1TCM
#0
I$
#0
D$
#0
16KB
16KB
DDR
HSSPI
EBI
AXI2AHB
AXI2AHB
CLK_HPM
AHB-64
CLK_MEMC
AXI-64
AHB-32
CLK_SHE
CLK_SHE
AHB-64
CLK_MEMC
From/To
Memory Config Grp.
AXI-64
LLPP
AXI32-M AHB32
AXI-M AXI-S
CLK_CPU
AXI-64
CLK_CPU
AXI-64
CLK_CPU
AXI-32
CLK_CPU
From/To CommonPERI#2
DMAC Config
AHB-32
CLK_HPM2
AHB-32
CLK_CPU
AHB-64
CLK_HPM
AHB-32
CLK_HPM2
AXI-32
CLK_HSSPI
AXI-32
CLK_EXTBUS
High Performance Matrix (HPM)
AHB-32
CLK_CPU
AXI-64
AXI-64
AHB-32
CLK_HPM
CLK_HPM
System SRAM
16KB
AHB-32
CLK_SYSC1
EAM
AHB-64
CLK_HPM
From/To
Flash Group
CLK_MEMC
CLK_HPM
AHB-32
BBU
BBU
AHB-32
CLK_LLPBM
Low Latency Peripheral Bus Matrix (LLPBM)
CLK_LLPBM
AHB-32
BBU
State manage (2)
BBU
Power Domain 6_0
Clock divide
and distribution
CLK_COMH
Power
Domain 4_1
System
Controller(SYSC)
Reset manage
CLK_LCP
BootROM
16KB
SW-Watchdog
CSV(for PLL)
Timing
Protection
SYSC1
CLK_MEMC
Wakeup
Request #0
#0 TCM SRAM
(Config)
CSV
Memory & Config Group
Fast-CR
Slow-CR
CLK_MEMC
CLK_LCP1A
Reload Timer
4ch
M.F.S
5ch
QPRC
2ch
32Bit FRT
6ch
M.F.S
5ch
32Bit ICU
12ch
SMC
4ch
32Bit OCU
12ch
LCDC
32seg×4com
Peripheral
Bus Bridge
CLK_LLPBM2
P
Bus Config
Group
(Config)
P
Reload Timer
2ch
DMAC
Complex #0
(Config)
PPU Master
(Cnofig)
12Bit A/DC
Unit0×22ch
Reload Timer
4ch
Wakeup-detect
RTC
CLK_LCP0A
Base Timer
30ch
Power Domain 3
PLL0
SSCG PLL0
Clock Calibration
CLK_HPM
GPIO
RAM
State manage
Peripheral
Bus Bridge
C
Peripheral
Bus Bridge
CRC
4ch
IRC #0
512 Vectors
PONR
LVD
CLK_CAN
CLK_LCP1A
Peripheral
Bus Bridge
(TPU) #0
CLK_SYSC1
Power manage
Source Clock
Timer
CLK_LCP0A
CAN-FD
3ch
RAM
Clock manage
EICU 16ch
CAN Prescaler (CLK_CAN)
Backup RAM 4KB
(8+5 bit width RAM x 4)
Backup RAM 4KB
(8+5 bit width RAM x 4)
CLK_RAM1H
Power CLK_RAM0H
Domain 4_0
CLK_LLPBM
BBU
Flash Group I/F
CLK_SYSCH0H
ECC-ed RAM I/F
AHB-32
CLK_LLPBM
CLK_LLPBM
From/To
Core-Group
AHB-32
CLK_LLPBM
BBU
Common PERI #1
Group
Common PERI #2
Group
SG
3ch
Common PERI #0
Group
H/W Watchdog
EXT-IRQ
16ch
NMI
MCU Config Group
Power Domain 1
(Always on)
Document Number: 002-08976 Rev. *A
12Bit A/DC
Unit1×28ch
Common PERI #0
Group
Power Domain 1 (Always on)
Page 2 of 4
S6J3120 Series
Document History
Document Title: S6J3120 Series, 32-bit Microcontroller Traveo Family Fact Sheet
Document Number: 002-08976
Revision
ECN
Orig. of
Change
Submission
Date
**
−
NNAK
11/14//2014
*A
5159040
HIOT
04/20/2016
Document Number: 002-08976 Rev. *A
Description of Change
Migrated to Cypress and assigned document number 002-08976.
No change to document contents or format.
Updated to Cypress template
Added SHE-OFF option and updated revision
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S6J3120 Series
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Document Number: 002-08976 Rev. *A
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