E14506

SP7T+SP7T Diversity Antenna Switch with MIPI Interface
CXM3641ER
Description
The CXM3641ER is a SP7T+SP7T middle power switch with an integrated MIPI controller for
wireless communication system.
The Sony GaAs Junction gate pHEMT (JPHEMT) MMIC process is used for low insertion loss
and high linearity.
Features

Low Insertion Loss:
0.27 dB (Typ.) at 900MHz
0.34 dB (Typ.) at 2GHz

Low Voltage Operation:
VDD = 2.5 V

Supports Qualcomm MIPI interface

No DC Blocking Capacitor (except external DC bias)

Small Package Size:

Lead-Free and RoHS Compliant
VQFN-24P (2.4 mm x 3.2 mm x 0.725 mm Typ.)
Structure
GaAs Junction gate pHEMT (JPHEMT) MMIC Switch, CMOS Decoder
Moisture Sensitivity
Moisture Sensitivity Level for this part is MSL = 2
Absolute Maximum Ratings
(Ta = 25 ℃)
Bias voltage
VDD
6
V
Control voltage
SDATA
2.5
V
SCLK
2.5
V
VIO
2.5
V
Input power max.(TRx)
32
dBm
Operating temperature range
-35 to +90
℃
Storage temperature range
-65 to +150
℃
This IC is ESD sensitive device. Special handling precautions are required.
1
CXM3641ER
Block Diagram of SP7T+SP7T Antenna Switch Module with MIPI Interface
2
CXM3641ER
Block Diagram of SP7T+SP7T
AntHB
AntLB
F1
F2
F3
F4
F5
F6
F7
F8
F9
F15
F16
F17
F18
F19
F20
F21
F22
F23
F10
F24
F12
F11
F25
F13
F26
F27
F14
F28
TRx
TRx
TRx
TRx
TRx
TRx
TRx
TRx
TRx
TRx
TRx
TRx
TRx
TRx
HB1
HB2
HB3
HB4
HB5
HB6
HB7
LB1
LB2
LB3
LB4
LB5
LB6
LB7
Truth Table
HB SP7T (Register0)
HB
State
Path
1
2
3
4
5
6
7
8
LB SP7T
Isolation
ANTHB-TRxHB1
ANTHB-TRxHB2
ANTHB-TRxHB3
ANTHB-TRxHB4
ANTHB-TRxHB5
ANTHB-TRxHB6
ANTHB-TRxHB7
(Register 0x0001)
HB Series
D2
D1
D0
F1
F2
F3
F4
F5
F6
F7
F15
F16
F17
F18
F19
F20
F21
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
LB
State
Path
9
10
11
12
13
14
15
16
Isolation
ANTLB-TRxLB1
ANTLB-TRxLB2
ANTLB-TRxLB3
ANTLB-TRxLB4
ANTLB-TRxLB5
ANTLB-TRxLB6
ANTLB-TRxLB7
HB Shunt
LB Series
LB Shunt
D2
D1
D0
F8
F9
F10
F11
F12
F13
F14
F22
F23
F24
F25
F26
F27
F28
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
State “L” means a switch “OFF”, state “H” means a switch “ON”.
3
CXM3641ER
Pin Configuration
VQFN-24P PKG
(2.4 mm x 3.2 mm x 0.725 mm Typ.)
Top View
4
CXM3641ER
Electrical Characteristics
(VDD = 2.5 V, Ta = 25 ℃)
Parameter
Insertion Loss
Symbol
IL
Path
Condition
Min.
Typ.
Max.
ANTLB-TRxLB1
-
0.32
0.42
ANTLB-TRxLB2
-
0.32
0.42
ANTLB-TRxLB3
-
0.30
0.42
-
0.29
0.42
ANTLB-TRxLB5
-
0.31
0.42
ANTLB-TRxLB6
-
0.29
0.42
ANTLB-TRxLB7
-
0.27
0.42
ANTHB-TRxHB1
-
0.37
0.60
ANTHB-TRxHB2
-
0.39
0.60
ANTHB-TRxHB3
-
0.40
0.60
-
0.36
0.60
ANTHB-TRxHB5
-
0.37
0.60
ANTHB-TRxHB6
-
0.36
0.60
ANTHB-TRxHB7
-
0.34
0.60
ANTHB-TRxHB1
-
0.36
0.65
ANTHB-TRxHB2
-
0.41
0.65
ANTHB-TRxHB3
-
0.40
0.65
-
0.37
0.65
ANTHB-TRxHB5
-
0.39
0.65
ANTHB-TRxHB6
-
0.39
0.65
ANTHB-TRxHB7
-
0.36
0.65
ANTHB-TRxHB1
-
0.47
0.80
ANTHB-TRxHB2
-
0.58
0.80
ANTHB-TRxHB3
-
0.57
0.80
-
0.55
0.80
ANTHB-TRxHB5
-
0.62
0.80
ANTHB-TRxHB6
-
0.65
0.80
ANTHB-TRxHB7
-
0.67
0.80
600 to 2170MHz
-
1.2
-
2500 to 2700MHz
-
1.4
-
ANTLB-TRxLB4
*1,*2
ANTHB-TRxHB4
*3
Unit
dB
ANTHB-TRxHB4
*4
ANTHB-TRxHB4
VSWR
VSWR
*5
All ports in active paths
-
5
CXM3641ER
Electrical Characteristics
(VDD = 2.5 V, Ta = 25 ℃)
Parameter
Harmonics
Symbol
2fo
Path
Condition
Min.
Typ.
Max.
-
-69
-55
-
-71
-55
-
-67
-55
-
-75
-55
*6,*15,*16
-
-
-105
*6,*17,*18
-
-
-105
*6,*7,*8,*11*12,*19,*20
-
-
-105
*6,*9,*10,*13,*14,*21,*22
-
-
-105
*6,*24
65
68
-
ANTLB-TRxLB1~TRxLB7
*2
3fo
2fo
ANTHB-TRxHB1~TRxHB7
dBm
*3,*5
3fo
IMD2
Inter Modulation Distortion
ANTLB-TRxLB1~TRxLB7
IMD3
Unit
dBm
dBm
in Rx Band
IMD2
ANTHB-TRxHB1~TRxHB7
IMD3
IIP3
Input IP3
ANTLB-TRxLB1~TRxLB7
ANTHB-TRxHB1~TRxHB7
ANTHB-TRxHB1~TRxHB7
dBm
*6,*23
65
68
-
Electrical Characteristics are measured with all RF ports terminated in 50 .
* 1 Pin = 25dBm, 704 to 787 MHz
(Band13, Band17)
* 2 Pin = 26dBm, 824 to 960 MHz
(Band5, Band8)
* 3 Pin = 26dBm, 1710 to 1990 MHz
(Band1 Tx, Band 2 Tx, Band 3 Tx, Band 4 Tx)
* 4 Pin = 10dBm, 2110 to 2170 MHz
(Band1 Rx, Band4 Rx)
* 5 Pin = 26dBm, 2500 to 2690 MHz
(Band7)
* 6 Measured with the recommended circuit.
6
CXM3641ER
Electrical Characteristics
(VDD = 2.5 V, Ta = 25 ℃)
Parameter
Isolation
Parameter
Isolation
Symbol
ISO.
Symbol
ISO.
Path
Condition
Min.
Typ.
Max.
ANTLB-TRxLB1
*1,*2
25
28
-
ANTLB-TRxLB2
*1,*2
23
26
-
ANTLB-TRxLB3
*1,*2
23
26
-
ANTLB-TRxLB4
*1,*2
25
29
-
ANTLB-TRxLB5
*1,*2
25
28
-
ANTLB-TRxLB6
*1,*2
27
30
-
ANTLB-TRxLB7
*1,*2
23
26
-
Condition
Min.
Typ.
Max.
*3,*4
20
24
-
*5
18
22
-
*3,*4
18
21
-
*5
16
20
-
*3,*4
19
23
-
*5
18
22
-
*3,*4
20
24
-
*5
19
23
-
*3,*4
19
23
-
*5
18
22
-
*3,*4
20
23
-
*5
18
21
-
*3,*4
17
21
-
*5
15
18
-
Path
ANTHB – TRxHB1
ANTHB – TRxHB2
ANTHB – TRxHB3
ANTHB – TRxHB4
Unit
dB
Unit
dB
ANTHB – TRxHB5
ANTHB – TRxHB6
ANTHB – TRxHB7
Electrical Characteristics are measured with all RF ports terminated in 50 .
* 1 Pin = 25dBm, 704 to 787 MHz
(Band13, Band17)
* 2 Pin = 26dBm, 824 to 960 MHz
(Band5, Band8)
* 3 Pin = 26dBm, 1710 to 1990 MHz
(Band1 Tx, Band 2 Tx, Band 3 Tx, Band 4 Tx)
* 4 Pin = 10dBm, 2110 to 2170 MHz
(Band1 Rx, Band4 Rx)
* 5 Pin = 26dBm, 2500 to 2690 MHz
(Band7)
* 6 Measured with the recommended circuit.
7
CXM3641ER
ANT to TRx
Isolation Matrix (Min.)
(VDD = 2.5 V, Ta = 25 ℃)
Isolation (dB)
Active
Condition
Path (ANTLB - TRxLB)
TRxLB1
TRxLB2
TRxLB3
TRxLB4
TRxLB5
TRxLB6
TRxLB7
23
32
36
32
30
23
18
24
25
23
22
16
2170MHz
18
23
24
22
21
15
2690MHz
16
21
22
20
18
13
23
33
32
29
23
19
25
23
21
16
960MHz
1990MHz
TRxLB1
-
960MHz
25
1990MHz
20
TRxLB2
2170MHz
19
19
24
22
20
15
2690MHz
18
17
22
20
18
13
960MHz
32
24
25
33
30
23
1990MHz
24
20
20
23
21
16
TRxLB3
2170MHz
23
20
20
22
20
15
2690MHz
21
18
19
20
18
13
960MHz
35
34
26
29
32
24
1990MHz
25
26
21
21
22
16
TRxLB4
2170MHz
24
25
20
20
21
15
2690MHz
21
23
19
19
18
13
960MHz
35
37
35
28
27
24
1990MHz
25
26
25
21
19
16
TRxLB5
2170MHz
24
25
24
21
18
15
2690MHz
21
23
22
20
17
12
960MHz
35
36
36
34
25
1990MHz
25
26
25
24
19
TRxLB6
26
16
-
2170MHz
24
25
24
23
19
15
2690MHz
21
23
22
21
17
12
960MHz
35
37
36
35
34
30
1990MHz
25
26
26
24
23
20
2170MHz
24
25
24
23
22
19
2690MHz
21
22
22
21
19
17
TRxLB7
-
8
CXM3641ER
ANT to TRx
Isolation Matrix (Min.)
(VDD = 2.5 V, Ta = 25 ℃)
Isolation (dB)
Active
Condition
Path (ANTHB - TRxHB)
TRxHB1
TRxHB2
TRxHB3
TRxHB4
TRxHB5
TRxHB6
TRxHB7
24
33
39
36
32
25
19
27
29
27
25
19
2170MHz
18
26
28
26
24
18
2690MHz
16
24
26
24
21
16
24
35
35
31
24
20
28
26
24
18
960MHz
1990MHz
TRxHB1
-
960MHz
26
1990MHz
21
TRxHB2
2170MHz
20
19
27
25
23
17
2690MHz
18
18
25
23
21
15
960MHz
34
25
26
36
32
24
1990MHz
27
21
21
26
24
18
TRxHB3
2170MHz
26
20
20
25
23
17
2690MHz
24
19
19
23
21
15
960MHz
38
35
27
29
35
25
1990MHz
29
29
22
23
25
18
TRxHB4
2170MHz
28
28
21
22
24
18
2690MHz
25
26
20
21
21
15
960MHz
39
40
37
28
28
26
1990MHz
29
30
29
23
21
18
TRxHB5
2170MHz
28
29
28
22
20
17
2690MHz
25
27
25
21
18
15
960MHz
39
40
40
36
25
1990MHz
29
30
29
27
20
TRxHB6
28
18
-
2170MHz
28
29
28
26
19
17
2690MHz
25
27
26
24
18
15
960MHz
40
41
41
40
37
31
1990MHz
30
31
30
29
27
23
2170MHz
29
30
29
27
26
22
2690MHz
26
27
26
25
23
19
TRxHB7
-
9
CXM3641ER
IMD Condition
fRx
fTx
fBlocker
on TRx
+20dBm on TRx
-15dBm on ANT
IMD
Band
Condition
[MHz]
Band 1
Band 2
Band 5
Band 7
2140
1960
880
2655
[MHz]
[MHz]
IMD2(fRx - fTx)
190
*7
IMD2(fRx + fTx)
4090
*8
IMD3(2fTx - fRx)
1760
*9
IMD3(2fTx + fRx)
6040
*10
IMD2(fRx - fTx)
80
*11
IMD2(fRx + fTx)
3840
*12
IMD3(2fTx - fRx)
1800
*13
IMD3(2fTx + fRx)
5720
*14
IMD2(fRx - fTx)
45
*15
IMD2(fRx + fTx)
1715
*16
IMD3(2fTx - fRx)
790
*17
IMD3(2fTx + fRx)
2550
*18
IMD2(fRx - fTx)
120
*19
IMD2(fRx + fTx)
5190
*20
IMD3(2fTx - fRx)
2415
*21
IMD3(2fTx + fRx)
7725
*22
1950
1880
835
2535
*Electrical characteristics are measured with all RF ports terminated in 50 .
Measured with the recommended circuit
f1
f2
IIP3 Condition
+27dBm on TRx
+27dBm on TRx
IIP3=(3*Pout-IMD3) / 2
[MHz]
[MHz]
[dBm]
Band 1
1950
1951
*23
Band 5
835
836
*24
Band
*Electrical characteristics are measured with all RF ports terminated in 50 .
Measured with the recommended circuit
10
CXM3641ER
MIPI Specification
Features

PM_TRIG with three triggers

Software reset and debug using the RFFE_STATUS register

Register 0 write

Full speed write, Half speed read

GSID

Programmable USID
Control Characteristics
Parameter
Symbol
Min.
Typ.
Max.
Unit
Supply Voltage
VDD
2.5
2.8
5.0
V
IDD
-
200
400
uA
IDD
-
-
10
uA
VIO
1.65
1.8
1.95
V
200
400
uA
10
uA
Supply current
(ACTIVE) *VDD=2.5V
Supply current
Low Power(disable) *VDD=2.5V
Interface Supply Voltage
Supply current
(ACTIVE) *VIO=1.8V
Supply current
Low Power(disable) *VIO=1.8V
Ivio
Ivio
Signal level low
Vcl
0
-
0.2xVIO
V
Signal level high
Vch
0.8xVIO
-
VIO
V
SCLK write Frequency
fSCLKw
0.032
19.2
26
MHz
SCLK read Frequency
fSCLKr
0.032
9.6
13
MHz
SDATA/SCLK input capacitance
Cin
2
3
pF
Data setup time
Ts
2
ns
Data hold time
Th
5
ns
Switching Time *
Tsw
-
-
5
us
Turn on Time **
Ton
-
-
100
us
* Switching Time: Timing for switching from an arbitrary state to the next state.
**Turn on time: Time to guarantee RF performance after IC shifts to active mode.
11
CXM3641ER
Explanation of Register
Register Address
Register Name
Data Bits
Notes
Read
Write
0x0000
0x00001
0x001A
0x001B
0x001C
REGISTER_0
HB Ant SW States
(Table A or B)
LB Ant SW States
(Table C)
RFFE_STATUS
(Table D)
GROUP_ID
(Table E)
PM_TRIG
(Table F)
7
HB Antenna sw itch states (see Truth Table)
Register 0 Write command sequence use.
Trigger Supprt.
HB Antenna sw itch states (see Truth Table)
Read/Write command sequence use.
Trigger Supprt.
LB Antenna sw itch states (see Truth Table)
Read/Write command sequence use.
Trigger Supprt.
SOFTWARE RESET
6
COMMAND_FRAME_PARITY_ERR
5
COMMAND_LENGTH_ERR
4
ADDRESS_FRAME_PARITY_ERR
3
DATA_FRAME_PARITY_ERR
2
READ_UNUSED_REG
1
WRITE_UNUSED_REG
0
BID_GID_ERR
6:0
7:0
7:0
7:4
RESERVED
3:0
GROUP_SID
7:6
Pow er mode
5:3
Trigger_Mask_[2:0]
2:0
Trigger_[2:0]
W
R/W
R/W
R/W
R/W
R/W
0x001D
PRODUCT_ID
(Table G)
7:0
PRODUCT_ID
R
0x001E
MANUFACTURER_ID
(Table H)
7:0
MANUFACTURER_ID[7:0]
R
7:6
SPARE
R
0x001F
SPARE
MANUFACTURER_ID
USID
(Table I)
5:4
MANUFACTURER_ID[9:8]
3:0
USID
MANUFACTURER_ID[9:0] is defined by SONY ID (0x01B0)
SSEL Level GND : USID 1010
SSEL Level VIO : USID 1011
12
R
R/W
CXM3641ER
Write and Read command sequence
- REGISTER_0 Write command sequence
SCLK
SDATA
SSC
SA3
SA2
SA1
SA0
1
D6
D5
D4
D3
D2
D1
D0
Slave Address
P
0
Parity
Bit
Bus
Park
- Write command sequence (except REGISTER_0)
SCLK
SDATA
SSC
SA3
SA2
SA1
SA0
Slave Address
0
1
0
A4
A3
Write Command
A2
A1
A0
P
D7
D6
D5
D4
D3
D2
D1
D0
Parity
Bit
Register Address
P
0
Parity
Bit
Bus
Park
- Read command sequence
Data frame from ANT Switch needs Half Speed function
①
SCLK
SDATA
SSC
SA3
SA2
SA1
SA0
Slave Address
SCLK
SDATA
0
1
1
A4
Read Command
A3
A2
A1
A0
P
0
Parity
Bit
Register Address
Bus
Park
①
0
Bus
Park
D7
D6
D5
D4
D3
D2
Data f rame f rom ANT Sw itch (Read Half Speed)
13
D1
D0
P
Bus
Park
CXM3641ER
Register Map
Command Frame
Initial value :
[D6:D0]
=000 0000
Table B REGISTER_0 for HB ANT Switch State (0x0000)
Items
Bit
Description
SA3 1
Slave
SA2 0
Address of Diversity Switch
Address SA1 1
SA0 0/1
C2
0
Read
Write : 010
C1
1
Write
Read: 011
C0 0/1
A4
0
A3
0
Register
A2
0 Register Address: 0x0000
Address
A1
0
A0
0
Parity Bit
P
0/1 Parity bit for Command Frame
D7
0
D6
0
D5
0 Switch State
Initial value :
D4
0 See the truth table
Data
[D7:D0]
D3
0
=0000 0000
D2 0/1 Trigger Supprt.
D1 0/1
D0 0/1
Parity Bit
P
0/1 Parity bit for Data Frame
Data Frame
Command Frame
Table A REGISTER_0 for HB ANT Switch State (0x0000)
Items
Bit
Description
SA3 1
Slave
SA2 0
Address of Diversity Switch
Address SA1 1
SA0 0/1
C0
1 REGISTER_0 Write : 1
D6
0
D5
0
Switch State
D4
0
See the truth table
Data
D3
0
D2 0/1 Trigger Supprt.
D1 0/1
D0 0/1
Parity Bit
P
0/1 Parity bit for Frame
Data Frame
Command Frame
Table C LB ANT Switch State (0x0001)
Items
Description
Bit
SA3 1
Slave
SA2 0
Address of Diversity Switch
Address SA1 1
SA0 0/1
C2
0
Read
Write : 010
C1
1
Write
Read: 011
C0 0/1
A4
0
A3
0
Register
A2
0 Register Address: 0x0001
Address
A1
0
A0
1
Parity Bit
P
0/1 Parity bit for Command Frame
D7
0
D6
0
D5
0 Switch State
Initial value :
D4
0 See the truth table
Data
[D7:D0]
D3
0
=0000 0000
Trigger
Supprt.
D2 0/1
D1 0/1
D0 0/1
Parity Bit
P
0/1 Parity bit for Data Frame
14
CXM3641ER
Command Frame
Table D RFFE_STATUS
Items
Bit
SA3 1
Slave
SA2 0
Address SA1 1
SA0 0/1
C2
0
Read
C1
1
Write
C0 0/1
A4
1
A3
1
Register
A2
0
Address
A1
1
A0
0
Parity Bit
P
0/1
Data Frame
Parity Bit
Data Frame
Write : 010
Read: 011
Register Address: 0x001A
D5
0/1 Command length error
D4
D3
D2
D1
D0
P
0/1
0/1
0/1
0/1
0/1
0/1
Command Frame
Parity Bit
Address of Diversity Switch
D6
Table E GROUP_ID
Items
SA3
Slave
SA2
Address SA1
SA0
C2
Read
C1
Write
C0
A4
A3
Register
A2
Address
A1
A0
Parity Bit
P
Data
Description
Parity bit for Command Frame
0: Normal operation
0/1 1: Software reset (reset of all configurable registers to default values,
except for USID、PM_TRIG、GSID)
0/1 Command sequence received with parity error – discard command.
D7
Data
(0x001A)
(0x001B)
Bit Description
1
0
Address of Diversity Switch
1
0/1
0
Write : 010
1
Read: 011
0/1
1
1
0 Register Address: 0x001B
1
1
0/1 Parity bit for Command Frame
D7
0
D6
0
D5
0
D4
D3
D2
D1
D0
P
Address frame parity error = 1
Data frame with parity error
Read command to an invalid address
Write command to an invalid address
Read command with a Broadcast_ID or GROUP_ID
Parity bit for Data Frame
-
0
0/1
0/1
Group slave ID
0/1
0/1
0/1 Parity bit for Data Frame
Initial value :
[D3:D0]
=0000
15
Initial value :
[D7:D0]
=0000 0000
CXM3641ER
Parity Bit
D1
D0
P
Initial value :
[D7:D6]
=10
Initial value :
[D5:D3]
=000
Parity Bit
D2
0
D1
D0
P
0
0
0 Parity bit for Data Frame
Data Frame
Data Frame
0 Manufacturer ID [7:0]:B0h (SONY ID)
Command Frame
Table I Register for
Items
SA3
Slave
SA2
Address SA1
SA0
C2
Read
C1
Write
C0
A4
A3
Register
A2
Address
A1
A0
Parity Bit
P
D7
D6
D5
D4
Command Frame
Parity Bit
D3
Data
Initial value :
[D5:D3]
=000
Table H Register for Manufacturer ID (0x001E)
Items
Description
Bit
SA3 1
Slave
SA2 0
Address of Diversity Switch
Address SA1 1
SA0 0/1
C2
0
Read
C1
1 Read Only
Write
C0
1
A4
1
A3
1
Register
A2
1 Register Address: 0x001E
Address
A1
1
A0
0
Parity Bit
P 0/1 Parity bit for Command Frame
D7
1
D6
0
D5
1
D4
1
Data
Data Frame
Data Frame
0/1 Trigger_[2:0]
000: Invalid
0/1
other: valid
0/1
0/1 Parity bit for Data Frame
D2
Command Frame
Table G Register for Product ID (0x001D)
Items
Description
Bit
SA3 1
Slave
SA2 0
Address of Diversity Switch
Address SA1 1
SA0 0/1
C2
0
Read
C1
1 Read Only
Write
C0
1
A4
1
A3
1
Register
A2
1 Register Address: 0x001D
Address
A1
0
A0
1
Parity Bit
P
0/1 Parity bit for Command Frame
D7
0
Command Frame
Table F Register for Power Mode & Trigger Mode (0x001C)
Items
Description
Bit
SA3 1
Slave
SA2 0
Address of Diversity Switch
Address SA1 1
SA0 0/1
C2
0
Read
Write : 010
C1
1
Write
Read: 011
C0 0/1
A4
1
A3
1
Register
A2
1 Register Address: 0x001C
Address
A1
0
A0
0
Parity Bit
P
0/1 Parity bit for Command Frame
D7 0/1 00: Normal operation (ACTIVE)
01: Default settings (STARTUP)
D6 0/1 10: Low power (LOW POWER)
11: Reserved
D5 0/1
Trigger_Mask_[2:0]
D4 0/1
Data
111: valid
D3 0/1 other: Invalid
Data
D6
0
D5
D4
0
1
D3
0
D2
0
D1
D0
P
1
1
0
Product ID : 13h
Parity bit for Data Frame
Manufacturer ID and USID (0x001F)
Description
Bit
1
0
Address of Diversity Switch
1
0/1
0
Write : 010
1
Read : 011
0/1
1
1
1 Register Address: 0x001F
1
1
0/1 Parity bit for Command Frame
0
SPARE
0
0
Manufacturer ID [9:8]:01h (SONY ID)
1
D3
0/1
D2
0/1 Programmable USID
Initial value : [D3:D0]
SSEL Level GND : 1010
SSEL Level VIO : 1011
D1 0/1
D0 0/1
Parity Bit
P
0/1 Parity bit for Data Frame
For Programmable USID
The PRODUCT_ID and the MANUFACTURER_ID match, then a new USID is programmed.
16
CXM3641ER
Recommended Circuit
VQFN-24P PKG
(2.4mm x 3.2mm x 0.725mm Typ.)
Top View
*1: No DC blocking capacitors are required on all RF ports (except external DC bias)
*2: The DC levels of all RF ports are GND.
*3: L1(27nH) and C1(12pF) are recommended on ANTHB port for ESD protection.
*4: L2(27nH) and C2(12pF) are recommended on ANTLB port for ESD protection.
*5: C3(100pF) and C4 (0.1uF) are recommended.
17
CXM3641ER
Recommended Land Pattern
(Unit:mm)
Recommended PCB Design for VQFN-24P
PKG Line
GND Via Hole
18
CXM3641ER
Package Outline
(Unit : mm)
19
CXM3641ER
Marking
20
CXM3641ER
Tape and Reel Size
CXM3641ER-T2
(Unit : mm)
21
CXM3641ER
Note
Sony reserves the right to change products and specifications without prior notice.
This information does not convey any license by any implication or otherwise under any patents or other right.
Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume
responsibility for any problems arising out of the use of these circuits.
22
Similar pages