E15504

Ultra-High Linearity SP4T Switch with MIPI Interface
CXM3653ER
Description
The CXM3653ER is a high power and ultra-high linearity SP4T switch with an integrated MIPI controller for wireless
communication systems. The CXM3653ER can be used for SVLTE and carrier aggregation requiring very high linearity.
The Sony GaAs junction gate pHEMT (JPHEMT) MMIC process is used for low insertion loss and high linearity.
(Application: LTE/CDMA/GSM/UMTS Handsets and mini base-stations)
Features
◆ Low Insertion loss: 0.20 dB (Typ.) @900MHz
0.25 dB (Typ.) @2GHz
◆ High Isolation
: 41 dB (Typ.) @900MHz
33 dB (Typ.) @2GHz
◆ Ultra-high linearity: IIP3=82dBm (Min.) for SVLTE
2f0 = -98 dBm (Typ.) at Band13, Pin=25dBm
3f0 = -100 dBm (Typ.) at Band17, Pin=25dBm
◆ Low voltage operation: VDD = 2.5 V
◆ Supports Qualcomm MIPI interface
◆ No DC blocking capacitors required on RF ports (except external DC bias)
◆ Small package size: VQFN-18 pin (2.4 mm × 2.0 mm)
◆ Lead-Free and RoHS compliant
Structure
GaAs JPHEMT MMIC switch, CMOS decoder
Moisture Sensitivity
Moisture Sensitivity Level for this part is MSL= 2
This IC is ESD sensitive device. Special handling precautions are required.
1
CXM3653ER
Absolute Maximum Ratings
(Ta = 25 ˚C)
♦ Bias voltage
VDD
5.5
V
♦ Control voltage for MIPI
SDATA
2.5
V
SCLK
2.5
V
VIO
2.5
V
36
dBm
♦ Maximum input power
♦ Operating temperature
Topr
–35 to +90
˚C
♦ Storage temperature
Tstg
–65 to +150
˚C
2
(Duty cycle = 12.5 to 50 %)
CXM3653ER
Block Diagram
SP4T Antenna Switch with MIPI I/F
ANT
RF1 (Ultra-High Linearity)
RF2 (Ultra-High Linearity)
RF3 (Ultra-High Linearity)
RF4 (Ultra-High Linearity)
VDD
Regulator
Level Shifter
Decoder
DCDC Converter
VIO
SDATA
SCLK
SSEL
MIPI
I/F
CMOS Switch Controller
MMIC Switch
ANT
F1
F3
F2
F5
RF1
F4
F6
RF2
F7
RF3
F8
RF4
Truth Table
State
Path
1
2
3
4
5
Isolation
ANT-RF1
ANT-RF2
ANT-RF3
ANT-RF4
Data Frame
D2
D1
D0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
F1
OFF
ON
OFF
OFF
OFF
F2
OFF
OFF
ON
OFF
OFF
3
F3
OFF
OFF
OFF
ON
OFF
SW State
F4
F5
F6
F7
F8
OFF ON ON ON ON
OFF OFF ON ON ON
OFF ON OFF ON ON
OFF ON ON OFF ON
ON ON ON ON OFF
CXM3653ER
Pin Configuration
VQFN-18P PKG (2.4mm x 2.0mm)
18
SSEL
1
GND
AA
SCLK
12
11
GND
2
3
4
4
5
GND
17
GND
SDATA
13
GND
16
RF1
VIO
14
RF4
15
GND
VDD
GND
(Top View)
10
RF2
9
GND
8
ANT
7
GND
6
RF3
CXM3653ER
Electrical Characteristics
(VDD = 2.5 V, Ta = 25 °C)
Item
Symbol
Path
ANT-RF1,RF4
Insertion Loss
IL
ANT-RF2,RF3
RF1-RF2,RF3,
RF4
(RF1 Active)
RF2-RF1,RF3,
RF4
(RF2 Active)
Isolation
ISO.
RF3-RF1,RF2,
RF4
(RF3 Active)
RF4-RF1,RF2,
RF3
(RF4 Active)
VSWR
VSWR
ANT-RF1,RF2,
RF3,RF4
2fo
Condition
Min.
Typ.
Max.
*1, *2, *3, *7,*9
―
0.20
0.30
*4, *5, *8, *10
―
0.25
0.35
*6
―
0.30
0.45
*1, *2, *3, *7,*9
―
0.20
0.30
*4, *5, *8, *10
―
0.30
0.40
*6
―
0.35
0.50
*1, *2, *3, *7,*9
38
43
―
*4, *5, *8, *10
30
33
―
*6
27
30
―
*1, *2, *3, *7,*9
36
41
―
*4, *5, *8, *10
30
33
―
*6
27
30
―
*1, *2, *3, *7,*9
36
41
―
*4, *5, *8, *10
30
33
―
*6
27
30
―
*1, *2, *3, *7,*9
38
43
―
*4, *5, *8, *10
30
33
―
*6
27
30
―
704 to 2690 MHz
―
―
1.8
―
-73
-55
―
-70
-55
―
-70
-55
―
-75
-55
―
-82
-65
―
-93
-65
―
-98
-78
-100
-90
*7
3fo
2fo
3fo
Harmonics
2fo
*8
ANT-RF1,RF2,
RF3,RF4
*3,*4,*6
3fo
Inter modulation
distortion in Rx
Band
2fo
*2
3f0
*1
IMD2
*11, *12, *13, *16, *17, *20 ,*21, *24, *25
―
―
-110
*11, *14, *15, *18, *19, *22, *23, *26, *27
―
―
-110
*11, *28
―
―
-104
*11, *29
―
―
-110
IMD3
ANT-RF1,RF2,
RF3,RF4
Electrical characteristics are measured with all RF ports terminated in 50 Ω.
*1
*2
*3
*4
*5
*6
Pin = 25 dBm, 704 to 716 MHz
Pin = 25 dBm, 777 to 787 MHz
Pin = 26 dBm, 824 to 960 MHz
Pin = 26 dBm, 1710 to 1990 MHz
Pin = 10 dBm, 2110 to 2170 MHz
Pin = 26 dBm, 2500 to 2690 MHz
(Band 17 Tx)
(Band 13 Tx)
(Band 5, Band 8)
(Band 1 Tx, Band 2 Tx, Band 3 Tx, Band 4 Tx)
(Band 1 Rx, Band 4 Rx)
(Band 7)
5
Unit
dB
dB
dB
―
dBm
dBm
CXM3653ER
*7
*8
*9
*10
*11
Pin = 35 dBm, 824 to 915 MHz
(GSM850/900 Tx)
Pin = 32 dBm, 1710 to 1910 MHz (GSM1800/1900 Tx)
Pin = 10 dBm, 869 to 960 MHz
(GSM850/900 Rx)
Pin = 10 dBm, 1805 to 1990 MHz (GSM1800/1900 Rx)
Measured with the recommended circuit.
6
CXM3653ER
IMD Condition (1)
Band
Band 1
Band 2
Band 5
Band 7
fRx
on RF
[MHz]
2140
1960
880
2655
fTx
+20 dBm on RF
[MHz]
fBlocker
–15 dBm on ANT
[MHz]
1950
1880
835
2535
IMD condition
IMD2 (fRx – fTx)
190
*12
IMD2 (fRx + fTx)
4090
*13
IMD3 (2fTx – fRx)
1760
*14
IMD3 (2fTx + fRx)
6040
*15
IMD2 (fRx – fTx)
80
*16
IMD2 (fRx + fTx)
3840
*17
IMD3 (2fTx – fRx)
1800
*18
IMD3 (2fTx + fRx)
5720
*19
IMD2 (fRx – fTx)
45
*20
IMD2 (fRx + fTx)
1715
*21
IMD3 (2fTx – fRx)
790
*22
IMD3 (2fTx + fRx)
2550
*23
IMD2 (fRx – fTx)
120
*24
IMD2 (fRx + fTx)
5190
*25
IMD3 (2fTx – fRx)
2415
*26
IMD3 (2fTx + fRx)
7725
*27
IMD Condition (2)
Band
fRx on RF
[MHz]
fTx
PTx = +23 dBm
on RF [MHz]
fBlocker
PBlocker = +14 dBm on ANT
[MHz]
Band 13
747
786
IMD3 (2fTx – fRx)
825
*28
BC0
872
782
IMD3 (fTx + fRx)/2
827
*29
7
IMD condition
CXM3653ER
Triple Beat Ratio
(VDD = 2.5 V, Ta = 25 °C)
Condition
Item
Triple
beat
ratio
Symbol
TBR
Path
ANT-RF1,
RF2,RF3
RF4
Input
power
at RF
[dBm]
Tx1 at
RF
[MHz]
Tx2 at
RF
[MHz]
Jammer
at ANT
–30 dBm
[MHz]
Triple beat
product
at RF
[MHz]
21.5
835.5
836.5
881.5
21.5
1880
1881
13.5
1732
1733
Min.
Typ.
Max.
881.5 ± 1
88
―
―
1960
1960 ± 1
88
―
―
2132
2132 ± 1
88
―
―
Unit
dBc
* Electrical characteristics are measured with all RF ports terminated in 50 Ω.
Measured with the recommended circuit.
IIP2
(VDD = 2.5 V, Ta = 25 °C)
Condition
Item
Input
IP2
Symbol
IIP2
Path
RF1-RF4,
RF3
RF2-RF3,
RF4
Tx
at RF
24 dBm
[MHz]
Jammer
at ANT
–20 dBm
[MHz]
IM2 product
at RF
[MHz]
Min.
Typ.
Max.
836.61
1718.22
881.61
113.5
―
―
836.61
45
881.61
95.5
―
―
1885
3850
1965
95.5
―
―
1885
80
1965
95.5
―
―
1732.5
3865
2132.5
95.5
―
―
1732.5
400
2132.5
95.5
―
―
* Electrical characteristics are measured with all RF ports terminated in 50 Ω.
Measured with the recommended circuit.
8
Unit
dBm
CXM3653ER
MIPI Specification
Features

PM_TRIG with three triggers

Software reset and debug using the RFFE_STATUS register

Register 0 write

Full speed write, Half speed read

GSID

Programmable USID
Control Characteristics
Parameter
Symbol
Min.
Typ.
Max.
Unit
Supply Voltage
VDD
2.5
2.8
5.0
V
IDD
-
140
400
uA
IDD
-
-
10
uA
VIO
1.65
1.8
1.95
V
260
400
uA
10
uA
Supply current
(ACTIVE) *Vdd=2.5V
Supply current
Low Power(disable) *Vdd=2.5V
Interface Supply Voltage
Supply current
(ACTIVE) *Vio=1.8V
Supply current
Low Power(disable) *Vio=1.8V
Ivio
Ivio
Signal level low
Vcl
0
-
0.2xVIO
V
Signal level high
Vch
0.8xVIO
-
VIO
V
SCLK write Frequency
fSCLKw
0.032
19.2
26
MHz
SCLK read Frequency
fSCLKr
0.032
9.6
13
MHz
SDATA/SCLK input capacitance
Cin
2
3
pF
Data setup time
Ts
2
ns
Data hold time
Th
5
ns
Switching Time *
Tsw
-
4.5
6.5
us
Turn on Time **
Ton
-
-
100
us
* Switching Time: Timing for switching from an arbitrary state to the next state.
**Turn on time: Time to guarantee RF performance after switch activation.
9
CXM3653ER
Explanation of Register
Register Address
Register Name
Data Bits
Notes
Read
Write
0x0000
0x0010
0x001A
0x001B
0x001C
6:0
Antenna sw itch states (see Truth Table)
Register 0 Write command sequence use.
Trigger Supprt.
W
7:0
Antenna sw itch states (see Truth Table)
Read/Write command sequence use.
Trigger Supprt.
R/W
7:6
MAJOR REV
5:4
MINOR REV
3:0
MISC VARIANTS
REGISTER_0
(Table A or B)
REVISION_ID
(Table C)
RFFE_STATUS
(Table D)
GROUP_ID
(Table E)
PM_TRIG
(Table F)
7
SOFTWARE RESET
6
COMMAND_FRAME_PARITY_ERR
5
COMMAND_LENGTH_ERR
4
ADDRESS_FRAME_PARITY_ERR
3
DATA_FRAME_PARITY_ERR
2
READ_UNUSED_REG
1
WRITE_UNUSED_REG
0
BID_GID_ERR
7:4
RESERVED
3:0
GROUP_SID
7:6
Pow er mode
5:3
Trigger_Mask_[2:0]
2:0
Trigger_[2:0]
R
R/W
R/W
R/W
0x001D
PRODUCT_ID
(Table G)
7:0
PRODUCT_ID
R
0x001E
MANUFACTURER_ID
(Table H)
7:0
MANUFACTURER_ID[7:0]
R
7:6
SPARE
R
0x001F
SPARE
MANUFACTURER_ID
USID
(Table I)
5:4
MANUFACTURER_ID[9:8]
3:0
USID
MANUFACTURER_ID[9:0] is defined by SONY ID (0x01B0)
SSEL Level GND: USID 1011
SSEL Level VIO : USID 1010
10
R
R/W
CXM3653ER
Write and Read command sequence
- REGISTER_0 Write command sequence
SCLK
SDATA
SSC
SA3
SA2
SA1
SA0
1
D6
D5
D4
D3
D2
D1
D0
Slave Address
P
0
Parity
Bit
Bus
Park
- Write command sequence (except REGISTER_0)
SCLK
SDATA
SSC
SA3
SA2
SA1
SA0
Slave Address
0
1
0
A4
A3
Write Command
A2
A1
A0
P
D7
D6
D5
D4
D3
D2
D1
D0
Parity
Bit
Register Address
P
0
Parity
Bit
Bus
Park
- Read command sequence
Data frame from ANT Switch needs Half Speed function
①
SCLK
SDATA
SSC
SA3
SA2
SA1
SA0
Slave Address
SCLK
SDATA
0
1
1
A4
Read Command
A3
A2
A1
A0
P
0
Parity
Bit
Register Address
Bus
Park
①
0
Bus
Park
D7
D6
D5
D4
D3
D2
Data f rame f rom ANT Sw itch (Read Half Speed)
11
D1
D0
P
Bus
Park
CXM3653ER
Register Map
Table B REGISTER_0 for ANT Switch State (0x0000)
Items
Bit
Description
SA3 1
SA2 0
Slave
Address of Antenna Switch
Address SA1 1
SA0 0/1
Data
1
D6
D5
D4
D3
D2
D1
D0
P
0
0
0
0
0/1
0/1
0/1
0/1
REGISTER_0 Write : 1
Switch State
See the truth table
Trigger Supprt.
Initial value :
[D6:D0]
=000 0000
Parity bit for Frame
SA0 0/1
Read
Write
Register
Address
Parity Bit
Data Frame
Parity Bit
C0
Command Frame
Command Frame
Table A REGISTER_0 for ANT Switch State (0x0000)
Items
Bit
Description
SA3 1
SA2 0
Slave
Address of Antenna Switch
Address SA1 1
Data
Parity Bit
Data Frame
Command Frame
Table C REVISION_ID (0x0010)
Items
Bit
Description
SA3 1
Slave
SA2 0
Address of Antenna Switch
Address SA1 1
SA0 0/1
C2
0
Read
C1
1 Read Only
Write
C0
1
A4
1
A3
0
Register
A2
0 Register Address: 0x0010
Address
A1
0
A0
0
Parity Bit
P
0/1 Parity bit for Command Frame
D7
0
MAJOR REV
D6
0
D5
0
MINOR REV
D4
0
Data
D3
0
D2
0
MISC VARIANTS
D1
0
D0
0
Parity Bit
P
1 Parity bit for Data Frame
12
C2
0
C1
C0
A4
A3
A2
A1
A0
P
D7
D6
D5
D4
D3
D2
D1
D0
P
1
0/1
0
0
0
0
0
0/1
0
0
0
0
0
0/1
0/1
0/1
0/1
Write : 010
Read: 011
Register Address: 0x0000
Parity bit for Command Frame
Switch State
See the truth table
Trigger Supprt.
Parity bit for Data Frame
Initial value :
[D7:D0]
=0000 0000
CXM3653ER
Data Frame
Command Frame
Table D RFFE_STATUS
Items
Bit
SA3 1
Slave
SA2 0
Address SA1 1
SA0 0/1
C2
0
Read
C1
1
Write
C0 0/1
A4
1
A3
1
Register
A2
0
Address
A1
1
A0
0
Parity Bit
P
0/1
Data
Parity Bit
D7
0/1
D6
D5
D4
D3
D2
D1
D0
P
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
(0x001A)
Description
Address of Antenna Switch
Write : 010
Read: 011
Register Address: 0x001A
Parity bit for Command Frame
0: Normal operation
1: Software reset (reset of all configurable registers to default values,
except for USID、PM_TRIG、GSID)
Command sequence received with parity error – discard command.
Command length error
Address frame parity error = 1
Data frame with parity error
Read command to an invalid address
Write command to an invalid address
Read command with a Broadcast_ID or GROUP_ID
Parity bit for Data Frame
All Data bits become 0 aftter Read Command Sequence is sent.
Data Frame
Command Frame
Table E GROUP_ID
Items
SA3
Slave
SA2
Address SA1
SA0
C2
Read
C1
Write
C0
A4
A3
Register
A2
Address
A1
A0
Parity Bit
P
D7
D6
D5
Data
Parity Bit
D4
D3
D2
D1
D0
P
(0x001B)
Bit Description
1
0
Address of Antenna Switch
1
0/1
0
Write : 010
1
Read: 011
0/1
1
1
0 Register Address: 0x001B
1
1
0/1 Parity bit for Command Frame
0
0
0
-
0
0/1
0/1
Group slave ID
0/1
0/1
0/1 Parity bit for Data Frame
Initial value :
[D3:D0]
=0000
13
Initial value :
[D7:D0]
=0000 0000
CXM3653ER
Data Frame
Command Frame
Table F Register for Power Mode & Trigger Mode (0x001C)
Items
Description
Bit
SA3 1
Slave
SA2 0
Address of Antenna Switch
Address SA1 1
SA0 0/1
C2
0
Read
Write : 010
C1
1
Write
Read: 011
C0 0/1
A4
1
A3
1
Register
A2
1 Register Address: 0x001C
Address
A1
0
A0
0
Parity Bit
P
0/1 Parity bit for Command Frame
00: Normal operation (ACTIVE)
D7 0/1
01: Default settings (STARTUP)
10: Low power (LOW POWER)
D6 0/1
11: Reserved
D5 0/1 Trigger_Mask_[2:0]
Data
D4 0/1 111: valid
D3 0/1 other: Invalid
D2 0/1 Trigger_[2:0]
D1 0/1 000: Invalid
D0 0/1 other: valid
Parity Bit
P
0/1 Parity bit for Data Frame
Initial value :
[D7:D6]
=10
Initial value :
[D5:D3]
=000
Initial value :
[D5:D3]
=000
Data Frame
Command Frame
Table G Register for Product ID (0x001D)
Items
Description
Bit
SA3 1
Slave
SA2 0
Address of Antenna Switch
Address SA1 1
SA0 0/1
C2
0
Read
C1
1 Read Only
Write
C0
1
A4
1
A3
1
Register
A2
1 Register Address: 0x001D
Address
A1
0
A0
1
Parity Bit
P
0/1 Parity bit for Command Frame
D7
0
D6
0
D5
1
D4
0
Data
Product ID : 26h
D3
0
D2
1
D1
1
D0
0
Parity Bit
P
1 Parity bit for Data Frame
(Note) Product ID: TS1 sample is 00h.
Command Frame
Table I Register for
Items
SA3
Slave
SA2
Address SA1
SA0
C2
Read
C1
Write
C0
A4
A3
Register
A2
Address
A1
A0
Parity Bit
P
D7
D6
D5
D4
Data
D3
D2
D1
D0
Parity Bit
P
Data Frame
Data Frame
Command Frame
Table H Register for Manufacturer ID (0x001E)
Items
Description
Bit
SA3 1
Slave
SA2 0
Address of Antenna Switch
Address SA1 1
SA0 0/1
C2
0
Read
C1
1 Read Only
Write
C0
1
A4
1
A3
1
Register
A2
1 Register Address: 0x001E
Address
A1
1
A0
0
Parity Bit
P 0/1 Parity bit for Command Frame
D7
1
D6
0
D5
1
D4
1
Data
Manufacturer ID [7:0]:B0h (SONY ID)
D3
0
D2
0
D1
0
D0
0
Parity Bit
P
0 Parity bit for Data Frame
Manufacturer ID and USID (0x001F)
Description
Bit
1
0
Address of Antenna Switch
1
0/1
0
Write : 010
1
Read : 011
0/1
1
1
1 Register Address: 0x001F
1
1
0/1 Parity bit for Command Frame
0
SPARE
0
0
Manufacturer ID [9:8]:01h (SONY ID)
1
0/1
Initial value :[D3:D0]
0/1
Programmable USID
SSEL Level GND: USID 1011
0/1
SSEL Level VIO : USID 1010
0/1
0/1 Parity bit for Data Frame
For Programmable USID
The PRODUCT_ID and the MANUFACTURER_ID match, then a new USID is programmed.
14
CXM3653ER
Recommended Circuit
(Top View)
RF1
VDD
15
14
12
13
11
RF2
10
C2
VIO
16
9
17
8
SCLK
18
7
SSEL
1
SDATA
C1
C3
ANT
L1
2
3
4
5
6
RF4
*1 No DC blocking capacitors are required on all RF ports. (except external DC bias)
*2 The DC levels of all RF ports are GND.
*3 L1 (27nH) and C1(12pF) are recommended on Ant port for ESD protection.
*4 C2(100pF) and C3(0.1uF) are recommended .
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RF3
CXM3653ER
Recommended Land Pattern
16
CXM3653ER
Package Outline
(Unit: mm)
17
CXM3653ER
Marking
HK
18
CXM3653ER
Tape and Reel Size
CXM3653ER-T9
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CXM3653ER
Note
Sony reserves the right to change products and specifications without prior notice.
This information does not convey any license by any implication or otherwise under any patents or other right.
Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume
responsibility for any problems arising out of the use of these circuits.
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