Aeroflex Colorado Springs Application Note AN-LOG-002-001 Calculating Power Dissipation for the 16-Bit Transceiver Family Table 1: Cross Reference of Applicable Products Manufacturer Part SMD # Number MultiPurpose Transceiver with UT54ACS164245S/SE 5962-98580 Cold Spare I/O Product Name: MultiPurpose Transceiver with Cold/Warm Spare I/O MultiPurpose Registered Transceiver with Cold/Warm Spare I/O MultiPurpose 3-Volt Transceiver with Cold/Warm Spare I/O UT54ACS164245SEI 5962-98580 Device Type 01, 02, 03, 04, 05 06, 07 Internal PIC UT54ACS164646S 5962-06234 01 KE01 UT54ACS162245SLV 5962-02543 01 WA04,WA05 JM01,JM03, JM04 JM06 1.0 Overview The Aeroflex 16-bit Logic family contains products such as the UT54ACS164245S/SE, UT54ACS164245SEI, UT54ACS164646S, and the UT54ACS162245SLV. These products perform functions such as: asynchronous two-way communication, Schmitt input buffering, voltage translation, multiplexed real-time and stored data, as well as cold and warm sparing. This application note walks the designer through the calculations needed to determine power dissipation capacitance (CPD) and power dissipation (PD) for the 16-bit Logic Family with user specific capacitive loads (CL). 2.0 Technical Figures and Data Accurate power calculations are necessary to determine system power supply and thermal management requirements. The two primary components that determine the power consumption in a CMOS circuit are static and dynamic power. Static power is the power dissipated under DC conditions. Dynamic power consumption occurs when the device is switching capacitive loads. Power consumption can be decreased by lowering supply voltage, reducing the capacitive load that the device has to drive, or lowering the devices operating frequency. Usually none of these reductions can be made without compromising system performance. It then becomes very important to be able to estimate the power requirements of the device. From the device SMDs, power dissipation per switching output is offered as Ptota1 = X mW/MHz with a tester load CL = Y pF. SMD values enable the user to determine worst case power dissipation for the system. A power dissipation analysis can also determine the maximum reliable operating frequency of the device. Creation Date: 03/01/11 Page 1 of 24 Modification Date: 2.1 Characterization Data UT54ACS164245SEI The following plots show active current, or AIDD, measurements versus frequency, over temperature and are used as input current for calculating power dissipation and power dissipation capacitance(CPD). The AIDD values are from maximum measurements taken during characterization of numerous devices under the following conditions. Temperature: TC = 125°C, 25°C,-55°C VDD1 = VDD2 = 3.0V VDD1 = VDD2 = 3.6V VDD1 = VDD2 = 5.5V VDD1 =5.5V VDD2 = 3.6V Voltage: Frequency: f =10MHz, 25MHz, 50MHz UT54ACS164245SEI AIDD vs. Frequency TC =125°C CL=40pF VDD1=VDD2=3.0V VDD1=VDD2=3.6V VDD1=VDD2=5.5V AIDD (mA) VDD1=5.5V VDD2=3.6V 180 160 140 120 100 80 60 40 20 0 10 15 20 25 30 35 Frequency (MHz) 40 45 50 Figure 1. AIDD Values for 125°C with all 16 outputs switching Creation Date: 03/01/11 Page 2 of 24 Modification Date: VDD1=VDD2=3.0V UT54ACS164245SEI AIDD vs. Frequency TC =25°C CL=40pF VDD1=VDD2=3.6V VDD1=VDD2=5.5V AIDD (mA) VDD1=5.5V VDD2=3.6V 180 160 140 120 100 80 60 40 20 0 10 15 20 25 30 35 40 45 50 Frequency (MHz) Figure 2. AIDD Values for 25°C with all 16 outputs switching VDD1=VDD2=3.0V UT54ACS164245SEI AIDD vs. Frequency TC =-55°C CL=40pF VDD1=VDD2=3.6V VDD1=VDD2=5.5V VDD1=5.5V VDD2=3.6V 180 AIDD (mA) 160 140 120 100 80 60 40 20 0 10 15 20 25 30 35 40 45 50 Frequency (MHz) Figure 3 AIDD Values for -55°C with all 16 outputs switching Creation Date: 03/01/11 Page 3 of 24 Modification Date: Using the AIDD graphs above (figures 1-3), or the data in tables 2 through 5 below, an estimate of the power supply current can be calculated by taking the slope of the line between two adjacent frequencies at a given temperature and multiplying by the designer’s operating frequency. The values in the “Slope (mA/MHz)” column are the values for the power supply input current that will be used in determining the power dissipation and dynamic current consumption later in this application note Power dissipation capacitance or (CPD) for the 16-Bit Logic Transceivers is calculated using equation 1 as follows. Since the outputs switch rail to rail VDD = 3.3V or 5.0V, the capacitive load per switching output added by the automated tester (CLT) must be accounted for. Calculations for CPD are found in sections 3.0 and 4.0 of this application note. Table 2. AIDD over frequency and temperature with VDD1 = VDD2 = 3.0V AIDD is listed for all 16 outputs switching, CPD and CLT are listed per switching output. TC (°C) VDD1=VDD2=3.0V CLT=40pF CPD=15.0pF Creation Date: 03/01/11 25 25 25 25 Frequency (MHz) SIDD 0 10 25 50 -55 -55 -55 -55 SIDD 125 125 125 125 SIDD AIDD (mA) 12.62 14.41 36.08 80.71 Slope (mA/MHz) 1.45 1.79 0 10 25 50 12.71 14.50 36.45 81.29 1.46 1.79 0 10 25 50 13.21 14.89 37.11 79.07 1.48 1.68 Page 4 of 24 Modification Date: Table 3. AIDD over frequency and temperature with VDD1 = VDD2 = 3.6V AIDD is listed for all 16 outputs switching, CPD and CLT are listed per switching output. TC (°C) 25 25 25 25 VDD1=VDD2=3.6V CLT=40pF CPD=15.0pF Frequency (MHz) SIDD 0 10 25 50 -55 -55 -55 -55 SIDD 125 125 125 125 SIDD AIDD (mA) 15.33 17.50 44.26 98.55 Slope (mA/MHz) 1.78 2.17 0 10 25 50 15.59 17.71 45.07 98.15 1.82 2.12 0 10 25 50 15.87 17.99 45.01 97.99 1.80 2.12 Table 4. AIDD over frequency and temperature with VDD1 = 5.5V VDD2 = 3.6V AIDD is listed for all 16 outputs switching, CPD and CLT are listed per switching output. TC (°C) VDD1=5.5V VDD2=3.6V 25 25 25 25 Frequency (MHz) SIDD 0 10 25 50 AIDD (mA) 20.49 23.29 59.12 129.12 Slope (mA/MHz) 2.39 2.80 CLT=40pF CPD=15.0pF Creation Date: 03/01/11 -55 -55 -55 -55 SIDD 125 125 125 125 SIDD 0 10 25 50 21.04 23.71 60.97 127.58 2.48 2.66 0 10 25 50 20.92 23.71 58.95 128.72 2.35 2.79 Page 5 of 24 Modification Date: Table 5. AIDD over frequency and temperature with VDD1 = VDD2 = 5.5V AIDD is listed for all 16 outputs switching, CPD and CLT are listed per switching output. TC (°C) VDD1=VDD2=5.5V CLT=40pF CPD=15.0pF Creation Date: 03/01/11 25 25 25 25 Frequency (MHz) SIDD 0 10 25 50 -55 -55 -55 -55 SIDD 125 125 125 125 SIDD AIDD (mA) 25.18 28.43 72.74 154.03 Slope (mA/MHz) 2.95 3.25 0 10 25 50 26.06 29.08 75.42 150.94 3.09 3.02 0 10 25 50 25.36 28.74 71.78 156.26 2.87 3.38 Page 6 of 24 Modification Date: 2.2 Characterization Data UT54ACS164245S/SE Temperature: TC = 125°C, 25°C,-55°C Voltage: VDD1 = VDD2 = 3.0V VDD1 = VDD2 = 3.6V VDD1 = VDD2 = 5.5V VDD1 =5.5V VDD2 = 3.6V Frequency: f =10MHz, 25MHz, 50MHz VDD1=VDD2=3.0V UT54ACS164245S AIDD vs. Frequency TC =125°C CL=40pF VDD1=VDD2=3.6V VDD1=VDD2=5.5V VDD1=5.5V VDD2=3.6V 160 140 AIDD (mA) 120 100 80 60 40 20 0 10 15 20 25 30 35 Frequency (MHz) 40 45 50 Figure 4. AIDD Values for 125°C with all 16 outputs switching Creation Date: 03/01/11 Page 7 of 24 Modification Date: VDD1=VDD2=3.0V UT54ACS164245S AIDD vs. Frequency TC =25°C CL=40pF VDD1=VDD2=3.6V VDD1=VDD2=5.5V VDD1=5.5V VDD2=3.6V 160 140 AIDD (mA) 120 100 80 60 40 20 0 10 15 20 25 30 35 Frequency (MHz) 40 45 50 Figure 5. AIDD Values for 25°C with all 16 outputs switching VDD1=VDD2=3.0V UT54ACS164245S AIDD vs. Frequency TC =-55°C CL=40pF VDD1=VDD2=3.6V VDD1=VDD2=5.5V VDD1=5.5V VDD2=3.6V 160 140 AIDD (mA) 120 100 80 60 40 20 0 10 15 20 25 30 35 Frequency (MHz) 40 45 50 Figure 6. AIDD Values for -55°C with all 16 outputs switching Creation Date: 03/01/11 Page 8 of 24 Modification Date: Table 5. AIDD over frequency and temperature with VDD1 = VDD2 = 3.0V AIDD is listed for all 16 outputs switching, CPD and CLT are listed per switching output. TC (°C) VDD1=VDD2=3.0V CLT=40pF CPD=15.0pF 25 25 25 25 Frequency (MHz) SIDD 0 10 25 50 -55 -55 -55 -55 SIDD 125 125 125 125 SIDD AIDD (mA) 12.83 14.24 34.92 70.29 Slope (mA/MHz) 1.38 1.41 0 10 25 50 10.18 11.36 27.88 57.48 1.10 1.18 0 10 25 50 13.19 14.49 35.63 67.95 1.41 1.29 Table 6. AIDD over frequency and temperature with VDD1 = VDD2 = 3.6V AIDD is listed for all 16 outputs switching, CPD and CLT are listed per switching output. TC (°C) VDD1=VDD2=3.6V CLT=40pF CPD=15.0pF Creation Date: 03/01/11 25 25 25 25 Frequency (MHz) SIDD 0 10 25 50 25 -55 -55 -55 SIDD 125 125 125 125 SIDD AIDD (mA) 15.52 17.30 42.48 86.96 Slope (mA/MHz) 1.67 1.77 0 10 25 50 15.46 17.24 42.41 86.86 1.67 1.77 0 10 25 50 15.81 17.53 43.08 86.11 1.70 1.72 Page 9 of 24 Modification Date: Table 7. AIDD over frequency and temperature with VDD1 = 5.5V VDD2 = 3.6V AIDD is listed for all 16 outputs switching, CPD and CLT are listed per switching output. TC (°C) VDD1=5.5V VDD2=3.6V 25 25 25 25 Frequency (MHz) SIDD 0 10 25 50 AIDD (mA) 19.38 21.56 52.96 107.38 Slope (mA/MHz) 2.09 2.17 CLT=40pF CPD=15.0pF -55 -55 -55 -55 SIDD 25 125 125 125 SIDD 0 10 25 50 20.32 22.55 55.52 111.36 2.19 2.23 0 10 25 50 20.25 22.54 55.31 112.58 2.18 2.29 Table 8. AIDD over frequency and temperature with VDD1 = VDD2 = 3.0V AIDD is listed for all 16 outputs switching, CPD and CLT are listed per switching output. TC (°C) VDD1=VDD2=5.5V CLT=40pF CPD=15.0pF Creation Date: 03/01/11 25 25 25 25 Frequency (MHz) SIDD 0 10 25 50 -55 -55 -55 -55 SIDD 25 125 125 125 SIDD AIDD (mA) 24.72 27.49 67.79 136.92 Slope (mA/MHz) 2.68 2.76 0 10 25 50 25.12 27.74 68.78 134.33 2.73 2.62 0 10 25 50 24.65 27.52 67.84 139.5 2.68 2.86 Page 10 of 24 Modification Date: 2.1 Characterization Data UT54ACS164646S Temperature: TC = 125°C, 25°C,-55°C Voltage: VDD1 = VDD2 = 3.0V VDD1 = VDD2 = 3.6V VDD1 = VDD2 = 5.5V VDD1 =5.5V VDD2 = 3.6V f =10MHz, 25MHz, 50MHz Frequency: VDD1=VDD2=3.0V UT54ACS164646S AIDD vs. Frequency TC =125°C CL=40pF VDD1=VDD2=3.6V VDD1=VDD2=5.5V VDD1=5.5V VDD2=3.6V 200.000 180.000 160.000 AIDD (mA) 140.000 120.000 100.000 80.000 60.000 40.000 20.000 0.000 10 15 20 25 30 35 Frequency (MHz) 40 45 50 Figure 7. AIDD Values for 125°C with all 16 outputs switching Creation Date: 03/01/11 Page 11 of 24 Modification Date: VDD1=VDD2=3.0V UT54ACS164646S AIDD vs. Frequency TC =25°C CL=40pF VDD1=VDD2=3.6V VDD1=VDD2=5.5V VDD1=5.5V VDD2=3.6V 200.000 180.000 160.000 AIDD (mA) 140.000 120.000 100.000 80.000 60.000 40.000 20.000 0.000 10 15 20 25 30 35 Frequency (MHz) 40 45 50 Figure 8. AIDD Values for 25°C with all 16 outputs switching VDD1=VDD2=3.0V UT54ACS164646S AIDD vs. Frequency TC =-55°C CL=40pF VDD1=VDD2=3.6V VDD1=VDD2=5.5V VDD1=5.5V VDD2=3.6V 200.000 180.000 160.000 AIDD (mA) 140.000 120.000 100.000 80.000 60.000 40.000 20.000 0.000 10 15 20 25 30 35 Frequency (MHz) 40 45 50 Figure 9. AIDD Values for -55°C with all 16 outputs switching Creation Date: 03/01/11 Page 12 of 24 Modification Date: Table 9. AIDD over frequency and temperature with VDD1 = VDD2 = 3.0V AIDD is listed for all 16 outputs switching, CPD and CLT are listed per switching output. TC (°C) 25 25 25 25 VDD1=VDD2=3.0V CLT=40pF CPD=15.0pF Frequency (MHz) SIDD 0 10 25 50 -55 -55 -55 -55 SIDD 125 125 125 125 SIDD AIDD (mA) 16.29 18.34 45.76 97.10 Slope (mA/MHz) 1.82 2.05 0 10 25 50 16.07 18.13 45.86 97.21 1.84 2.05 0 10 25 50 16.82 18.75 46.54 94.73 1.85 1.92 Table 10. AIDD over frequency and temperature with VDD1 = VDD2 = 3.6V AIDD is listed for all 16 outputs switching, CPD and CLT are listed per switching output. TC (°C) VDD1=VDD2=3.6V CLT=40pF CPD=15.0pF Creation Date: 03/01/11 25 25 25 25 Frequency (MHz) SIDD 0 10 25 50 -55 -55 -55 -55 SIDD 125 125 125 125 SIDD AIDD (mA) 19.80 22.29 55.86 118.14 Slope (mA/MHz) 2.23 2.49 0 10 25 50 19.62 22.01 55.95 115.62 2.26 2.38 0 10 25 50 20.26 22.73 56.50 118.41 2.25 2.47 Page 13 of 24 Modification Date: Table 11. AIDD over frequency and temperature with VDD1 = 5.5V VDD2 = 3.6V AIDD is listed for all 16 outputs switching, CPD and CLT are listed per switching output. TC (°C) VDD1=5.5V VDD2=3.6V 25 25 25 25 Frequency (MHz) SIDD 0 10 25 50 AIDD (mA) 29.54 33.15 83.88 174.21 Slope (mA/MHz) 3.38 3.61 CLT=40pF CPD=15.0pF -55 -55 -55 -55 SIDD 125 125 125 125 SIDD 0 10 25 50 27.83 30.92 78.69 155.83 3.18 3.08 0 10 25 50 32.60 36.77 91.75 195.92 3.66 4.16 Table 12. AIDD over frequency and temperature with VDD1 = VDD2 = 5.5V AIDD is listed for all 16 outputs switching, CPD and CLT are listed per switching output. TC (°C) VDD1=VDD2=5.5V CLT=40pF CPD=15.0pF Creation Date: 03/01/11 25 25 25 25 Frequency (MHz) SIDD 0 10 25 50 -55 -55 -55 -55 SIDD 125 125 125 125 SIDD AIDD (mA) 31.80 35.59 90.03 184.77 Slope (mA/MHz) 3.62 3.79 0 10 25 50 31.74 34.97 88.15 168.99 3.54 3.23 0 10 25 50 31.85 35.72 88.98 185.59 3.55 3.86 Page 14 of 24 Modification Date: 2.1 Characterization Data UT54ACS162245SLV Temperature: TC = 125°C, 25°C,-55°C Voltage: VDD1 = VDD2 = 3.0V VDD1 = VDD2 = 3.6V VDD1 = VDD2 = 2.3V VDD1 =3.6V VDD2 = 2.7V f =10MHz, 25MHz, 50MHz Frequency: VDD=3.0V UT54ACS162245SLV AIDD vs. Frequency TC =125°C CL=40pF VDD=3.6V VDD=2.3V VDD1=3.6V VDD2=2.7V 100.000 90.000 80.000 AIDD (mA) 70.000 60.000 50.000 40.000 30.000 20.000 10.000 0.000 10 15 20 25 30 Frequency (MHz) 35 40 45 50 Figure 10. AIDD Values for 125°C with all 16 outputs switching Creation Date: 03/01/11 Page 15 of 24 Modification Date: VDD=3.0V UT54ACS162245SLV AIDD vs. Frequency TC =25°C CL=40pF VDD=3.6V VDD=2.3V VDD1=3.6V VDD2=2.7V 100.000 90.000 80.000 AIDD (mA) 70.000 60.000 50.000 40.000 30.000 20.000 10.000 0.000 10 15 20 25 30 Frequency (MHz) 35 40 45 50 Figure 11. AIDD Values for 25°C with all 16 outputs switching UT54ACS162245SLV AIDD vs. Frequency TC =-55°C CL=40pF VDD=3.0V VDD=3.6V VDD=2.3V VDD1=3.6V VDD2=2.7V 100.000 90.000 80.000 AIDD (mA) 70.000 60.000 50.000 40.000 30.000 20.000 10.000 0.000 10 15 20 25 30 35 Frequency (MHz) 40 45 50 Figure 12. AIDD Values for -55°C with all 16 outputs switching Creation Date: 03/01/11 Page 16 of 24 Modification Date: Table 13. AIDD over frequency and temperature with VDD1 = VDD2 = 3.0V AIDD is listed for all 16 outputs switching, CPD and CLT are listed per switching output. TC (°C) 25 25 25 25 VDD1=VDD2=3.0V CLT=40pF CPD=15.0pF Frequency (MHz) SIDD 0 10 25 50 -55 -55 -55 -55 SIDD 125 125 125 125 SIDD AIDD (mA) 14.14 15.61 38.34 74.97 Slope (mA/MHz) 1.51 1.46 0 10 25 50 14.16 15.53 38.01 72.34 1.49 1.37 0 10 25 50 14.40 15.94 38.94 77.29 1.53 1.53 Table 14. AIDD over frequency and temperature with VDD1 = VDD2 = 3.6V AIDD is listed for all 16 outputs switching, CPD and CLT are listed per switching output. TC (°C) VDD1=VDD2=3.6V CLT=40pF CPD=15.0pF Creation Date: 03/01/11 25 25 25 25 Frequency (MHz) SIDD 0 10 25 50 -55 -55 -55 -55 SIDD 125 125 125 125 SIDD AIDD (mA) 17.82 19.54 47.72 90.95 Slope (mA/MHz) 1.87 1.72 0 10 25 50 17.64 19.26 46.98 87.46 1.84 1.61 0 10 25 50 18.15 19.99 48.52 94.64 1.90 1.84 Page 17 of 24 Modification Date: Table 15. AIDD over frequency and temperature with VDD1 = 3.6 VDD2 = 2.7V AIDD is listed for all 16 outputs switching, CPD and CLT are listed per switching output. TC (°C) VDD1=3.6V VDD2=2.7V 25 25 25 25 Frequency (MHz) SIDD 0 10 25 50 AIDD (mA) 14.97 16.56 40.48 80.20 Slope (mA/MHz) 1.59 1.58 CLT=40pF CPD=15.0pF -55 -55 -55 -55 SIDD 125 125 125 125 SIDD 0 10 25 50 14.89 16.42 40.08 78.23 1.57 1.52 0 10 25 50 15.34 17.00 41.17 82.82 1.61 1.66 Table 16. AIDD over frequency and temperature with VDD1 = VDD2 = 2.3V AIDD is listed for all 16 outputs switching, CPD and CLT are listed per switching output. Frequency (MHz) SIDD 0 10 25 50 AIDD (mA) 10.45 11.58 28.49 56.86 -55 SIDD 0 -55 10 -55 25 -55 50 10.34 11.45 28.21 55.43 1.11 1.08 125 SIDD 0 125 10 125 25 125 50 10.53 11.76 28.82 59.38 1.13 1.22 TC (°C) VDD1=VDD2=2.3V CLT=40pF CPD=15.0pF Creation Date: 03/01/11 25 25 25 25 Page 18 of 24 Slope (mA/MHz) 1.12 1.13 Modification Date: 3.0 Calculating of Power with Variable Load Capacitance The following equations and examples are provided as a guide for estimating power dissipation, power dissipation capacitance, and dynamic current consumption using various capacitive loads. Definition of Terms: VDD11 VDD21 VOL VOL(actual) VOH VOH(actual) Port B Power Supply Voltage (V) Port A Power Supply Voltage (V) Low-level output voltage (V) Load Dependant Low-level output voltage (V) High-level output voltage (V) Load Dependant High-level output voltage (V) AIDD AIDD(slope) AIDD(frequency) SIDD IOL IOH ISD Active Supply Current with all 16 Outputs Switching (mA) Slope of AIDD (mA/MHz) Active current at given frequency (mA) Standby Current Device Enabled f=0MHz (mA) Low level output current (mA) High level output current (mA) Dynamic Current Consumption (A) PDCL PDCH Percent Duty Cycle Driving Logic Low (%) Percent Duty Cycle Driving Logic High (%) CPD CL CLT Power Dissipation Capacitance (F) Users Load Capacitance (F) Capacitive per switching output Tester Load (F) f Input Frequency (Hz) PSWO PST PDYN PRLOAD PTOTAL Power per Switching Output (W/MHz per output) Static Power Dissipation (W) Dynamic Power Dissipation (W) Resistive Load Output Power (W) Total Power Dissipation (W) NO N16 Number of switching outputs Number of outputs on the 16-bit Device Notes: 1. The 16-bit transceiver devices are running at different supply voltages use the supply voltage that corresponds to the bidirect pins configured as outputs when using the equations provided in section 3.0. Meaning if a calculation is being performed on the UT54ACS162245SLV device and VDD1=3.6V, VDD2 = 2.7V, and DIR1 = DIR2 = HIGH (meaning the device is in A data to B Bus), VDD1 = 3.6V would need to be used as the VDD terms in the section 3.0 equations Another example if a calculation is being performed on the UT54ACS164245SEI device and VDD1=5.5V, VDD2 = 3.6V, and DIR1 = DIR2 = LOW (meaning the device is in B data to A Bus), VDD2 = 3.6V would need to be used as the VDD terms in the section 3.0 equations Creation Date: 03/01/11 Page 19 of 24 Modification Date: Two methods are offered to calculate Power/MHz. The first method simply employs Joule’s law (P=IV), the power supply current, and voltage measured under a specific test condition. Method 1 offers a validation to the values that are then calculated using method 2. Method 2 contains terms like CPD, CL, f, and VDD, all of which can be varied by the designer in predicting power for a specific application. Power per Switching Output (PSWO): PSWO VDD * AIDD( frequency) N16 (1) Static Device Power (PST): PST SIDD * VDD (2) Dynamic Device Power per Switching Output (PDYN): PDYN C PD VDD * f C L VOH (actual ) VOL (actual ) * f 2 2 Resistive Output Load Power (PLOAD): PLOAD PDCL * VOL * I OL PDCH * VDD VOH * I OH (3) (4) Total Device Power (PTOTAL): PTOTAL PST N O PDYN PLOAD (5) Active Current at frequency (AIDD(frequency)): AIDD( frequency) f f @ known AIDD * AIDD( slope) AIDD @ known f (6) CPD Average AIDD( slope) N16*CLT VDD Creation Date: 03/01/11 Page 20 of 24 (7) Modification Date: 4.0 Example Calculations The following sections walk the designer through example calculations using data and equations presented in sections 2.0 and 3.0. 4.1 Example 1 The CPD value in Table 2 calculates using equation (7). CPD Average AIDD( slope) N16*CLT VDD Where: VDD AIDD(slope) CPD CLT N16 CPD total Maximum Users Power Supply Voltage (V) Slope of AIDD (mA/MHz) Power Dissipation Capacitance (F) Capacitive per switching output Tester Load (F) Number of outputs on the 16-bit Device Average AIDD( slope) N16 * CLT VDD Average1.44,1.785,1.463,1.793,1.481.1.679 16 * 40 pF 103.9 pF 3.0 Total power dissipation capacitance is not useful for further calculations. For meaningful calculations one must compute power dissipation capacitance per output. CPD per switching output Creation Date: 03/01/11 CPD total 103.9 pF 6.49 pF Per Switching Output 16 N16 Page 21 of 24 Modification Date: 4.2 Example 2 The UT54ACS164245SEI analysis assumes the following: utilization of 8 outputs switching at 20MHz with 80pF capacitive loads, VDD1=VDD2=3.0V, 512.5Ω pull up to VDD on the output, at 25°C. A bias resistor is present on the output to pull up the outputs are in Z state. In practice, the bias resistor will be defined by the system designer. Referencing tables 1-4, power supply current is found by estimating the slope of the line at various temperatures. The values in the “Slope (mA/MHz)” column are the values for the power supply input current that will be used in determining the power dissipation and dynamic current consumption. VDD1 VDD 2 VDD 3.0V TC 25C CLT 40 pF / output CPD 6.49 pF CL 80 pF (users load ) AIDD( slope) 1.45mA / MHz (Table 2) SIDD 12.62mA N O 8 outputs f 20MHz PDCL 0.5 PDCH 0.5 VOH VDD 0.2 3.0V 0.2V 2.8V at I OH 100A VOH (actual ) 3.0V Assume no bias resistors output swinging rail to rail VOL 0.2V at I OL 100 A VOL (actual ) VDD 512.5 * I OL 3.0V 2.5V 0.44V at I OL 5.0mA 4.2.1 Method 1: For these conditions power per switching output (PSWO) calculates using equations (1) and (6): To calculate the active current at 20MHz using Joule’s law (P=IV): See Table 2 TC=25°C I AIDD( slope) * f 1.45mA / MHz * 20MHz 1.81mA / output N16 16 PJoule ' s N O I * V SIDD * V 8outputs * 1.81mA * 3.0V 12.62 * 3.0V 81.36mW for 8 outputs switching Creation Date: 03/01/11 Page 22 of 24 Modification Date: AIDD( frequency) f f @ known AIDD * AIDD( slope) AIDD @ known f 20MHz 10MHz *1.45mA / MHz 14.41mA 14.45 14.41 28.91mA PSWO VDD * AIDD( frequency) 3.0V * 28.91mA 5.42mW / per output N16 16 PTOTAL (method1) SIDD * VDD PSWO * N O 12.62mA * 3.0V 5.42mW / output * 8 outputs 81.23mW 4.2.2 Method 2: Using equation (2) for calculating Static Device Power (PST): PST SIDD * VDD 12.62mA * 3.0V 37.86mW Dynamic Device Power per Switching Output (PDYN): PDYN CPD VDD * f CL VOH (actual ) VOL (actual ) * f 6.49 pF 3.0V 2 2 2 * 20MHz 80 pF 3.0V 0.44V * 20MHz 11.65mW 2 Resistive Output Load Power (PLOAD): PLOAD PDCL * VOL * I OL PDCH * VDD VOH * I OH 0.5 * 0.5V * 8.0mA 0.5 * 3.0V 3.0V * 100A 2.0mW 0mW 2.0mW Total Device Power (PTOTAL) for 8 switching outputs: PTOTAL PST N O PDYN PLOAD 37.86mW 811.65mW 2.0mW 147.06mW 5.0 Summary and Conclusion This application note empowers the designer to more accurately determine the power dissipation of the 16-bit logic products as implemented in the user’s application. The calculations described in the above sections employ application specific variables such as load capacitance, frequency, DC loading contributes to overall power dissipation. Using accurate power dissipation calculations improved power supply selection and design of proper thermal management schemes is achieved. Creation Date: 03/01/11 Page 23 of 24 Modification Date: SMD Ptotal Reference Aeroflex Part Number SMD Number UT54ACS164245S 5962-98580 Power Dissipation Ptotal1 Test Conditions A Port = 3.3V VDD1 = 4.5V and 5.5V VDD2 = 3.13V and 3.6V -----------------------------------B Port = 3.3V VDD1 = 3.13V and 3.6V VDD2 = 3.13V and 3.6 V Ptotal2 B Port = 5.0V VDD1 = 4.5V and 5.5V VDD2 = 3.13V and 3.6V UT54ACS164245SEI 5962-98580 5962-98580 UT54ACS164646S 5962-06234 UT54ACS162245SLV 5962-02543 Creation Date: 03/01/11 Limits (mW/MHz) 40 1.5 40 2.0 40 2.0 40 1.5 Ptotal1 Port B=5.0V VDD1 = 4.5V and 5.5V VDD2 = 4.5V and 5.5V A Port = 3.3V VDD1 = 4.5V and 5.5V VDD2 = 3.0V and 3.6V -----------------------------------B Port = 3.3V VDD1 = 3.0V and 3.6V VDD2 = 3.0V and 3.6V Ptotal2 Port B = 5.0V VDD1 = 4.5V and 5.5V VDD2 = 3.0V and 3.6V 40 2.0 Ptotal3 Port B=5.5V VDD1 = 4.5V and 5.5V VDD2 = 4.5V and 5.5V 40 2.0 Ptotal1 A Port = 3.3V VDD1 = 4.5V and 5.5V VDD2 = 3.0V and 3.6V -----------------------------------B Port = 3.3V VDD1 = 3.0V and 3.6V VDD2 = 3.0V and 3.6V 40 1.5 Ptotal2 Port B = 5.0V VDD1 = 4.5V and 5.5V VDD2 = 3.0V and 3.6V 40 2.0 Ptotal3 Ptotal1 Ptotal2 Ptotal1 Ptotal2 Port B=5.5V VDD1 = 4.5V and 5.5V VDD2 = 4.5V and 5.5V VDDA = VDDB = 4.5V and 5.5V VDDA = VDDB = 3.0V and 3.6V VDD = 3.0V and 3.6V VDD = 2.3V and 2.7V 40 20 20 40 40 2.0 2.0 1.5 6.2 3.0 Ptotal3 UT54ACS164245SE CL (pF) Page 24 of 24 Modification Date: