UT54ACS164245SEI Transceiver with Cold/Warm Spare I/O (4/16)

UT54ACS164245SEI
Schmitt CMOS 16-bit Bidirectional MultiPurpose Transceiver
Datasheet
April 2016
www.aeroflex.com/16BitLogic
The direction and output enable controls operate these devices
as either two independent 8-bit transceivers or one 16-bit transceiver.
FEATURES
 Flexible voltage operation
- 5V bus to 3.3V bus; 5V bus to 5V bus
- 3.3V bus to 5V bus; 3.3V bus to 3.3V bus
 Cold sparing
- 1M minimum input impedance power-off
 Warm sparing
- Guaranteed output tri-state while one power supply is "off"
and the other is "on"
- 1Mminimum input impedance power-off
 m CRH CMOS Technology
 Operational Environment:
- Total dose: 100 krads(Si)
- Single Event Latchup immune
 High speed, low power consumption
 Schmitt trigger inputs to filter noisy signals
 Available QML Q or V processes
 Standard Microcircuit Drawing 5962-98580
- Device Types 06 and 07
 Package:
- 48-lead flatpack, 25 mil pitch (.390 x .640), wgt 1.4 grams
LOGIC SYMBOL
OE1 (48)
G1
OE2 (25)
(1)
DIR1
G2
1A1
1A2
(3)
(43)
1A4
(41)
1A5
(40)
1A6
(38)
1A7
(37)
1A8
(36)
2A1
(6)
2A3
(35)
(33)
(32)
2A4
(30)
2A5
(29)
2A6
(27)
2A7
(26)
2A8
1
12
(5)
2A2
The 16-bit wide UT54ACS164245SEI MultiPurpose transceiver is built using Aeroflex’s CRH technology. This high speed,
low power UT54ACS164245SEI transceiver is designed to perform multiple functions including: asynchronous two-way
communication, schmitt input buffering, voltage translation,
cold and warm sparing. With either or both VDD1 and VDD2 are
equal to zero volts, the UT54ACS164245SEI outputs and inputs
present a minimum impedance of 1M making it ideal for "cold
spare" applications. Balanced outputs and low "on" output impedance make the UT54ACS164245SEI well suited for driving
high capacitance loads and low impedance backplanes. The
UT54ACS164245SEI enables system designers to interface 3.3
volt CMOS compatible components with 5 volt CMOS components. For voltage translation, the A port interfaces with the 3.3
volt bus; the B port interfaces with the 5 volt bus. The direction
control (DIRx) controls the direction of data flow. The output
enable (OEx) overrides the direction control and disables both
ports. These signals can be driven from either port A or B.
DIR2
(2)
11
(46)
(24)
(44)
1A3
DESCRIPTION
(47)
2EN1 (BA)
2EN2 (AB)
1EN1 (BA)
1EN2 (AB)
(8)
1B1
1B2
1B3
1B4
1B5
(9)
1B6
(11)
1B7
(12)
1B8
(13)
2B1
21
22
(14)
2B2
(16)
2B3
(17)
2B4
(19)
2B5
(20)
2B6
(22)
2B7
(23)
2B8
PIN DESCRIPTION
Pin Names
PINOUTS
Description
OEx
Output Enable Input (Active Low)
DIRx
Direction Control Inputs
xAx
Side A Inputs or 3-State Outputs (3.3V Port)
xBx
Side B Inputs or 3-State Outputs (5V Port)
48-Lead Flatpack
Top View
FUNCTION TABLE
ENABLE
OEx
DIRECTION
DIRx
OPERATION
L
L
B Data To A Bus
L
H
A Data To B Bus
H
X
Isolation
2
DIR1
1
48
OE1
1B1
2
47
1A1
1B2
3
46
VSS
1B3
4
5
45
44
1A2
VSS
1B4
6
43
1A4
VDD1
7
42
VDD2
1B5
1B6
VSS
8
9
10
41
40
39
1A5
1A6
VSS
1B7
11
38
1A7
1B8
12
37
1A8
2B1
13
36
2A1
2B2
VSS
14
15
35
34
2A2
VSS
2B3
16
33
2A3
2B4
17
32
2A4
VDD1
2B5
2B6
VSS
18
19
20
21
31
30
29
28
VDD2
2A5
2A6
VSS
2B7
2B8
DIR2
22
23
24
27
26
25
2A7
2A8
OE2
1A3
POWER APPLICATION GUIDELINES
For proper operation, connect power to all VDD pins and ground
all VSS pins (i.e., no floating VDD or VSS input pins). By virtue
of the UT54ACS164245SEI warm spare feature, power supplies
VDD1 and VDD2 may be applied to the device in any order. To
ensure the device is in cold spare mode, both supplies, VDD1 and
VDD2 must be equal to VSS +/- 0.3V. Warm spare operation is
in effect when one power supply is >1V and the other power
supply is equal to VSS +/- 0.3V. If VDD1 has a power on ramp
longer than 1 second, then VDD2 should be powered on first to
ensure proper control of DIRx and OEx. During normal operation of the part, after power-up, ensure VDD1>VDD2.
IO GUIDELINES
All inputs are 5 volt tolerant. When VDD2 is at 3.3 volts, either
3.3 or 5 volt CMOS logic levels can be applied to all control inputs. It is recommended that all unused inputs be tied to VSS
through a 1K to 10K resistor.
It's good design practice to tie the unused input to VSS via a resistor to reduce noise susceptibility. The resistor protects the input pin by limiting the current from high going variations in
VSS.
The number of inputs that can be tied to the resistor pull-down
can vary. It is up to the system designer to choose how many
inputs are tied together by figuring out the max load the part can
drivewhile still meeting system performance specs. Input signal
transitions should be driven to the device with a rise
and fall time that is <100ms.
WARM SPARE
By definition, warm sparing occurs when half of the chip receives its normal VDD supply value while the VDD supplying the
other half of the chip is set to 0.0V. When the chip is "warm
spared", the side that has VDD set to a normal operational value
is "actively" tri-stated because the chip’s internal OE signal is
forced low. The side of the chip that has VDD set to 0.0V is "passively" tri-stated by the cold spare circuitry. In order to minimize transients and current consumption, the user is encouraged
to first apply a high level to the OEx pins and then power down
the appropriate supply.
POWER TABLE
Port B
Port A
OPERATION
5 Volts
3.3 Volts
Voltage Translator
5 Volts
5 Volts
Non Translating
3.3 Volts
3.3 Volts
Non Translating
VSS
VSS
Cold Spare
VSS
3.3V or 5V
Port A Warm Spare
3.3V or 5V
VSS
Port B Warm Spare
COLD SPARE
The UT54ACS164245SEI places the device into "Cold Spare"
mode when BOTH supplies are set to VSS +/_0.25V with a maximum 1Kimpedance between VDDx and VSS. While in Cold
Spare, the device places all outputs into a high impedance state
(see DC electrical parameters, Ics).
3
LOGIC DIAGRAM
2A1
3.3V PORT
1A4
(20)
2A7
(22)
2A8
(12)
4
2B7
(26)
(23)
1B8
2B6
(27)
1B7
(37)
2B5
(29)
1B6
(38)
2B4
(30)
(19)
2A6
(11)
1A8
(17)
2A5
2B3
(32)
1B5
(40)
(9)
1A7
1B4
(41)
(8)
1A6
(16)
2A4
2B2
(33)
1B3
(43)
(6)
1A5
(14)
2A3
2B1
(35)
1B2
(44)
OE2
(36)
(13)
2A2
(5)
(25)
1B1
(46)
(3)
1A3
(24)
OE1
(47)
(2)
1A2
DIR2
3.3V PORT
1A1
(48)
2B8
5 V PORT
(1)
5 V PORT
DIR1
OPERATIONAL ENVIRONMENT1
PARAMETER
LIMIT
UNITS
Total Dose
1.0E5
rad(Si)
SEL Immune
>114
MeV-cm2/mg
Neutron Fluence2
1.0E14
n/cm2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Not tested, inherent of CMOS technology.
ABSOLUTE MAXIMUM RATINGS1
SYMBOL
PARAMETER
LIMIT (Mil only)
UNITS
VI/O (Port B)2
Voltage any pin during operation
-.3 to VDD1 +.3
V
VI/O (Port A)2
Voltage any pin during operation
-.3 to VDD2 +.3
V
VDD1
Supply voltage
-0.3 to 6.0
V
VDD2
Supply voltage
-0.3 to 6.0
V
TSTG
Storage Temperature range
-65 to +150
C
TJ
Maximum junction temperature
+175
C
JC
Thermal resistance junction to case
20
C/W
II
DC input current
10
mA
PD
Maximum power dissipation
1
W
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability and performance.
2. For cold spare mode (VDD = VSS), VI/O may be -0.3V to the maximum recommended operating VDD + 0.3V.
DUAL SUPPLY OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMIT
UNITS
VDD1
Supply voltage
3.0 to 3.6 or 4.5 to 5.5
V
VDD2
Supply voltage
3.0 to 3.6 or 4.5 to 5.5
V
VIN (Port B)
Input voltage any pin
0 to VDD1
V
VIN (Port A)
Input voltage any pin
0 to VDD2
V
TC
Temperature range
-55 to + 125
C
5
DC ELECTRICAL CHARACTERISTICS 1
(Tc = -55C to +125C for "C" screening and -40C to +125C for "W" screening)
SYMBOL
PARAMETER
CONDITION
VT +
Schmitt Trigger, positive going threshold2
VT-
Schmitt Trigger, negative going threshold2 VDD from 3.0 to 5.5
VH1
Schmitt Trigger range of hysteresis
VH2
IIN
MIN
VDD from 3.0 to 5.5
MAX
UNIT
.7VDD
V
.3VDD
V
VDD from 4.5 to 5.5
0.6
V
Schmitt Trigger range of hysteresis
VDD from 3.0 to 3.6
0.4
V
Input leakage current
VDD from 3.6 to 5.5
-1
3
A
-1
3
A
-1
5
A
-1
5
A
-200
200
mA
-100
100
mA
0.4
V
VIN = VDD or VSS
IOZ
Three-state output leakage current
VDD from 3.6 to 5.5
VIN = VDD or VSS
ICS
Cold sparing leakage current3
VIN = 5.5
VDD = VSS
IWS
Warm sparing input leakage current (any
pin)3
VIN = 5.5V
VDD1 = VSS & VDD2 = 3.0V to 5.5V
or
VDD1 = 3.0V to 5.5V & VDD2 = VSS
IOS1
Short-circuit output current 6, 10
VO = VDD or VSS
VDD from 4.5 to 5.5
IOS2
Short-circuit output current 6, 10
VO = VDD or VSS
VDD from 3.0 to 3.6
VOL1
Low-level output voltage4
IOL= 8mA
IOL= 100A
0.2
VDD = 4.5
VOL2
Low-level output voltage4
IOL= 8mA
0.5
IOL= 100A
0.2
VDD = 3.0
VOH1
High-level output voltage4
V
IOH= -8mA
VDD - 0.7
IOH= -100A
VDD - 0.2
V
VDD = 4.5
VOH2
High-level output voltage4
IOH= -8mA
VDD - 0.9
IOH= -100A
VDD - 0.2
VDD = 3.0
6
V
Ptotal1
Power dissipation 5,7, 8
CL = 50pF
2.0
mW/
MHz
1.5
mW/
MHz
VDD from 4.5 to 5.5
Ptotal2
Power dissipation 5, 7, 8
CL = 50pF
VDD from 3.00 to 3.6
IDDQ
Standby Supply Current VDD1 or VDD2
VIN = VDD or VSS
VDD = 5.5
CIN
Pre-Rad 25oC
OE = VDD
60
A
Pre-Rad -55oC to +125oC
OE = VDD
100
A
Post-Rad 25oC
OE = VDD
100
A
Input capacitance 9
 = 1MHz @ 0V
15
pF
15
pF
VDD from 3.0 to 5.5
COUT
Output capacitance9
 = 1MHz @ 0V
VDD from 3.0 to 5.5
Notes:
1. All specifications valid for radiation dose  1E5 rad(Si) per MIL-STD-883, Method 1019.
2. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to VIH(min) and VIL(max).
3. This parameter is unaffected by the state of OEx or DIRx.
4. Per MIL-PRF-38535, for current density  5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765
pF-MHz.
5. Guaranteed by characterization.
6. Not more than one output may be shorted at a time for maximum duration of one second.
7. Power does not include power contribution of any CMOS output sink current.
8. Power dissipation specified per switching output.
9.Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
10. Supplied as a design limit, but not guaranteed or tested.
.
7
AC ELECTRICAL CHARACTERISTICS*1 (Port B = 5 Volt, Port A = 3.3 Volt)
(VDD1 = 5V 10%; VDD2 = 3.3V  0.3V) (Tc = -55C to +125C for "C" screening and -40C to +125C for "W" screening)
SYMBOL
PARAMETER
MIN
MAX
UNIT
UT54ACS164245SEI
tPLH
Propagation delay Data to Bus
3.5
11
ns
tPHL
Propagation delay Data to Bus
3.5
11
ns
tPZL
Output enable time OEx to Bus
2.5
16
ns
tPZH
Output enable time OEx to Bus
2.5
16
ns
tPLZ
Output disable time OEx to Bus high impedance
2.5
16
ns
tPHZ
Output disable time OEx to Bus high impedance
2.5
16
ns
tPZL2
Output enable time DIRx to Bus
1
18
ns
tPZH2
Output enable time DIRx to Bus
1
18
ns
tPLZ2
Output disable time DIRx to Bus high impedance
1
20
ns
tPHZ2
Output disable time DIRx to Bus high impedance
1
20
ns
tSKEW3
Skew between outputs
-
600
ps
tDSKEW4
Differential skew between outputs
-
1.5
ns
Notes:
1. All specifications valid for radiation dose  1E5 rad(Si) per MIL-STD-883, Method 1019.
2. DIRx to bus times are guaranteed by design, but not tested. OEx to bus times are tested
3. Output skew is defined as a comparison of any two output transitions of the same type at the saame temperature and voltage for the same port within the same byte:
1A1 through 1A8 are compared high-to-low versus high-to-low and low-to-high versus low-to-high; similarly 1B1 through 1B8 are compared, 2A1 through 2A8 are
compared, and 2B1 through 2B8 are compared.
4. Differential output skew is defined as a comparison of any two output transitions of opposite types on the same type at the same temperature and voltage for the same
port within the same byte: 1A1 through 1A8 are compared high-to-low versus low-to-high; similarly 1B1 through 1B8 are compared, 2A1 through 2A8 are compared,
and 2B1 through 2B8 are compared.
.
8
Propagation Delay
Input
tPLH
VDD
VDD/2
0V
tPHL
VOH
VDD/2
VOL
Output
Enable Disable Times
Control Input
5V Output
Normally Low
5V Output
Normally High
tPZL
tPLZ
VDD/2-0.2
tPHZ
tPZH
VDD/2+0.2
.8VDD - .2V
tPLZ
tPZL
3.3V Output
Normally Low
3.3V Output
Normally High
.2VDD + .2V
VDD/2-0.2
.2VDD + .2V
tPHZ
tPZH
VDD/2+0.2
9
.7VDD - .2V
VDD
VDD/2
0V
VDD/2
.2VDD
.8VDD
VDD/2
VDD/2
.2VDD
.7VDD
VDD/2
AC ELECTRICAL CHARACTERISTICS*1 (Port A = Port B, 5 Volt Operation)
(VDD1 = 5V  10%; VDD2 = 5.0V  10%) (Tc = -55C to +125C for "C" screening and -40C to +125C for "W" screening)
SYMBOL
PARAMETER
MIN
MAX
UNIT
UT54ACS164245SEI
tPLH
Propagation delay Data to Bus
3.5
9
ns
tPHL
Propagation delay Data to Bus
3.5
9
ns
tPZL
Output enable time OEx to Bus
3
9
ns
tPZH
Output enable time OEx to Bus
3
9
ns
tPLZ
Output disable time OEx to Bus high impedance
3
9
ns
tPHZ
Output disable time OEx to Bus high impedance
3
9
ns
tPZL2
Output enable time DIRx to Bus
1
12
ns
tPZH2
Output enable time DIRx to Bus
1
12
ns
tPLZ2
Output disable time DIRx to Bus high impedance
1
15
ns
tPHZ2
Output disable time DIRx to Bus high impedance
1
15
ns
tSKEW3
Skew between outputs
-
600
ps
tDSKEW4
Differential skew between outputs
-
1.5
ns
Notes:
1. All specifications valid for radiation dose  1E5 rad(Si) per MIL-STD-883, Method 1019.
2. DIRx to bus times are guaranteed by design, but not tested. OEx to bus times are tested
3. Output skew is defined as a comparison of any two output transitions of the same type at the saame temperature and voltage for the same port within the same byte:
1A1 through 1A8 are compared high-to-low versus high-to-low and low-to-high versus low-to-high; similarly 1B1 through 1B8 are compared, 2A1 through 2A8 are
compared, and 2B1 through 2B8 are compared.
4. Differential output skew is defined as a comparison of any two output transitions of opposite types on the same type at the same temperature and voltage for the same
port within the same byte: 1A1 through 1A8 are compared high-to-low versus low-to-high; similarly 1B1 through 1B8 are compared, 2A1 through 2A8 are compared,
and 2B1 through 2B8 are compared.
10
Propagation Delay
Input
tPLH
VDD
VDD/2
0V
tPHL
VOH
VDD/2
VOL
Output
Enable Disable Times
Control Input
5V Output
Normally Low
5V Output
Normally High
tPZL
tPLZ
.2VDD + .2V
VDD/2-0.2
tPHZ
tPZH
VDD/2+0.2
VDD
VDD/2
0V
VDD/2
.2VDD
.8VDD
.8VDD - .2V
VDD/2
Propagation Delay
Input
tPLH
VDD
VDD/2
0V
tPHL
VOH
VDD/2
VOL
Output
Enable Disable Times
Control Input
3.3V Output
Normally Low
3.3V Output
Normally High
tPZL
tPLZ
VDD/2-0.2
.2VDD + .2V
tPHZ
tPZH
VDD/2+0.2
11
.7VDD - .2V
VDD
VDD/2
0V
VDD/2
.2VDD
.7VDD
VDD/2
AC ELECTRICAL CHARACTERISTICS*1 (Port A = Port B, 3.3 Volt Operation)
(VDD1 = 3.3V + 0.3V; VDD2 = 3.3V + 0.3V) (Tc = -55C to +125C for "C" screening and -40C to +125C for "W" screening)
SYMBOL
PARAMETER
MIN
MAX
UNIT
UT54ACS164245SEI
tPLH
Propagation delay Data to Bus
3.5
11
ns
tPHL
Propagation delay Data to Bus
3.5
11
ns
tPZL
Output enable time OEx to Bus
2.5
16
ns
tPZH
Output enable time OEx to Bus
2.5
16
ns
tPLZ
Output disable time OEx to Bus high impedance
2.5
16
ns
tPHZ
Output disable time OEx to Bus high impedance
2.5
16
ns
tPZL2
Output enable time DIRx to Bus
1
18
ns
tPZH2
Output enable time DIRx to Bus
1
18
ns
tPLZ2
Output disable time DIRx to Bus high impedance
1
20
ns
tPHZ2
Output disable time DIRx to Bus high impedance
1
20
ns
tSKEW3
Skew between outputs
600
ps
tDSKEW4
Differential skew between outputs
1.5
ns
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019,
Condition A up to the maximum TID level procured.
1. All specifications valid for radiation dose  1E5 rad(Si) per MIL-STD-883, Method 1019.
2. DIRx to bus times are guaranteed by design, but not tested. OEx to bus times are tested.
3. Output skew is defined as a comparison of any two output transitions of the same type at the saame temperature and voltage for the same port within the same byte:
1A1 through 1A8 are compared high-to-low versus high-to-low and low-to-high versus low-to-high; similarly 1B1 through 1B8 are compared, 2A1 through 2A8
are compared, and 2B1 through 2B8 are compared.
4. Differential output skew is defined as a comparison of any two output transitions of opposite types on the same type at the same temperature and voltage for the
same port within the same byte: 1A1 through 1A8 are compared high-to-low versus low-to-high; similarly 1B1 through 1B8 are compared, 2A1 through 2A8 are
compared, and 2B1 through 2B8 are compared.
12
PACKAGE
5
6
4
6
1. All exposed metalized areas are gold plated over electroplated nickel per MIL-PRF-38535.
2. The lid is electrically connected to VSS.
3. Lead finishes are in accordance with MIL-PRF-38535.
4. Lead position and colanarity are not measured.
5. ID mark symbol is vendor option.
6. With solder, increase maximum by 0.003.
Figure 1. 48-Lead Flatpack
13
ORDERING INFORMATION
UT54ACS164245SEI: SMD
5962
R 98580 **
*
*
*
Lead Finish:
(C) = Gold
Case Outline:
(X) = 48 lead BB FP (Gold only)
Class Designator:
(Q) = Class Q
(V) = Class V
Device Type
(06) = 16-bit MultiPurpose Transceiver with warm and cold sparing (Full Mil-Temp)
(07) = 16-bit MultiPurpose Transceiver with warm and cold sparing (Extended Industrial Temp)
Drawing Number: 98580
Total Dose: (Note 1)
(R) = 1E5 rad(Si)
Federal Stock Class Designator: No options
Notes:
1. Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening.
14
UT54ACS164245SEI
UT54 *** ****** -* * *
Lead Finish:
(C)
= Gold
Screening:
(C) = HiRel Temp (-55oC to +125oC)
(P)
= Prototype (Room temp Only)
(W) = Extended Industrial Temp (-40oC to +125oC)
Package Type:
(U) = 48-lead BB FP (Gold only)
Part Number:
(164245SEI) = 16-bit MultiPurpose Transceiver with warm and cold sparing
I/O Type:
(ACS)=
CMOS compatible I/O Level
Aeroflex Core Part Number
Notes:
1. HiRel Temperature Range flow per Aeroflex Manufacturing Flows Document. Devices are tested -55C, room temp, and 125C. Radiation neither tested
nor guaranteed.
2. Extended Industrial Temperature Range Flow per Aeroflex Manufacturing Flows Document. Devices are tested at -40oC, room temp, and +125oC.
Radiation is neither tested nor guaranteed.
3. Extended Industrial Range flow per Aeroflex Colorado Springs Manufacturing Flows Document. Devices are tested at -40C, room temp, and 125C.
Radiation neither tested nor guaranteed.
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Aeroflex Colorado Springs - Datasheet Definition
Advanced Datasheet - Product In Development
Preliminary Datasheet - Shipping Prototype
Datasheet - Shipping QML & Reduced Hi-Rel
COLORADO
Toll Free: 800-645-8862
Fax: 719-594-8468
INTERNATIONAL
Tel: 805-778-9229
Fax: 805-778-1980
NORTHEAST
Tel: 603-888-3975
Fax: 603-888-4585
SE AND MID-ATLANTIC
Tel: 321-951-4164
Fax: 321-951-4254
WEST COAST
Tel: 949-362-2260
Fax: 949-362-2266
CENTRAL
Tel: 719-594-8017
Fax: 719-594-8468
www.aeroflex.com
[email protected]
Aeroflex Colorado Springs, Inc. reserves the right to make
changes to any products and services herein at any time
without notice. Consult Aeroflex or an authorized sales
representative to verify that the information in this data sheet
is current before using this product. Aeroflex does not assume
any responsibility or liability arising out of the application or
use of any product or service described herein, except as
expressly agreed to in writing by Aeroflex; nor does the
purchase, lease, or use of a product or service from Aeroflex
convey a license under any patent rights, copyrights,
trademark rights, or any other of the intellectual rights of
Aeroflex or of third parties.
Our passion for performance is defined by three
attributes represented by these three icons:
solution-minded, performance-driven and customer-focused
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