1 A A PCA: PCB: FAB DRW: ASSY DRW: SCH: 121-60210-01 600-60243-01 610-60235-01 620-60243-01 630-60242-01 CYPRESS SEMICONDUCTOR © 2015 Title CY8CKIT-059 PSoC 5LP Prototyping Kit Size B Date: 1 Document Number Rev 630-60242-01 Thursday, April 02, 2015 04 Sheet 1 of 3 5 4 J1 J2 provide silk for UART pins provide silk for I2C pins P2_6 P2_7 P12_4 P12_5 VSSD PROG_RESET XRES PROG_SWDIO P1_0 PROG_SWDCLK P1_1 P1_2 P_SWO P1_3 P_TDI P1_4 P1_5 VDDIO1 VDDIO PSoC 5LP I/O Header C 0402 EPAD P2_5 VDDIO2 P2_4 P2_3 P2_2 P2_1 P2_0 P15_5 P15_4 VDDD VSSD VCCD P0_7 P0_6 P0_5 P0_4 VDDIO0 I2C_SDA I2C_SCL C32 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 U2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 P2_6 P0_3 P2_7 P0_2 P12_4 I2C0_SCL, SIO P0_1 P12_5 I2C0_SDA, SIO P0_0 VSSB SIO_P12_3 IND SIO_P12_2 VBOOST VSSD CY8C5888LTI-LP097 QFN68 VBAT VDDA VSSD VSSA XRES VCCA P1_0 P15_3 P1_1 P15_2 P1_2 SIO, I2C1_SDA P12_1 P1_3 SIO, I2C1_SCL P12_0 P1_4 P3_7 P1_5 P3_6 VDDIO1 VDDIO3 P0_3 P0_2 P0_1 P0_0 P12_3 P12_2 VSSD VDDA VSSA VCCA P15_3 P15_2 P12_1 P12_0 P3_7 P3_6 VDDIO3 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 C34 1.0 uF SAR0 EXTREF 1.0 uF 0603 HDR 1x26 C12 0603 C7 C23 0402 0.1 uF 1.0 uF 0.1 uF DP R16 DM PSoC 5LP I/O Header SAR1 EXTREF EXTREF1 1.0 uF R18 LED1 820 ohm 2 R17 USER LED User LED BLUE SW1 P2_2 22E 1A 1B R5 22E P15_4 CMOD 0603 2200 pF VTARG B 0402 C29 0.1 uF C33 0402 0.1 uF J5 1 3 5 7 9 PROG_SWDIO PROG_SWDCLK P_SWO P_TDI PROG_RESET 2 4 6 8 10 R19 4.7K 50MIL KEYED SMD No Load I2C_SCL I2C_SDA UART RX UART TX R22 0603 R23 ZERO ZERO P12_7 P12_6 UART TX UART RX VTARG P15_2 VTARG SOD123 DM DP C27 0.1 uF Y1 2 R20 1 TP2 BLACK TP3 BLACK 32.768 KHz No Load C41 22 pF ZERO C42 22 pF J4 No Load No Load P5LP_VDD 0402 0402 No Load VDDIO R15 No Load HEADER 1X 2 ZERO A CYPRESS SEMICONDUCTOR © 2015 C19 0.01 uF This signals will be coming from Kitprog from Breakable area PCA: PCB: FAB DRW: ASSY DRW: SCH: 5 R11 ZERO P15_3 TP1 BLACK VDD P5LP_VDD PTC Resettable Fuse 0402 100K R12 0603 D2 1 2 S1 S2 S3 S4 VBUS DM DP ID GND B 2 P5LP_VDD F1 0402 HDR 1x5 No Load PROG_RESET PROG_SWDCLK PROG_SWDIO 1 2 3 4 5 6 7 8 9 1 2 3 4 5 USB Connector C17 0.1 uF No Load 0402 1 SW PUSHBUTTON No Load 0402 1 2 3 4 5 A J6 USB Micro-B VTARG SW2 XRES No Load XRES PSoC 5LP Program/Debug Header J3 USER PUSH BUTTON VTARG 1 2 1.0 uF TVS1 TVS DIODE 0603 2A 2B Switch 0603 ZERO C31 1.0 uF 1 0805 C4 C37 C 1.0 uF P2_1 VCCA P_VCCD P_VCCD 0603 P3_2,P0_2, P0_3 and P0_4 D these pins have bypass CAP connected No Load EXTREF0 1.0 uF 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 C21 0603 0603 0402 C9 P1_6 P1_7 P12_6 P12_7 DP_P DM_P VDDD VSSD P_VCCD P15_0 P15_1 P3_0 P3_1 P3_2 P3_3 P3_4 P3_5 C36 1.0 uF 0.1 uF P_XRES P0_7 P0_6 P0_5 P0_4 P0_3 P0_2 P0_1 P0_0 P15_5 P15_4 P15_3 P15_2 P15_1 P15_0 P3_7 P3_6 P3_5 P3_4 P3_3 P3_2 P3_1 P3_0 SAR Bypass Capacitors 0603 C26 0402 0603 0.1 uF C35 0402 C13 VDDD C22 0.1 uF 0603 0603 VDD 0.1 uF C18 0402 P0_4 P0_3 P0_2 P3_2 VDD VDDA C20 0402 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 VDDIO0 VDDIO1 VDDIO2 VDDIO3 P2_5 VDDIO2 P2_4 P2_3 P2_2 P2_1 P2_0 P15_5 P15_4 VDDD VSSD P_VCCD P0_7 P0_6 P0_5 P0_4 VDDIO0 UART TX UART RX HDR 1x26 No Load 0.1 uF 1 VDDIO P1_6 P1_7 P12_6_SIO P12_7_SIO P15_6 DP P15_7 DM VDDD VSSD VCCD P15_0 P15_1 P3_0 P3_1 P3_2 P3_3 P3_4 P3_5 D 2 PSoC 5LP Target Device P2_0 P2_1 P2_2 P2_3 P2_4 P2_5 P2_6 P2_7 P12_7 P12_6 P12_5 P12_4 P12_3 P12_2 P12_1 P12_0 P1_0 P1_1 P1_2 P1_3 P1_4 P1_5 P1_6 P1_7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 3 4 3 121-60210-01 600-60243-01 610-60235-01 620-60243-01 630-60242-01 2 Title CY8CKIT-059 PSoC 5LP Prototyping Kit Size B Date: Document Number Rev 630-60242-01 Wednesday, April 01, 2015 04 Sheet 1 2 of 3 5 4 3 2 1 Kitprog on-board Programmer / Debugger KP_P3_1 KP_VDD LED3 820 ohm R21 2 1 0805 KP_VDDIO0 KP_VDDIO1 KP_VDDIO2 KP_VDDIO3 C14 0.1 uF U1 KP_VDD VSSD KP_XRES C6 0603 0402 0.1 uF C VDDA C39 KP_VDDIO1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 P2_6 P0_3 P2_7 P0_2 P12_4 I2C0_SCL, SIO P0_1 P12_5 I2C0_SDA, SIO P0_0 VSSB SIO_P12_3 IND SIO_P12_2 VBOOST VSSD CY8C5868LTI-LP039 QFN68 VBAT VDDA VSSD VSSA XRES VCCA P1_0 P15_3 P1_1 P15_2 P1_2 SIO, I2C1_SDA P12_1 P1_3 SIO, I2C1_SCL P12_0 P1_4 P3_7 P1_5 P3_6 VDDIO1 VDDIO3 C38 0402 0603 VBUS POWER LED Amber D1 Power LED 1.0 uF 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 KP_P0_3 KP_P0_2 KP_P0_1 KP_P0_0 KP_P12_3 KP_P12_2 VSSD VDDA SW3 PROG_RESET VCCA KP_P12_1 KP_P12_0 2A 2B Switch C15 0603 C16 C8 0603 1.0 uF 1.0 uF SAR Bypass Capacitor 1.0 uF VTARG C KP_P3_6 KP_VDDIO3 KP_P2_6 KP_P2_7 R9 2.2K 2 R7 2.2K P3_3, P3_2, P0_7, P0_6, P0_5, P0_4 pins are reserved for HW REV ID 5(MSB) 4 P3.3 P3.2 Floating GND 3 2 1 P0.7 P0.6 P0.5 P0.4 Floating Floating GND Floating U3 NTZD3152P 0(LSB) 6 KP_P3_4 KP_P3_5 C30 1.0 uF KP_P3_0 KP_P3_1 KP_P1_6 KP_P1_7 KP_P12_6 KP_P12_7 KP_DP_P KP_DM_P VDDD VSSD KP_VCCD VCCA 1A 1B KP_P0_4 KP_P0_3 KP_P0_2 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 0.1 uF D 1 4 C25 2 3 KP_P2_6 KP_P2_7 KP_P12_4 KP_P12_5 0.1 uF VDDD 1.0 uF VTARG EPAD P2_5 VDDIO2 P2_4 P2_3 P2_2 P2_1 P2_0 P15_5 P15_4 VDDD VSSD VCCD P0_7 P0_6 P0_5 P0_4 VDDIO0 C5 0402 1.0 uF 560 ohm 0805 P1_6 P1_7 P12_6_SIO P12_7_SIO P15_6 DP P15_7 DM VDDD VSSD VCCD P15_0 P15_1 P3_0 P3_1 P3_2 P3_3 P3_4 P3_5 C24 R10 ZERO SOD123 VDDD 0603 LED2 R8 5 0402 1 0402 0.1 uF 0.1 uF VDDD VSSD KP_VCCD KP_P0_7 KP_P0_6 KP_P0_5 KP_P0_4 KP_VDDIO0 C3 KP_VDDIO2 C1 0402 0.1 uF VBUS 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 C11 0402 Status LED VBUS KP_VDD 0603 D Status LED Green KP_P12_1 I2C_SDA 0603 VTARG VBUS 0402 C28 0.1 uF R1 4.7K R3 15K R2 15K KP_P1_6 KP_P1_7 KP_XRES No Load 0603 C10 1.0 uF C2 0402 R14 30K Place Near PSoC 5LP KP_P12_0 J9 KP_P12_5 I2C_SCL I2C_SDA UART RX UART TX VTARG 1 2 3 4 5 PTC Resettable Fuse C40 0.1 uF 1 2 3 4 5 Target PSoC Program/Debug Header HDR 1x7 No Load A PCA: PCB: FAB DRW: ASSY DRW: SCH: 121-60210-01 600-60243-01 610-60235-01 620-60243-01 630-60242-01 CYPRESS SEMICONDUCTOR © 2015 Title CY8CKIT-059 PSoC 5LP Prototyping Kit Size B Date: 4 1 2 3 4 5 6 7 PROG_RESET PROG_SWDCLK PROG_SWDIO USB Finger Connector 5 J8 KP_P3_0 KP_P3_4 KP_P3_5 KP_P3_6 KP_P0_0 KP_P0_1 KitProg I/O Headers KP_P12_4 KP_P12_3 KP_P12_2 HDR 1x5 No Load 0402 USB FINGER 1 2 3 4 5 6 7 HDR 1x7 No Load J7 KP_DM KP_DP UART RX VBUS F2 VBUS DM DP GND KP_P12_6 R13 30K VBUS 1 2 3 4 UART TX B 0.1 uF J10 KP_P12_7 I2C & UART Connection No Load A I2C_SCL GND read as binary "1" floating pin is read as binary "0" KP_DP KP_DM KP_VCCD B 0603 0603 22E R4 22E R6 KP_VDD 3 2 Document Number Rev 630-60242-01 Wednesday, March 11, 2015 04 Sheet 1 3 of 3