DK-START-4CGX15N Starter Kit Schematic

8
7
6
5
4
NOTES:
E
3
REV
A
1. Project Drawing Numbers:
Raw PCB
Gerber Files
PCB Design Files
Assembly Drawing
Fab Drawing
Schematic Drawing
PCB Film
Bill of Materials
Schematic Design Files
Functional Specification
PCB Layout Guidelines
Assembly Rework
100-0311002-B1
110-0311002-B1
120-0311002-B1
130-0311002-B1
140-0311002-B1
150-0311002-B1
160-0311002-B1
170-0311002-B1
180-0311002-B1
210-0311002-B1
220-0311002-B1
320-0311002-B1
2
DATE
PAGES
11/04/2009
All
1
DESCRIPTION
Rev A Release
E
Cyclone IV GX Transceiver Starter Kit Board
PAGE
1
D
2
3
4
5
6
7
8
9
10
11
C
12
13
14
15
DESCRIPTION
Title, Notes, Block Diagram, Revision History
FPGA Package Top
Cyclone IV GX Configuration
Cyclone IV GX Banks
Cyclone IV GX Clock
Cyclone IV GX Transceivers I/O and Power
10/100/1000 Ethernet
PCI Express Edge Connector
SRAM & FLASH
User IO & Power Monitor
EPM2210 System Controller
Embedded USB Blaster
Power - 2.5V and 1.2V Output
Power - 5V, 3.3V and 2.5V Output
Cyclone IV GX Decoupling
D
C
16
17
18
19
20
B
B
21
22
23
24
25
26
27
28
29
A
A
Altera Corporation, 9330 Scranton Rd, San Diego, CA 92121
Copyright (c) 2009 Altera Corporation. All Rights Reserved.
Title
Cyclone IV GX FPGA Development Kit Board
Size
B
Date:
8
7
6
5
4
3
Document Number
Rev
150-0311002-B1 (6XX-42746R)
Wednesday, March 03, 2010
2
Sheet
B
1
of
1
15
8
7
6
E
4
3
2
1
FPGA Package Top View
Notes:
1.
5
FPGA Schematic Symbol Breakdown:
(A) Configuration
(B) Clocks
(C) Banks
(D) Transceivers
(E) Power
(F) GND
E
D
D
C
C
B
B
A
A
Altera Corporation, 9330 Scranton Rd, San Diego, CA 92121
Copyright (c) 2009 Altera Corporation. All Rights Reserved.
Title
Cyclone IV GX FPGA Development Kit Board
Size
B
Date:
8
7
6
5
4
3
Document Number
Rev
150-0311002-B1 (6XX-42746R)
Wednesday, March 03, 2010
2
Sheet
B
2
of
1
15
8
7
6
5
4
3
2
1
Cyclone IV GX Configuration
Configuration Signals
2.5V
S8
R105
R106
R107
R108
1.00k
1.00k
1.00k
10.0K
TDA04H0SB1
Cyclone IV GX Configuration
2.5V
R84
R121
R85
R81
10.0K
10.0K
10.0K
10.0K
FPGA_DCLK
A4
DCLK
FPGA_nSTATUS
FPGA_nCONFIG
FPGA_CONF_DONE
FPGA_NCE
K6
D5
J5
C4
NSTATUS
NCONFIG
CONF_DONE
NCE
FPGA_CONFIG_D0
A5
DATA0/IO
USER_LED3
CPU_RESETn
USB Blaster Programming Header
(uses JTAG mode only)
M6
D10
2.5V
TCK
TMS
TDI
TDO
MSEL0
MSEL1
MSEL2
INIT_DONE/IO/DIFFIO_B2P
DEV_CLRN/IO/DIFFIO_R2N
2
4
6
8
10
D
R119
R120
User IO
FPGA_MSEL0
FPGA_MSEL1
FPGA_MSEL2
K5
N3
L3
JTAG_TCK
JTAG_BLASTER_TDI
JTAG_TMS
JTAG_BLASTER_TDO
EPCS_nCS
2.5V
C71
0.1uF
3.3V
C70
0.1uF
1
2
3
4
USER_LED[3..0]
USER_LED[3..0]
CPU_RESETn
CLK_SEL
USER_PGM
CPU_RESETn 10
CLK_SEL 5,11
USER_PGM 11
4,10
JTAG Signals
2.5_VCC
S7
1
3
5
7
9
E
10.0K
10.0K
EP4CGX15F14
J1
USB_DISABLEn
JTAG_TCK
JTAG_TMS
JTAG_BLASTER_TDO
JTAG_FPGA_TDO
B3
A2
A3
A1
FPGA_DCLK 11
FPGA_nSTATUS 11
FPGA_nCONFIG 11
FPGA_CONF_DONE 11
FPGA_CONFIG_D0 11
FPGA_DCLK
FPGA_nSTATUS
FPGA_nCONFIG
FPGA_CONF_DONE
FPGA_CONFIG_D0
2.5V
U8A
8
7
6
5
OPEN
E
CLK_SEL
USER_PGM
EPM2210_JTAG_EN
PCIE_JTAG_EN
8
7
6
5
OPEN
1
2
3
4
EPCS_nCS_PU
R76
R77
R70
R78
1.00k
1.00k
1.00k
10.0K
TDA04H0SB1
JTAG_TCK
JTAG_TMS
JTAG_BLASTER_TDO
JTAG_FPGA_TDO
JTAG_EPM2210_TDO
JTAG_BLASTER_TDI
USB_DISABLEn
JTAG_TCK 11,12
JTAG_TMS 11,12
JTAG_BLASTER_TDO 12
JTAG_FPGA_TDO 11
JTAG_EPM2210_TDO 11
JTAG_BLASTER_TDI 12
USB_DISABLEn
D
12
HDR 2X5, VERTICAL, SMD
U13
R17
JTAG_TCK
R16
1.00k
DNI JTAG_TCK_R
C2
DNI
JTAG_TCK
JTAG_PCIE_TDI
JTAG_PCIE_TDO
JTAG_TMS
PCIE_JTAG_EN
Place at the end of JTAG Chain near PCIE
1
2
3
4
5
6
8
VCCA
A1
A2
A3
A4
NC1
EN
VCCY
Y1
Y2
Y3
Y4
NC2
GND
14
13
12
11
10
9
7
PCIe JTAG Signals
2.5V
PCIE_JTAG_TCK
PCIE_JTAG_TDI
PCIE_JTAG_TDO
PCIE_JTAG_TMS
PCIE_JTAG_TCK
PCIE_JTAG_TMS
PCIE_JTAG_TDO
PCIE_JTAG_TDI
C205
R131
100, 1%
0.1uF
ADG3304BRUZ
DUAL_SPDT_PW
1
EPM2210_JTAG_EN
EPCS INTERFACES
U22
EPCS_nCS
EPCS_ASDI
5
JTAG_FPGA_TDO
2
JTAG_EPM2210_TDO
C
4
3
PCIE_JTAG_TCK 8
PCIE_JTAG_TMS 8
PCIE_JTAG_TDO 8
PCIE_JTAG_TDI 8
EPCS_nCS 4,11
EPCS_ASDI 4
C
CONFIGURATION
JTAG_PCIE_TDI
FPGA_MSEL[2..0]
FPGA_MSEL[2..0]
11
7
PCIE_JTAG_EN
10
JTAG_PCIE_TDO
9
JTAG_BLASTER_TDI
8
6
DUAL SPDT, NLAS4717EPMTR2G
3.3V
J12
B
FPGA_DCLK
FPGA_CONF_DONE
FPGA_nCONFIG
FPGA_D0_R
EPCS_ASDI
3.3V
1
3
5
7
9
B
1
3
5
7
9
2
4
6
8
10
2
4
6
8
10
FPGA_NCE
EPCS_nCS
EPCS128
A
GND
DATA
DCLK
nCS
ASDI
8
16
7
15
FPGA_D0_R R18
FPGA_DCLK
EPCS_nCS
EPCS_ASDI
24.9 FPGA_CONFIG_D0
10
NC01
NC02
NC03
NC04
NC05
NC06
NC07
NC08
VCC01
VCC02
VCC03
3
4
5
6
11
12
13
14
1
2
9
DNI
U15
A
Altera Corporation, 9330 Scranton Rd, San Diego, CA 92121
Copyright (c) 2009 Altera Corporation. All Rights Reserved.
Title
Cyclone IV GX FPGA Development Kit Board
Size
B
Date:
8
7
6
5
4
3
Document Number
Rev
150-0311002-B1 (6XX-42746R)
Wednesday, March 03, 2010
2
Sheet
B
3
of
1
15
8
7
6
5
4
3
2
1
Cyclone IV GX Banks
FLASH & SRAM & LCD INTERFACE
E
U8C
Cyclone IV GX
BANK 3
FSML_A0
USER_LED2
MAX_CSn
SRAM_CLK
N4
N5
L5
L7
CRC_ERROR/IO/DIFFIO_B1P
NCEO/IO/DIFFIO_B1N
IO/DQS1B/CQ0B#,DPCLK2
IO/VREFB3N0
IO/PLL1_CLKOUTP
IO/PLL1_CLKOUTN
L4
M4
SRAM_BWan
SRAM_BWbn
IO/DIFFIO_B2N/DQ0B
N6
SRAM_CEn
K10
L11
L9
M9
N10
N11
FSML_A8
FSML_A9
LCD_CSn
FSML_A10
FSML_A11
FSML_A12
D
IO/DIFFIO_R5P/DQ0R
IO/DIFFIO_R5N/DQ0R
IO/DIFFIO_R6P/DQ0R
IO/DIFFIO_R6N/DQ0R
IO/DIFFIO_R7P/DQ0R
IO/DIFFIO_R7N/DQ0R
J13
K13
L12
L13
K11
K12
FSML_A17
FSML_A18
FSML_A19
FSML_A20
FSML_A21
FSML_A22
F10
F11
G9
G10
FSML_D5
FSML_D6
FSML_D7
FSML_D8
C8
B8
B13
A13
D13
C13
FSML_D15
FLASH_CEn
FSML_OEn
FSML_WEn
FSML_A23
USER_LED1
IO/PLL2_CLKOUTP
IO/PLL2_CLKOUTN
A8
A7
FSML_A4
FSML_A5
NC1
NC2
N2
M3
FSML_D[15:0] 9,10,11
FSML_A[23:0]
FSML_A[23:0] 9,10,11
FSML_OEn
FSML_WEn
SRAM_BWan
SRAM_BWbn
SRAM_CEn
SRAM_CLK
FLASH_CEn
LCD_CSn
FSML_OEn 9,11
FSML_WEn 9,11
SRAM_BWan 9,11
SRAM_BWbn 9,11
SRAM_CEn 9,11
SRAM_CLK 9,11
FLASH_CEn 9,11
LCD_CSn 10
E
LED INTERFACES
BANK 4
USER_LED0
ENET_MDC
ENET_MDIO
ENET_RESETn
FSML_A6
FSML_A7
FSML_D[15:0]
N8
N9
K8
K9
M11
N12
IO/DIFFIO_B3P/DQ0B
IO/PLL3_CLKOUTP
IO/DIFFIO_B3N/DQ0B
IO/PLL3_CLKOUTN
IO/VREFB4N0
IO/DIFFIO_B4P/DQ0B
IO/DQ0B
IO/DIFFIO_B4N/DQS0B/CQ0B,DPCLK5
IO/RUP2/DQ0B
IO/DIFFIO_B5P/DQ0B
IO/RDN2/DM0B
IO/DIFFIO_B5N/DQ0B
FSML_A13
FSML_A14
H10
H12
IO/DQS1R/CQ0R#,DPCLK7
IO/VREFB5N0
FSML_A15
FSML_A16
N13
M13
IO/RUP3
IO/RDN3
FSML_D0
FSML_D1
FSML_D2
FSML_D3
FSML_D4
D11
D12
E10
F9
E13
IO/DIFFIO_R1P
IO/DIFFIO_R1N
IO/DIFFIO_R3P/DQ0R
IO/DIFFIO_R2P/DM0R
IO/DIFFIO_R3N/DQ0R
IOB6
IO/DIFFIO_R4P/DQS0R/CQ0R,DPCLK8
IO/VREFB6N0
DEV_OE/IO/DIFFIO_R4N
FSML_D9
FSML_D10
FSML_D11
FSML_D12
FSML_D13
FSML_D14
A12
A11
B11
B10
C11
C12
USER_LED[3..0]
USER_LED[3..0]
3,10
EPCS INTERFACES
D
EPCS_nCS 3,11
EPCS_ASDI 3
EPCS_nCS
EPCS_ASDI
BANK 5
ETHERNET INTERFACE
ENET_RESETn
ENET_MDIO
ENET_MDC
ENET_RESETn 7
ENET_MDIO 7
ENET_MDC 7
BANK 6
C
MAX II INTERFACE
MAX_CSn 11
MAX_CSn
C
BANK 7
IO/DIFFIO_T1P/DM0T
DQ0T/IO/DIFFIO_T2P
DQ0T/IO/DIFFIO_T1N
DQ0T/IO/DIFFIO_T2N
IOB7
DQ0T/IO/DIFFIO_T3P
IO/VREFB7N0
IO/DIFFIO_T3N/DQS0T/CQ0T,DPCLK10
DQ0T/IO/RUP4
DQ0T/IO/DIFFIO_T4P
DQ0T/IO/RDN4
DQ0T/IO/DIFFIO_T4N
BANK 8
FSML_A1
FSML_A2
FSML_A3
A6
B6
C6
CLKUSR/IO
IODQS1T/CQ0T#,DPCLK13
IO/VREFB8N0
EPCS_nCS
EPCS_ASDI
C5
B5
NCSO/IO
ASDO/IO
BANK 9
B
B
EP4CGX15F14
A
A
Altera Corporation, 9330 Scranton Rd, San Diego, CA 92121
Copyright (c) 2009 Altera Corporation. All Rights Reserved.
Title
Cyclone IV GX FPGA Development Kit Board
Size
B
Date:
8
7
6
5
4
3
Document Number
Rev
150-0311002-B1 (6XX-42746R)
Wednesday, March 03, 2010
2
Sheet
B
4
of
1
15
5
4
3
2
1
Cyclone IV GX Banks & Clock
100MHz crystal footprint compatible
with Si570 programmable oscillator
2.5V
2.5V
C33
2.5V
C21
C10
C11
0.1uF
0.1uF
2.5V
CLOCK
2.5V
CLK125_EN
CLK_SEL
X1
CLK125_EN
2
OE
VCC
6
CLK125_SDA
7
SDA
CLK-
5
CLK125_SCK
8
SCL
CLK+
4
NC
1
2.5V
R34
84.5
3
R35
84.5
GND
U6
DIFF_OE
DIFF_EN
8
2
125M_OSC_P
LVDS
R23
100, 1%
125MHz
J3
C40
1 CLKIN_SMA_P
LTI-SASF546-P26-X1
5
4
3
2
CLKIN_SMA_CP
CLKIN_SMA_CN
R33
124
J2
100, 1%
100, 1%
C
0.1uF
R21
R20
125M_OSC_N
CLKIN_SMA_CP
CLKIN_SMA_CN
C41
0.1uF
CLK_SEL
CLK_SEL
DIP Setting
OSC
'0' = ON
'1' = OFF
SMA
Board Settings DIP Switch
1 CLKIN_SMA_N
LTI-SASF546-P26-X1
5
4
3
2
R32
124
R89
4.7K
10
18
R86
4.7K
LVPECL INPUT CLOCK
OE
CLK_EN
C138
C127
0.1uF
0.1uF
2.2uF
CLK125_EN 11
CLK_SEL 3,11
125_REFCLK_P
125_REFCLK_N
Q0P
Q0p
Q0n
20
19
Q1p
Q1n
17
16
4
5
CLKp
CLKn
6
7
PCLKp
PCLKn
Q2p
Q2n
15
14
3
CLK_SEL
Q3p
Q3n
12
11
ICS8543
C113
LVDS
VDD
VDD
0.1uF 10uF
R15
1.00k
GND
GND
GND
D
R19
10.0K
R24
Q0N
C32
DNI
C37
0.1uF
0.1uF
D
125_REFCLK_P 6
125_REFCLK_N 6
125_REFCLK_P
I2C
125_REFCLK_N
CLK125_SDA
CLK125_SCK
125_DIFF_P
125_DIFF_N
CLK125_SDA 11
CLK125_SCK 11
1
9
13
R22
10.0K
C
Can also operate single-ended
1.0V pk-pk MAX
125_DIFF_P
U8B
R91
100
Cyclone IV GX Clocks
LCD & USER I/O INTERFACES
BANK 4
125_DIFF_N
B
M7
N7
CLK14/DIFFCLK_6P
CLK15/DIFFCLK_6N
H13
G13
CLK5/DIFFCLK_2P
CLK4/DIFFCLK_2N
USER_PB[1..0]
USER_PB[1..0]
10
B
BANK 5
USER_PB0
USER_PB1
2.5V
2.5V
PCIE INTERFACE
PCIE_PERSTn
PCIE_PERSTn 8
BANK 6
ENET_INTn
R90
1.00k
C128
C129 3.3V
2.2uF
0.1uF
U18
X5
CLK50_EN
1
EN
VCC
4
2
GND
OUT
3
F12
F13
2.5V
50M_OUT
50MHz
1
2
VDDO
VDD
3
CLK
4
GND
R116
22
Q0
Q1
Q2
Q3
5
6
7
8
CLK_B7R_SE
CLK_MAXII_R
MAX II CLOCK
CLK7/DIFFCLK_3P
CLK6/DIFFCLK_3N
CLK_MAXII
CLK_MAXII 11
BANK 7
PCIE_PERSTn
CLK_B7_SE
A10
A9
ETHERNET INTERFACE
CLK9/DIFFCLK_5P
CLK8/DIFFCLK_5N
ENET_INTn
ENET_INTn 7
CLK_MAXII
EP4CGX15F14
R114
22
Clock Buffer, ICS8304
A
A
Altera Corporation, 9330 Scranton Rd, San Diego, CA 92121
Copyright (c) 2009 Altera Corporation. All Rights Reserved.
Title
Cyclone IV GX FPGA Development Kit Board
Size
B
Date:
5
4
3
2
Document Number
Rev
150-0311002-B1 (6XX-42746R)
Wednesday, March 03, 2010
Sheet
1
5
B
of
15
8
7
6
5
4
3
2
1
Cyclone IV GX Transceivers I/O and Power
J9
LTI-SASF546-P26-X1
SMA_RX_N
C57
DNI
SMA_RX_P
C60
DNI
ENET_RX_N
D
0.1uF
U8D
0.1uF
C59
E
SMA_TX_N
R54
DNI
PCIE_RX_P
PCIE_RX_N
J2
J1
GXB_RX0P
GXB_RX0N
GXB_TX0P
GXB_TX0N
G2
G1
PCIE_TX_P
PCIE_TX_N
ENETR_RX_P
ENETR_RX_N
E2
E1
GXB_RX1P
GXB_RX1N
GXB_TX1P
GXB_TX1N
C2
C1
ENETR_TX_P
ENETR_TX_N
PCIE_REFCLK_P
PCIE_REFCLK_N
J6
J7
CLK12/DIFFCLK_7P,REFCLK0P
CLK13/DIFFCLK_7N,REFCLK0N
125_REFCLK_P
E7
E6
CLK11/DIFFCLK_4P,REFCLK1P
CLK10/DIFFCLK_4N,REFCLK1N
C58
5
4
3
2
SMA_TX_P
Cyclone IV GX Transceivers
ENET_RX_P
J10
LTI-SASF546-P26-X1
5
4
3
2
1
1
5
4
3
2
1
5
4
3
2
E
J11
LTI-SASF546-P26-X1
1
J8
LTI-SASF546-P26-X1
R51
DNI
0
R53 ENET_TX_P
0
R52 ENET_TX_N
D
R104
100
RREF0
L1
R93
RREF
2.00K
EP4CGX15F14
125_REFCLK_N
C
C
U8E
U8F
Cyclone IV GX Power
1.2_VCCINT
Core Power 1.2V
E4
E8
F5
F7
G4
G6
G8
H5
H7
J8
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
2.5_VCC
PLL Analog Power 2.5V
D4
K4
H9
D9
B
VCCA
VCCA
VCCA
VCCA
VCCIO3
L6
VCCIO4
VCCIO4
L8
L10
VCCIO5
VCCIO5
J11
H11
VCCIO6
VCCIO6
E11
G11
VCCIO7
VCCIO7
C10
C9
VCCIO8
C7
VCCIO9
C3
1.2_VCCD_PLL
1.2_VCCL_GXB
PLL Digital Power 1.2V
D3
J4
J10
Cyclone IV GX Ground
2.5_VCCIO
IO Bank Power
ETHERNET INTERFACE
B1
B2
B4
B7
B9
B12
D1
D2
D6
D8
E3
E5
E9
E12
F1
F2
F4
F6
F8
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
ENET_RX_P
ENET_RX_N
G5
G7
G12
H1
H2
H4
H6
H8
J9
J12
K1
K2
K3
L2
M1
M5
M8
M10
M12
ENET_TX_P
ENET_TX_N
125_REFCLK_P
125_REFCLK_N
VCCL_GXB
VCCL_GXB
VCCL_GXB
ENET_TX_P 7
ENET_TX_N 7
125_REFCLK_P 5
125_REFCLK_N 5
PCIe EDGE GOLD FINGER
PCIE_RX_P
PCIE_RX_N
PCIE_TX_P
PCIE_TX_N
PCIE_REFCLK_P
PCIE_REFCLK_N
Transceiver PMA Power 1.2V
VCCD_PLL
VCCD_PLL
VCCD_PLL
ENET_RX_P 7
ENET_RX_N 7
PCIE_RX_P 8
PCIE_RX_N 8
B
PCIE_TX_P 8
PCIE_TX_N 8
PCIE_REFCLK_P
PCIE_REFCLK_N
8
8
EP4CGX15F14
F3
H3
N1
2.5_VCC_GXB
DIFF Clock Input Power
K7
D7
Transceiver (Tx) Power 2.5V
VCC_CLKIN3
VCC_CLKIN8
VCCH_GXB
G3
Transceiver PMA Power 2.5V
VCCA_GXB
VCCA_GXB
A
J3
M2
A
Altera Corporation, 9330 Scranton Rd, San Diego, CA 92121
Copyright (c) 2009 Altera Corporation. All Rights Reserved.
EP4CGX15F14
Title
Cyclone IV GX FPGA Development Kit Board
Size
B
Date:
8
7
6
5
4
3
Document Number
Rev
150-0311002-B1 (6XX-42746R)
Wednesday, March 03, 2010
2
Sheet
B
6
of
1
15
8
7
6
5
4
3
2
1
10/100/1000 Ethernet
ETHERNET INTERFACE
ENET_RX_P 6
ENET_RX_N 6
ENET_RX_P
ENET_RX_N
U9A
R44
R43
R42
R41
R57
R58
R56
R55
MDI_T0_R
MDI_T1_R
0.01uF
MDI_T2_R
0.01uF
C67
0.01uF
MDI_P0
MDI_N0
MDI_P1
MDI_N1
MDI_P2
MDI_N2
MDI_P3
MDI_N3
29
31
33
34
39
41
42
43
MDI0_P
MDI0_N
MDI1_P
MDI1_N
MDI2_P
MDI2_N
MDI3_P
MDI3_N
ENET_MDIO
ENET_MDC
ENET_INTn
24
25
23
MDIO
MDC
INT_N
37
38
HSDAC_P
HSDAC_N
30
56
RSET
SEL_FREQ
2.5V
MDI_T3_R
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
2.5V
MDI_P0
MDI_N0
MDI_P1
MDI_N1
MDI_P2
MDI_N2
MDI_P3
MDI_N3
GND_TAB
GND_TAB
D
2.5V
12
11
9
TD0_P
TD0_N
1
2
TD1_P
TD1_N
3
6
TD2_P
TD2_N
4
5
TD3_P
TD3_N
7
8
GND
ENET_LED_LINK1000
ENET_LED_LINK10
ENET_LED_RX
10
HFJ11-1G02E
ENET_RSET
2.5V
X4
25M_EN
1
EN
VCC
4
2
GND
OUT
3
R49
22
ENET_25MHZ
ENET_XTAL_25MHZ
25.00MHz
C56
0.01uF
C
ENET_TRST_N
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
13
51
NC1
NC2
97
VSS
B
5
21
88
96
R124
4.7K
47
49
44
50
46
TRST_N
TCK
TDI
TDO
TMS
ENET_TX_P 6
ENET_TX_N 6
TXD0
TXD1
TXD2
TXD3
TXD4
TXD5
TXD6
TXD7
11
12
14
16
17
18
19
20
ENET_INTn
ENET_RESETn
ENET_MDIO
ENET_MDC
ENET_INTn 5
ENET_RESETn 4
ENET_MDIO 4
ENET_MDC 4
RXCLK
RX_DV
RX_ER
2
94
3
RXD0
RXD1
RXD2
RXD3
RXD4
RXD5
RXD6
RXD7
95
92
93
91
90
89
87
86
CRS
COL
84
83
S_CLK_P
S_CLK_N
S_IN_P
S_IN_N
S_OUT_P
S_OUT_N
79
80
82
81
77
75
LED_TX
LED_RX
LED_DUPLEX
LED_LINK1000
LED_LINK100
LED_LINK10
68
69
70
73
74
76
D
SGMII Mode (default)
ENET_TX_P
ENET_TX_N
ENET_RX_P
ENET_RX_N
ENET_LED_TX
ENET_LED_RX
C
ENET_LED_LINK1000
ENET_LED_LINK100
ENET_LED_LINK10
2.5V
88E1111
72
66
52
VDDOH
VDDOH
VDDOH
32
36
35
40
45
78
VDDO
VDDO
VDDO
VDDO
U9B
VDDOX
VDDOX
26
48
R115
4.99K
125CLK
XTAL1
XTAL2
VSSC
JTAG
2.5V
22
55
54
53
ENET_TX_P
ENET_TX_N
TEST
R50
10.0K
VCC
1.2V
D14
ENET_LED_TX
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
E
8
4
9
7
GTX_CLK
TX_CLK
TX_EN
TX_ER
SGMII INTERFACE
ENET_MDIO
ENET_MDC
ENET_RESETn
ENET_INTn
0.01uF
C68
CONFIG0
CONFIG1
CONFIG2
CONFIG3
CONFIG4
CONFIG5
CONFIG6
MGMT
4.7K
4.7K
4.7K
4.7K
J7
C42
65
64
63
61
60
59
58
ENET_RESETn
R47
R46
R45
R48
C43
COMA
RESET_N
MDI INTERFACE
2.5V
27
28
GMII/MII/TBI INTERFACE
E
1
6
10
15
57
62
67
71
85
R59
220
ENET_LEDR_TX
Green_LED
D15
ENET_LED_RX
R60
220
ENET_LEDR_RX
Green_LED
D16
ENET_LED_LINK1000 R61
220
ENET_LEDR_LINK1000
Green_LED
D17
ENET_LED_LINK100
R62
220
B
ENET_LEDR_LINK100
88E1111
Green_LED
D18
ENET_LED_LINK10
Place near 88E1111 PHY
2.5V
R63
220
ENET_LEDR_LINK10
Green_LED
1.2V
C44
C55
C50
C51
C45
C47
C49
C54
C61
C63
C169
C170
C64
C62
C48
C52
C46
10uF
10uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
10uF
10uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
A
A
Altera Corporation, 9330 Scranton Rd, San Diego, CA 92121
Copyright (c) 2009 Altera Corporation. All Rights Reserved.
Title
Cyclone IV GX FPGA Development Kit Board
Size
B
Date:
8
7
6
5
4
3
Document Number
Rev
150-0311002-B1 (6XX-42746R)
Wednesday, March 03, 2010
2
Sheet
B
7
of
1
15
8
7
6
5
4
3
2
1
PCI Express Edge Connector
PCIe EDGE GOLD FINGER
E
3.3V_PCIE
12V_PCIE
12V_PCIE
3.3V_PCIE
PCIE_JTAG_TCK
PCIE_JTAG_TDI
PCIE_JTAG_TDO
PCIE_JTAG_TMS
PCIE_JTAG_TCK
PCIE_JTAG_TDI
PCIE_JTAG_TDO
PCIE_JTAG_TMS
PCIE_RX_P
PCIE_RX_N
PCIE_RX_P 6
PCIE_RX_N 6
3
3
3
3
E
U14
R64
D
DNI 3.3V_PCIE_AUX
PCIE_RX_P
PCIE_RX_N
PCIE_PRSNTn_x1
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
+12V
PRSNT1_N
+12V
+12V
+12V
+12V
GND
GND
SMCLK
JTAG_TCK
SMDAT
JTAG_TDI
GND
JTAG_TDO
+3_3V
JTAG_TMS
JTAG_TRSTN
+3_3V
+3_3VAUX
+3_3V
WAKE_N
PERST_N
KEY
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
B12
B13
B14
B15
B16
B17
B18
RSVD1
GND
X1
GND
REFCLK+
PET0P
REFCLKPET0N
GND
GND
PER0P
PRSNT2_N_X1
PER0N
GND
GND
A12
A13
A14
A15
A16
A17
A18
PCIE_TX_P 6
PCIE_TX_N 6
PCIE_PRSNTn_x1
PCIE_TX_P
PCIE_TX_N
PCIE_JTAG_TCK
PCIE_JTAG_TDI
PCIE_JTAG_TDO
PCIE_JTAG_TMS
PCIE_REFCLK_P
PCIE_REFCLK_N
PCIE_REFCLK_P
PCIE_REFCLK_N
PCIE_PERSTn
PCIE_PERSTn
PCIE_PERSTn 5
6
6
D
PCIE_REFCLK_P
PCIE_REFCLK_N
PCIE_TX_CP
PCIE_TX_CN
0.1uF
0.1uF
C220
C219
PCIE_TX_P
PCIE_TX_N
PCIE_Bracket_X1
C
C
12V_PCIE
3.3V_PCIE
B1
C73
10uF
C72
10uF
C74
C75
0.1uF
C76
0.1uF
C77
0.1uF
C78
0.1uF
C79
0.1uF
10uF
C80
0.1uF
C81
0.1uF
C82
0.1uF
PCI BRACKET
B
B
A
A
Altera Corporation, 9330 Scranton Rd, San Diego, CA 92121
Copyright (c) 2009 Altera Corporation. All Rights Reserved.
Title
Cyclone IV GX FPGA Development Kit Board
Size
B
Date:
8
7
6
5
4
3
Document Number
Rev
150-0311002-B1 (6XX-42746R)
Friday, July 16, 2010
2
Sheet
B
8
of
1
15
8
7
6
5
4
3
2
1
SRAM & FLASH
FSM BUS
FSML_D[15:0]
FLASH & SRAM INTERFACE
FSML_A[23:0]
FSML_D[15:0]
FSML_D[15:0]
4,10,11
FSML_A1
FSML_A2
FSML_A3
FSML_A4
FSML_A5
FSML_A6
FSML_A7
FSML_A8
FSML_A9
FSML_A10
FSML_A11
FSML_A12
FSML_A13
FSML_A14
FSML_A15
FSML_A16
FSML_A17
FSML_A18
FSML_A19
FSML_A20
37
36
32
33
34
35
42
43
44
45
46
47
48
49
50
80
81
82
99
100
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
SRAM_CLK
89
CLK
FSML_OEn
SRAM_CEn
SRAM_CE2
SRAM_CE3n
SRAM_MODE
86
98
97
92
31
OE_n
CE1_n
CE2
CE3_n
MODE
SRAM_BWan
SRAM_BWbn
FSML_WEn
93
94
87
BWA_n
BWB_n
BWE_n
D
2.5V
R132
R133
R134
R100
10.0K
10.0K
10.0K
10.0K
C
2.5V
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
15
41
65
91
VDD
VDD
VDD
VDD
U12
4
11
20
27
54
61
70
77
2.5V
E
IS61VPS102418A-250TQL
SSRAM
10.0K
SRAM_GWn
88
GW_n
R126
R136
R127
R118
10.0K
10.0K
10.0K
10.0K
SRAM_ADSCn
SRAM_ADSPn
SRAM_ADVn
SRAM_ZZ
85
84
83
64
ADSC_n
ADSP_n
ADV_n
ZZ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
58
59
62
63
68
69
72
73
8
9
12
13
18
19
22
23
DQPA
DQPB
74
24
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
NC19
NC20
NC21
NC22
NC23
NC24
1
2
3
6
7
14
16
25
28
29
30
38
39
51
52
53
56
57
66
75
78
79
95
96
FSML_D0
FSML_D1
FSML_D2
FSML_D3
FSML_D4
FSML_D5
FSML_D6
FSML_D7
FSML_D8
FSML_D9
FSML_D10
FSML_D11
FSML_D12
FSML_D13
FSML_D14
FSML_D15
U11
2.5V
JS28FxxxP33BF
FLASH
FSML_A1
FSML_A2
FSML_A3
FSML_A4
FSML_A5
FSML_A6
FSML_A7
FSML_A8
FSML_A9
FSML_A10
FSML_A11
FSML_A12
FSML_A13
FSML_A14
FSML_A15
FSML_A16
FSML_A17
FSML_A18
FSML_A19
FSML_A20
FSML_A21
FSML_A22
FSML_A23
29
25
24
23
22
21
20
19
8
7
6
5
4
3
2
1
55
18
17
16
11
10
9
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22(64M)
NC/A23(128M)
45
CLK
VPP
43
VCC
33
VCCQ
38
D0
D1
D2
D3
D4
D5
D6
D7
34
36
39
41
47
49
51
53
FSML_D0
FSML_D1
FSML_D2
FSML_D3
FSML_D4
FSML_D5
FSML_D6
FSML_D7
D8
D9
D10
D11
D12
D13
D14
D15
35
37
40
42
48
50
52
54
FSML_D8
FSML_D9
FSML_D10
FSML_D11
FSML_D12
FSML_D13
FSML_D14
FSML_D15
WAIT
56
VSS
VSS
VSS
12
28
31
RFU0
RFU1
RFU2
13
26
27
2.5V
FSML_A21
R137
R138
10.0KFLASH_RESETn
10.0KFLASH_CEn
FSML_OEn
FSML_WEn
R103
10.0KFLASH_WPn
44
30
32
14
46
15
RESET#
CE#
OE#
WE#
ADV#
WP#
FSML_A[23:0] 4,10,11
SRAM_BWan
SRAM_BWbn
FSML_WEn
FSML_OEn
SRAM_CEn
SRAM_ADSCn
SRAM_ADSPn
SRAM_ADVn
SRAM_CLK
FLASH_CEn
SRAM_BWan 4,11
SRAM_BWbn 4,11
FSML_WEn 4,11
FSML_OEn 4,11
SRAM_CEn 4,11
SRAM_ADSCn 11
SRAM_ADSPn 11
SRAM_ADVn 11
SRAM_CLK 4,11
FLASH_CEn 4,11
E
D
C
Flash, JS28FxxxP33BF
5
10
17
21
26
40
55
60
67
71
76
90
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
R135
FLASH 128Mb (8M X 16)
FSML_A[23:0]
B
SRAM, IS61VPS102418A-250TQL
B
2.5V
2.5V
C69
C53
C209
C201
C178
C207
C160
C159
C158
C200
C208
C184
C210
C213
C137
C161
C162
C212
C211
C214
10uF
10uF
0.1uF
0.1uF
0.1uF
0.1uF
4.7nF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
10uF
0.1uF
10uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
A
A
Altera Corporation, 9330 Scranton Rd, San Diego, CA 92121
Copyright (c) 2009 Altera Corporation. All Rights Reserved.
Title
Cyclone IV GX FPGA Development Kit Board
Size
B
Date:
8
7
6
5
4
3
Document Number
Rev
150-0311002-B1 (6XX-42746R)
Wednesday, March 03, 2010
2
Sheet
B
9
of
1
15
8
7
6
5
3
2
1
User IO & Power Monitor
Low Side
2.5_VCC
V4
1
High Side
RSNS SNS
2
2x16 LED DISPLAY INTERFACE
SENSE_PAD
V3
2.5_VCC_TP
1
E
RSNS SNS
FSML_D[15:0]
2
5.35V_MONITOR
1
RSNS SNS
A/D #0
2
SENSE_PAD
V9
1.2_VCCL_GXB_TP
1
RSNS SNS
1
RSNS SNS
2
2
1
RSNS SNS
2
SENSE_PAD
V8
2.5_VCCIO
1
RSNS SNS
2
SENSE_PAD
V7
2.5V
1
RSNS SNS
2
VCC_P
VCC_N
21
22
CH0
CH1
VCCLGXB_P
VCCLGXB_N
23
24
CH2
CH3
VCCGXB_P
VCCGXB_N
25
26
CH4
CH5
VCCIO_P
VCCIO_N
27
28
CH6
CH7
1.2_VCCINT
1
RSNS SNS
1
RSNS SNS
1
RSNS SNS
11
REF-
12
F0
19
SDO
SDI
SCK
CSn
17
20
18
16
3
4
CH10
CH11
5
6
CH12
CH13
7
8
CH14
CH15
NC1
NC2
13
14
10
COM
GND
15
2
1
RSNS SNS
LCD_CSn
LCD_CSn 4
E
0
0
10uF
DNI
SENSE5_REF_P
REF=5.35V
SENSE5_REF_N
R111
R109
R110
R112
SENSE5_SDO
SENSE5_SDI
SENSE5_SCK
SENSE5_CSn
2.5V
10.0K
10.0K
10.0K
10.0K
CPU_RESETn
CPU_RESETn 3
USER_PB[1..0]
USER_PB[1..0]
PGM_SEL
PGM_SEL 11
PGM_CONFIG
PGM_CONFIG 11
MAX_RESETn
MAX_RESETn 11
5
5.0V
U20
14
13
12
11
10
9
8
R113
10.0K
MAX3378_TS
LTC2418
VCC
IO VCC1
IO VCC2
IO VCC3
IO VCC4
NC2
/TS
D
LED INTERFACE
VL
IO VL1
IO VL2
IO VL3
IO VL4
NC1
GND
1
2
3
4
5
6
7
USER_LED[3..0]
USER_LED[3..0]
2.5V
PGM_LED[1..0]
PGM_LED[1..0]
SENSE_SDO
SENSE_SDI
SENSE_SCK
SENSE_CSn
MAX_ERROR
MAX_ERROR 11
CONF_DONE_LED
CONF_DONE_LED
MAX3378
3,4
11
11
POWER MONITOR INTERFACE
SENSE_SDO
SENSE_SDI
SENSE_SCK
SENSE_CSn
SENSE_SDO
SENSE_SDI
SENSE_SCK
SENSE_CSn
2
SENSE_PAD
V2
1.2_VCCD_PLL_TP
FSML_A[23:0] 4,9,11
5.0V
VCCDPLL_P
VCCDPLL_N
SENSE_PAD
V1
1.2_VCCD_PLL
REF+
CH8
CH9
SENSE_PAD
V6
1.2V
9
1
2
2
FSML_A[23:0]
PUSH BUTTON INTERFACE
VCC
VCCINT_P
VCCINT_N
SENSE_PAD
V5
FSML_D[15:0] 4,9,11
R130
C215
0.1uF
SENSE_PAD
V10
2.5_VCC_GXB_TP
C204
R129
U19
SENSE_PAD
V12
2.5_VCC_GXB
D
R128
SENSE_PAD
V11
1.2_VCCL_GXB
C
4
11
11
11
11
C
2
SENSE_PAD
2 x 16 Display Connector
5.0V
J6
2.5V
FSML_A0
FSML_D0
FSML_D2
FSML_D4
FSML_D6
D8
USER_LED0
56.2
RESn_LED1 R9
56.2
2.5V
Green_LED
D7
CPU_RESETn
RESn_LED2 R8
56.2
S6
56.2
R71
10.0K
PGM_SEL
R14
10.0K
PGM_CONFIG
R13
10.0K
MAX_RESETn
R73
10.0K
3
2
1
Copyright (c) 2009 Altera Corporation. All Rights Reserved.
Title
Cyclone IV GX FPGA Development Kit Board
RES_PGM_LED1
R5
56.2
Size
B
Green_LED
Date:
8
A
Altera Corporation, 9330 Scranton Rd, San Diego, CA 92121
Green_LED
D3
PGM_LED1
B
3
R6
USER_PB1
4
RES_PGM_LED0
1
PGM_LED0
2
56.2
10.0K
4
R4
1
RES_CONF_DONE
4
S3
Green_LED
D4
A
4
1
100, 1%
RED_LED
D2
CONF_DONE_LED
FSML_A1
LCD_CSn
FSML_D1
FSML_D3
FSML_D5
FSML_D7
2x16 LCD
S1
RES_MAX_ERROR R3
R69
3
2
4
S2
1
56.2
Green_LED
D1
MAX_ERROR
2
4
6
8
10
12
14
3
2
4
1
RESn_LED3 R7
USER_LED3
2
4
6
8
10
12
14
B2
S5
Green_LED
D5
USER_PB0
3
USER_LED2
10.0K
1
3
5
7
9
11
13
2X7
2
S4
SW-Button
Green_LED
D6
R72
3
USER_LED1
2
B
RESn_LED0 R10
1
3
5
7
9
11
13
7
6
5
4
3
Document Number
Rev
150-0311002-B1 (6XX-42746R)
Wednesday, March 03, 2010
2
Sheet
B
10
of
1
15
8
7
6
5
4
3
2
1
EPM2210 System Controller
U10A
SRAM_BWan
E
SRAM_BWbn
SRAM_CEn
SRAM_ADSCn
SRAM_ADSPn
SRAM_ADVn
SRAM_CLK
D
CLK_MAXII
U10B
MAX II
BANK1
D3
C2
E3
C3
E4
D2
E5
D1
IOB1_1
IOB1_2
IOB1_3
IOB1_4
IOB1_5
IOB1_6
IOB1_7
IOB1_8
IOB1_25
IOB1_26
IOB1_27
IOB1_28
IOB1_29
IOB1_30
IOB1_31
IOB1_32
H3
J1
H4
J2
J4
K1
J3
K2
F3
E2
F4
E1
F5
F2
F6
F1
IOB1_9
IOB1_10
IOB1_11
IOB1_12
IOB1_13
IOB1_14
IOB1_15
IOB1_16
IOB1_34
IOB1_35
IOB1_36
IOB1_37
IOB1_38
IOB1_39
IOB1_40
L1
K5
L2
K4
M1
K3
M2
G3
G2
G4
G1
G5
H2
IOB1_17
IOB1_18
IOB1_19
IOB1_20
IOB1_21
IOB1_22
H1
IOB1_24
IOB1_41
IOB1_42
IOB1_43
IOB1_44
IOB1_45
IOB1_46
IOB1_47
IOB1_48
L5
M3
L4
N1
L3
N2
M4
N3
IOB1_49
P2
TCK
TDI
TDO
TMS
P3
L6
M5
N4
H5
J5
IOB1/GCLK0
IOB1/GCLK1
SENSE_SCK
FPGA_MSEL0
SENSE_SDI
FPGA_MSEL1
SENSE_SDO
SENSE_CSn
FPGA_MSEL2
EPCS_nCS
FPGA_DCLK
FPGA_nSTATUS
FPGA_nCONFIG
FPGA_CONF_DONE
FPGA_CONFIG_D0
IOB2_50
IOB2_51
IOB2_52
IOB2_53
IOB2_54
IOB2_55
IOB2_56
IOB2_57
IOB2_74
IOB2_75
IOB2_76
IOB2_77
IOB2_78
IOB2_79
IOB2_80
IOB2_81
E9
A9
A8
B8
E8
A7
D8
B7
D11
A13
E11
B12
C10
A12
D10
B11
IOB2_58
IOB2_59
IOB2_60
IOB2_61
IOB2_62
IOB2_63
IOB2_64
IOB2_65
IOB2_82
IOB2_83
C8
A6
FSML_D5
FSML_D6
IOB2_85
IOB2_86
IOB2_87
IOB2_88
IOB2_89
B6
E7
A5
D7
B5
FSML_D7
E10
A11
IOB2_66
IOB2_67
B10
C9
A10
D9
B9
IOB2_69
IOB2_70
IOB2_71
IOB2_72
IOB2_73
IOB2_90
IOB2_91
IOB2_92
IOB2_93
IOB2_94
IOB2_95
IOB2_96
IOB2_97
IOB2_98
IOB2_99
IOB2_100
IOB2_101
IOB2_102
JTAG_TCK
JTAG_FPGA_TDO
JTAG_EPM2210_TDO
JTAG_TMS
FSML_A2
FSML_A3
FSML_A4
FSML_A5
FSML_A6
FSML_A7
B
FSML_A8
FSML_A9
FSML_A10
FSML_D3
FSML_D[15:0]
FSML_D[15:0] 4,9,10
FSML_A[23:0]
FSML_A[23:0] 4,9,10
E
FLASH INTERFACE
FSML_D4
FSML_WEn
FLASH_CEn
FSML_OEn
FSML_WEn 4,9
FLASH_CEn 4,9
FSML_OEn 4,9
SRAM INTERFACE
FSML_D8
SRAM_BWan
SRAM_BWbn
SRAM_BWan 4,9
SRAM_BWbn 4,9
FSML_D9
SRAM_CEn
SRAM_CEn 4,9
C7
A4
E6
B4
D6
C4
C6
B3
FSML_D10
FSML_D11
SRAM_ADSCn
SRAM_ADSPn
SRAM_ADVn
SRAM_CLK
SRAM_ADSCn 9
SRAM_ADSPn 9
SRAM_ADVn 9
SRAM_CLK 4,9
C5
A2
D5
B1
D4
FSML_WEn
FLASH_CEn
FSML_D12
D
FSML_D13
FSML_D14
FSML_D15
FPGA CONFIGURATION
FPGA_DCLK 3
FPGA_nSTATUS 3
FPGA_nCONFIG 3
FPGA_CONF_DONE 3
FPGA_CONFIG_D0 3
EPCS_nCS 3,4
FPGA_DCLK
FPGA_nSTATUS
FPGA_nCONFIG
FPGA_CONF_DONE
FPGA_CONFIG_D0
EPCS_nCS
FSML_OEn
FPGA_MSEL[2..0]
3
EPM2210_F256FBGA
U10D
MAX II
BANK3
FSML_A11
P14
N13
P15
M14
N14
M13
N15
L14
IOB3_103
IOB3_104
IOB3_105
IOB3_106
IOB3_107
IOB3_108
IOB3_109
IOB3_110
IOB3_127
IOB3_128
IOB3_129
IOB3_130
IOB3_131
IOB3_132
IOB3_133
IOB3_134
J16
J13
H16
H13
H15
H14
G16
G12
N16
L13
M15
L12
M16
L11
L15
K14
IOB3_111
IOB3_112
IOB3_113
IOB3_114
IOB3_115
IOB3_116
IOB3_117
IOB3_118
IOB3_135
G15 FSML_A15
IOB3_137
IOB3_138
IOB3_139
IOB3_140
IOB3_141
IOB3_142
F16 FSML_A16
G13
F15 FSML_A17
G14
E16 FSML_A18
F11
L16
K13
K15
K12
K16
IOB3_119
IOB3_120
IOB3_121
IOB3_122
IOB3_123
J15
J14
IOB3_125
IOB3_126
IOB3_143
IOB3_144
IOB3_145
IOB3_146
IOB3_147
IOB3_148
IOB3_149
IOB3_150
E15 FSML_A19
F12
D16 FSML_A20
F13
D15 FSML_A21
F14
D14
E12
IOB3/GCLK2
IOB3/GCLK3
IOB3_151
IOB3_152
IOB3_153
IOB3_154
IOB3_155
C15 FSML_A22
E13
C14 FSML_A23
E14
D13
J12
H12
FSML_D0
FSML_D1
FSML_D2
FPGA_MSEL[2..0]
U10C
FSML_A1
SHARED BUS
C13
B16
C12
A15
D12
B14
C11
B13
EPM2210_F256FBGA
C
MAX II
BANK2
CLK125_EN
FSML_A12
CLK125_SDA
FSML_A13
CLK125_SCK
FSML_A14
CLK_SEL
MAX_RESETn
MAX II
BANK4
P4
R1
P5
T2
N5
R3
P6
R4
IOB4_156
IOB4_157
IOB4_158
IOB4_159
IOB4_160
IOB4_161
IOB4_162
IOB4_163
IOB4_180
IOB4_181
IOB4_182
IOB4_183
IOB4_184
IOB4_185
N9
T8
T9
R9
P9
T10
MAX_ERROR
PGM_LED0
PGM_LED1
USER_PGM
PGM_SEL
IOB4_187
R10
PGM_CONFIG
N6
T4
M6
R5
P7
T5
N7
R6
IOB4_164
IOB4_165
IOB4_166
IOB4_167
IOB4_168
IOB4_169
IOB4_170
IOB4_171
IOB4_188
IOB4_189
IOB4_190
IOB4_191
IOB4_192
IOB4_193
IOB4_194
IOB4_195
M10
T11
N10
R11
P10
T12
M11
R12
M7
T6
IOB4_172
IOB4_173
R7
P8
T7
N8
R8
IOB4_175
IOB4_176
IOB4_177
IOB4_178
IOB4_179
IOB4_196
IOB4_197
IOB4_198
IOB4_199
IOB4_200
IOB4_201
IOB4_202
IOB4_203
N11
T13
P11
R13
M12
R14
N12
T15
M9
M8
IOB4_204
IOB4/DEV_CLRn IOB4_205
IOB4/DEV_OE
IOB4_206
P12
R16
P13
EPM2210_F256FBGA
MAX II USER INTERFACE
U10E
EPM2210_F256FBGA
CONF_DONE_LED
MAX_CSn
2.5V
MAX II
Power
H7
H9
J8
J10
G6
F7
K11
L10
GNDINT
GNDINT
GNDINT
GNDINT
GNDINT
GNDINT
GNDINT
GNDINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
H8
H10
J7
J9
K6
L7
G11
F10
A1
A16
B2
B15
G7
G8
G9
G10
K7
K8
K9
K10
R2
R15
T1
T16
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
VCCIO1
VCCIO1
VCCIO1
VCCIO1
C1
H6
J6
P1
VCCIO2
VCCIO2
VCCIO2
VCCIO2
A3
A14
F8
F9
VCCIO3
VCCIO3
VCCIO3
VCCIO3
C16
H11
J11
P16
VCCIO4
VCCIO4
VCCIO4
VCCIO4
L8
L9
T3
T14
MAX_ERROR
CONF_DONE_LED
PGM_SEL
PGM_CONFIG
MAX_RESETn
USER_PGM
MAX_CSn
MAX_ERROR 10
CONF_DONE_LED 10
PGM_SEL 10
PGM_CONFIG 10
MAX_RESETn 10
USER_PGM 3
MAX_CSn 4
PGM_LED[1..0]
PGM_LED[1..0]
C
10
CURRENT & TEMP SENSE INTERFACES
SENSE_SCK
SENSE_SDI
SENSE_SDO
SENSE_CSn
SENSE_SCK 10
SENSE_SDI 10
SENSE_SDO 10
SENSE_CSn 10
MAX II JTAG
JTAG_TCK
JTAG_FPGA_TDO
JTAG_EPM2210_TDO
JTAG_TMS
JTAG_TCK 3,12
JTAG_FPGA_TDO 3
JTAG_EPM2210_TDO 3
JTAG_TMS 3,12
B
CLOCK
CLK125_EN 5
CLK125_SDA 5
CLK125_SCK 5
CLK_MAXII 5
CLK_SEL 3,5
CLK125_EN
CLK125_SDA
CLK125_SCK
CLK_MAXII
CLK_SEL
EPM2210_F256FBGA
Place near MAX II
2.5V
A
A
Altera Corporation, 9330 Scranton Rd, San Diego, CA 92121
Copyright (c) 2009 Altera Corporation. All Rights Reserved.
C147
C218
C185
C186
C165
C216
C148
C202
C217
C187
C179
C163
C164
C188
10uF
10uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
Title
Cyclone IV GX FPGA Development Kit Board
Size
B
Date:
8
7
6
5
4
3
Document Number
Rev
150-0311002-B1 (6XX-42746R)
Wednesday, March 03, 2010
2
Sheet
B
11
of
1
15
8
7
6
5
4
3
2
Embedded USB Blaster
1
2.5V_USB
U4A
5V_USB
L3
USB
USB_CON_5V
USB_RXFn
5V_USB
J5
USB TYPE-B
BLM21PG331SN1
C35
R87
470
10uF
1
2
3
4
6
C144
6
3V3OUT
27
27
USB_DM
USB_DP
8
7
USBDM
USBDP
R95
1.5K
5
RSTOUT#
USB_RSTn
SN65220DBV
D
USB_XTAL1
USB_XTAL2
5V_USB
R92
18pF
USB_RESETn
USB_EECS
USB_EESK
EEDATA
USB_XTAL1
XTIN
XTOUT
4
RESET#
32
1
2
EECS
EESK
EEDATA
31
TEST
2
C6
10.0K
27
28
18pF
9
17
C5
1
X3
CRYSTAL, 6MHz, SMD
USB_XTAL2
13
3
26
VCC-IO
USB_3V3
VCC1
VCC2
U5
AGND
R39
R38
USB_DM_R
USB_DP_R
6
4
5
NC1
A
NC2
B
GNDGND
30
0.1uF
29
C145
33nF
AVCC
5
C124
U7
1
3
2
0.1uF
USB_AVCC
GND1
GND2
E
2.5V_USB
D0
D1
D2
D3
D4
D5
D6
D7
25
24
23
22
21
20
19
18
USB_D0
USB_D1
USB_D2
USB_D3
USB_D4
USB_D5
USB_D6
USB_D7
RD#
WR
16
15
USB_RDn
USB_WR
TXE#
RXF#
14
12
USB_TXEn
USB_RXFn
SI/WU
PWREN#
11
10
USB_SI_WU
USB_PWR_ENn
FT245BL
C
2.5V_USB
U16
DECOUPLING CAPS
C36
C134
1
2
3
4
C123
CS
SK
DIN
DOUT
VCC
NC1
NC2
GND
8
7
6
5
0.1uF
0.1uF
R40
J7
K10
K3
K4
K5
K6
K7
K9
F3
G1
G2
H1
H2
H3
J5
J6
IOB1_9
IOB1_10
IOB1_11
IOB1_12
IOB1_13
IOB1_14
IOB1_15
IOB1_16
IOB1_25
IOB1_26
IOB1_27
IOB1_28
IOB1_29
IOB1_30
IOB1_31
IOB1_32
L1
L10
L11
L2
L3
L4
L5
L6
IOB1_33
IOB1_34
L7
L9
JTAG_TCK
TCK
TDI
TDO
TMS
K1
J2
K2
J1
USB_MAX_TCK
USB_MAX_TDI
USB_MAX_TDO
USB_MAX_TMS
USB_RESETn
K8
L8
IOB1/DEV_CLRn
IOB1/DEV_OE
2.5V_USB
E
D13
Green_LED
USB BLASTER INTERFACE
JTAG_BLASTER_TDO
JTAG_TCK
JTAG_TMS
JTAG_BLASTER_TDI
JTAG_BLASTER_TDO
USB_SI_WU
USB_LED
USB_DISABLEn
JTAG_TCK 3,11
JTAG_TMS 3,11
JTAG_BLASTER_TDI 3
JTAG_BLASTER_TDO 3
USB_DISABLEn
USB_DISABLEn
3
D
U4B
USB_TXEn
USB_D1
USB_D0
USB_WR
USB_RDn
USB_D7
USB_D6
USB_D5
A1
A10
A11
A2
A3
A4
A5
A6
USB_D4
USB_D3
USB_D2
A7
A8
A9
B10
B11
B2
B3
B4
MAX II
BANK2
IOB2_51
IOB2_52
IOB2_53
IOB2_54
IOB2_55
IOB2_56
IOB2_57
IOB2_58
B5
B6
B7
B8
B9
C10
C11
C5
IOB2_43
IOB2_44
IOB2_45
IOB2_46
IOB2_47
IOB2_48
IOB2_49
IOB2_50
IOB2_59
IOB2_60
IOB2_61
IOB2_62
IOB2_63
IOB2_64
IOB2_65
IOB2_66
C6
C7
D10
D11
D9
E10
E11
F11
IOB2/CLK2
IOB2/CLK3
IOB2_67
IOB2_68
IOB2_69
IOB2_70
IOB2_71
IOB2_72
IOB2_73
IOB2_74
F9
G10
H10
H11
H9
J10
J11
K11
IOB2_35
IOB2_36
IOB2_37
IOB2_38
IOB2_39
IOB2_40
IOB2_41
IOB2_42
10.0K
F10
G11
B
RES_USB_LED
EPM240M100
R88
2.2K
USB_EEDATA
IOB1_17
IOB1_18
IOB1_19
IOB1_20
IOB1_21
IOB1_22
IOB1_23
IOB1_24
IOB1/CLK0
IOB1/CLK1
AT93C46DN-SH-B
10uF
IOB1_1
IOB1_2
IOB1_3
IOB1_4
IOB1_5
IOB1_6
IOB1_7
IOB1_8
F2
E1
5V_USB
5V_USB
B1
C1
C2
D1
D2
D3
E2
F1
CLKIN_24MHZ
R94
1.00k
R37
56.2
MAX II
BANK1
5V_USB
2.5V_USB
C
USB_PWR_ENn
USB_EECS
USB_EESK
EEDATA
JTAG_TMS
JTAG_BLASTER_TDI
B
EPM240M100
X2
C3
0.01uF
1
EN
VCC
4
2
GND
OUT
3
U4C
CLKIN_24MHZ
24MHz
C4
0.01uF
10uF
D5
D7
E4
E8
G4
G8
H5
H7
2.5V_USB
2.5V_USB
2.5V_USB
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
J13
R68
A
R67
1.00K USB_MAX_TCK
USB_MAX_TDO
1.00K USB_MAX_TMS
USB_MAX_TDI
1
3
5
7
9
1
3
5
7
9
2
4
6
8
10
2
4
6
8
10
USB_JTAG_PW
0
R80
2.5V_USB
PLACE NEAR MAX II
MAX II
Power
C146
VCCINT
VCCINT
E9
G3
VCCIO1
VCCIO1
VCCIO1
E3
J4
J8
VCCIO2
VCCIO2
VCCIO2
C4
C8
G9
C101
C102
C125
C110
C111
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
EPM240M100
Copyright (c) 2009 Altera Corporation. All Rights Reserved.
USB_JTAG_GND
0
R79
Title
Cyclone IV GX FPGA Development Kit Board
DNI
Size
B
Date:
8
7
A
Altera Corporation, 9330 Scranton Rd, San Diego, CA 92121
6
5
4
3
Document Number
Rev
150-0311002-B1 (6XX-42746R)
Wednesday, March 03, 2010
2
Sheet
B
12
of
1
15
8
7
6
5
4
3
2
1
Power - 2.5V and 1.2V Output
9V - 16V
DC Input
E
D9
MBRS340
12V_PCIE
2
DC_INPUT
J4
CONN JACK PWR
2
1
3
D19
DC_J 2
CONDITION
1
DC INPUT = ON
U2
FDS6575
1
FM540
DC_MAIN
PCIE = OFF
C1
12V_PCIE
R1
10.0K
CTL
R2
10.0K
D
8
7
6
5
1
2
3
10uF
U1
VIN
GND
CTL
C25
C24
C23
47uf
10uF
0.1uF
0.1uF
SENSE
GATE
STAT
6
5
4
E
- CTL of LTC4412 go LOW and TURN ON the MOSFET, DC INPUT
flow through to DC MAIN.
- D9 MBRS340 used to prevent DC MAIN flow back to 12V PCIE
4
LTC4412
1
2
3
C22
DESCRIPTION
DC INPUT = OFF
GATE
PCIE = ON
OR
Power Controller, LTC4412
DC INPUT = ON
PCIE = ON
- Logical HIGH on CTL forces the gate to source voltage of the
primary P-channel MOSFET power switch to a small voltage
(VGOFF).
- This will turn the MOSFET off and no current will flow from the
primary power input at VIN if the MOSFET is configured so that the
drain to source diode does not forward bias.
D
- VGS of MOSFET go HIGH and disable the junction. DC INPUT will be
blocked while 12V PCIE flow through DC MAIN
DC_MAIN
LT3510_SHDn
5.0V
1.2V
D20
C112
0.003
C91
C86
10uF
1.2_VCCL_GXB
R82
10uF
0.003
C93
0.1uF
L2
4.7uH
10.0KPG1
FB1
VC1
SS
17
18
19
4.02K
1
C103
C39
R29
8.06k
1.2_VCCD_PLL
R65
1.2_VCCD_PLL_TP
0.003
D11
MBRS340
VIN1
SHDN
BST1
LT3510
SW1
IND1
VOUT1
PG1
FB1
VC1
SS/TRACK1
VIN2
RT/SYNC
BST2
SW2
IND2
VOUT2
PG2
FB2
VC2
SS/TRACK2
10
16
11
1000PF
VC1_C
21
GND
R31
BLM21PG331SN1
L4
LT3510_SHDn 14
2.5_VCCIO
C
0.003
R28
120k
5.0V
C92
10uF
RT
BST2
9
8
7
6
SW2
IND2 1
14
13
12
FB2
VC2
L1
8.2uH
R36
1.00k
C94
0.1uF
2.5_VCC_GXB_TP
2
PG2 R11
2.5_VCC_GXB
BLUE_PU
10.0K
L7
R26
1000PF
VC2_C
R25
BLM21PG331SN1
R83
0.003
D12
BLUE LED
16.9k
C104
R27
D10
MBRS340
C38
Regulator, LT3510
2
B
SW1
IND1
1
15
20
2
3
4
5
2
R12
10uF
0.1uF
U3
1
R30
0.1uF
R75
LT3510_SHDn
BST1
BLM21PG331SN1
L6
10uF
1
BAT54AW
1.2_VCCL_GXB_TP
10uF
2.5V
2
10uF
C13
1
R74
C14
2
C
C15
3
1.2_VCCINT
C12
10uF
B
8.06k
2.5_VCC_TP
2.5_VCC
C34
L5
24.9k
BLM21PG331SN1
R66
0.003
24.9k
0.1uF
C83
C85
C84
C89
C87
C88
C90
10uF
10uF
10uF
10uF
10uF
10uF
10uF
A
A
Altera Corporation, 9330 Scranton Rd, San Diego, CA 92121
Copyright (c) 2009 Altera Corporation. All Rights Reserved.
Title
Cyclone IV GX FPGA Development Kit Board
Size
B
Date:
8
7
6
5
4
3
Document Number
Rev
150-0311002-B1 (6XX-42746R)
Wednesday, March 03, 2010
2
Sheet
B
13
of
1
15
5
4
3
2
1
Power - 5.0V, 5.35V, 3.3V and 2.5V Output
D
D
DC_MAIN
5.0V
U21
8
7
9
C199
10uF
LT3023
IN
OUT1
SHDN1n
SHDN2n
BYP1
ADJ1
OUT2
3
11
C
LT3510_SHDn
7
1
8
9
2
3
10
4
11
12
5
6
GND
GND
BYP2
ADJ2
6
R125
768k
C203
5
4
5V_BYP1
5V_ADJ1
C206
LT3510_SHDn 13
LT3510_SHDn
0.01uF
10uF
5.35V_MONITOR
10
C183
1
2
5V_BYP2
5V_ADJ2
C177
R117
845k
0.01uF
Regulator, LT3023
R122
249k
LTREG_SHDn
10uF
R123
249k
C
DC_MAIN
SW1
SW SLIDE-4P2T
DC_MAIN
3.3V
U17
8
7
C157
LT3027
IN1
SHDN1n
5V_USB
10uF
9
3
C136
B
IN2
SHDN2n
10uF
11
GND
OUT1
6
BYP1
ADJ1
5
4
OUT2
10
BYP2
ADJ2
C156
R99
422k
C171
3V3_BYP1 0.01uF
3V3_ADJ1
10uF
2.5V_USB
C135
1
2
2V5_BYP2 0.01uF
2V5_ADJ2
C126
R96
261k
R97
249k
Regulator, LT3027
B
10uF
R98
249k
A
A
Altera Corporation, 9330 Scranton Rd, San Diego, CA 92121
Copyright (c) 2009 Altera Corporation. All Rights Reserved.
Title
Cyclone IV GX FPGA Development Kit Board
Size
B
Date:
5
4
3
2
Document Number
Rev
150-0311002-B1 (6XX-42746R)
Wednesday, March 03, 2010
Sheet
1
14
B
of
15
8
7
6
5
4
3
2
1
Cyclone IV GX Decoupling
Cyclone IV GX VCCINT
E
E
1.2_VCCINT
C30
C26
C99
C96
C31
C122
C116
C121
C17
C19
C192
C196
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
C193
C117
C105
C28
C18
C195
C106
C108
C107
C97
C98
C194
C191
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
22nF
22nF
22nF
22nF
22nF
22nF
0.047uF 0.047uF 0.047uF 0.047uF 0.047uF 0.047uF
C20
C16
C119
C198
C27
C29
C190
C95
C65
C9
C7
C8
C66
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.47uF
0.47uF
10uF
10uF
10uF
10uF
10uF
C197
C118
C120
C100
C109
D
D
Cyclone IV GX VCCL GXB
Cyclone IV GX VCCD PLL
1.2_VCCL_GXB
1.2_VCCD_PLL
C167
C151
C141
C152
C142
C150
C166
C189
C153
C181
C155
C168
C180
2.2nF
4.7nF
0.01uF
22nF
0.1uF
0.47uF
10uF
2.2nF
4.7nF
0.01uF
0.1uF
0.47uF
10uF
C
C
Cyclone IV GX VCCA PLL and VCC CLKIN
Cyclone IV GX VCCIO
2.5_VCCIO
2.5_VCC
C133
C143
C176
C175
2.2nF
0.01uF
0.047uF 0.47uF
C182
C174
C140
C131
C173
C154
C172
10uF
2.2nF
4.7nF
0.01uF
0.1uF
0.47uF
10uF
B
B
Cyclone IV GX VCCH & VCCA
2.5_VCC_GXB
C115
C114
C132
C130
C149
C139
2.2nF
4.7nF
0.01uF
22nF
0.047uF
10uF
SCREW1
SCREW3
STANDOFF1
SPACER1
SCREW2
SCREW4
STANDOFF2
SPACER2
SCREW5
STANDOFF3
STANDOFF4
A
A
Altera Corporation, 9330 Scranton Rd, San Diego, CA 92121
Copyright (c) 2009 Altera Corporation. All Rights Reserved.
Title
Cyclone IV GX FPGA Development Kit Board
Size
B
Date:
8
7
6
5
4
3
Document Number
Rev
150-0311002-B1 (6XX-42746R)
Wednesday, March 03, 2010
2
Sheet
B
15
of
1
15
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