DK-DEV-4SGX230N / DK-VIDEO-4SGX230N Dev Kit Schematic

8
7
6
5
4
NOTES:
E
3
REV
1. Project Drawing Numbers:
Raw PCB
Gerber Files
PCB Design Files
Assembly Drawing
Fab Drawing
Schematic Drawing
PCB Film
Bill of Materials
Schematic Design Files
Functional Specification
PCB Layout Guidelines
Assembly Rework
A
B
100-0310901-B1
110-0310901-B1
120-0310901-B1
130-0310901-B1
140-0310901-B1
150-0310901-B1
160-0310901-B1
170-0310901-B1
180-0310901-B1
210-0310901-B1
220-0310901-B1
320-0310901-B1
2
DATE
PAGES
12/15/2008
02/23/2009
All
All
1
DESCRIPTION
Rev A Release
Rev B Release. Added Temp Sense SPI bus to EPM2210. Added 100M XTL SMBus
to EPM2210 for Si570 support, Added fan LED, Changed 3.3V power mux to LTC4352
+ new FET, Added 125MHz XTL to EPM2210, Added LTM8021 switcher to support
VCCA_GXB increase to 3.3V, Changed FPGA VCC to 0.95V, swapped
HSMA_TX_D_N2 and HSMA_TX_D_N13 with updated FPGA symbol, Updated HDMI
symbol, Changed HSMC a/c coupling caps to 0-ohm resistors.
E
Stratix IV GX FPGA Development Kit Board
2. 1542 Parts, 78 Library Parts, 1214 Nets, 7307 Pins
PAGE
D
C
B
DESCRIPTION
1
Title, Notes, Block Diagram, Revision History
2
FPGA Package Top
3
PCI Express Edge Connector
4
Stratix IV GX Banks 1 & 2
5
Stratix IV GX Banks 3 & 4
6
Stratix IV GX Banks 5 & 6
7
Stratix IV GX Banks 7 & 8
8
Stratix IV GX Transceiver Banks
9
Stratix IV GX Clocks
10
Stratix IV GX Configuration & JTAG
11
HDMI & DDR3 Top Port
12
HSMC Port A & Port B
13
Ethernet PHY & RJ-45
14
QDRII SRAM Ports 0 & 1
15
DDR3 Bottom Port
16
Flash & SRAM
17
EPM2210 System Controller
18
User I/O (LEDs, Buttons, Switches, LCD)
19
EPM240 Embedded USB Blaster
20
SDI TX Cable Driver & SMB
21
Power 1 - DC Input, 12V, 3.3V
22
Power 2 - 0.95V & 5V
23
Power 3 - 2.5V, 1.8V, 1.5V
24
Power 4 - Linear Regulator
25
Power 5 - Power & Temp Monitor
26
Power 6 - Stratix IV GX Power
27
Decoupling 1
28
Decoupling 2
29
Decoupling 3
A
D
C
B
A
Altera Corporation, 9330 Scranton Rd, San Diego, CA 92121
Title
Copyright (c) 2009 Altera Corporation. All Rights Reserved.
Stratix IV GX FPGA Development Kit Board
Size
B
Date:
8
7
6
5
4
3
Document Number
Rev
150-0310901-B1 (6XX-41284R )
Friday, November 06, 2009
2
Sheet
1
B
of
1
29
8
7
6
Notes:
1.
E
2.
FPGA Schematic Symbol Breakdown:
(A) Banks 1A,1C
(B) Banks 2A,2C
(C) Banks 3A,3B,3C
(D) Banks 4A,4B,4C
(E) Banks 5A,5C
(F) Banks 6A,6C
(G) Banks 7A,7B,7C
(H) Banks 8A,8B,8C
(I) Clocks
(J) Configuration
(K) Power
(L) IO Power
(M) GND1
(N) GND2
(O) GND3
(P) Transceivers
(Q) Transceiver Power
5
4
FPGA Package Top View
HSMC Port A x8
REFCLK 156, 155, 148
1
HSMC Port B x2
SMB SDI TX
SMA x1 (TX-only)
Silicon
RIGHT EDGE
VCCIO = 2.5V
2
XCVR BANK QR2
XCVR BANKS QR0, QR1
BANK 5A, 5C
3
E
BANK 6A, 6C
VCCIO = 2.5V
HSMC Port A
HSMC Port B
Board can support the EP4SGX230 and EP4SGX530 devices and their hardcopy equivalents
D
DDR3 Bottom Port (512MB)
BANK 4A
BANK 7A
BANK 4B
BANK 7B
BANK 4C
BANK 7C
D
DDR3 Top Port (128MB)
QDR2 Top 1 Port (2MB)
VCCIO = 1.5V
VCCIO = 1.5V
Silicon
BOTTOM EDGE
Silicon
TOP EDGE
C
C
DDR3 Bottom Port (512MB)
BANK 3C
BANK 8C
BANK 3B
BANK 8B
DDR3 Top Port (128MB)
VCCIO = 1.5V
BANK 8A
QDR2 Top 0 Port (2MB)
VCCIO = 1.5V
HDMI Video Output
HDMI Transmitter
BANK 3A
VCCIO = 1.8V
B
B
BANK 2A, 2C
BANK 1C, 1A
Silicon
LEFT EDGE
VCCIO = 2.5V
FSM Bus Address
FSM Bus Control
Ethernet PHY
VCCIO = 2.5V
FSM Bus Data
Switches, Buttons, LEDs
MAX II Control
LCD
XCVR BANKS QL0, QL1
A
XCVR BANK QL2
PCI Express x8
PCIe REFCLK
HSMC Port B x4
Title
B
Date:
7
6
Copyright (c) 2009 Altera Corporation. All Rights Reserved.
Stratix IV GX FPGA Development Kit Board
Size
8
A
Altera Corporation, 9330 Scranton Rd, San Diego, CA 92121
5
4
3
Document Number
Rev
150-0310901-B1 (6XX-41284R )
Friday, November 06, 2009
2
Sheet
2
B
of
1
29
8
7
6
5
4
PCI Express Edge Connector
3
2
1
2.5V
E
E
R227
10.0K
12V_PCIE
PCIE_SMBCLK 4
PCIE_SMBDAT 4
R87
R88
PCIE_WAKEn 4
D
DNI 3.3V_PCIE_AUX
DNI PCIE_WAKEn_R
PCIE_PRSNT2n_x1
J17
+12V
PRSNT1_N
+12V
+12V
+12V
+12V
GND
GND
SMCLK
JTAG_TCK
SMDAT
JTAG_TDI
GND
JTAG_TDO
+3_3V
JTAG_TMS
JTAG_TRSTN
+3_3V
+3_3VAUX
+3_3V
WAKE_N
PERST_N
KEY
RSVD1
GND
X1
GND
REFCLK+
PET0P
REFCLKPET0N
GND
GND
PER0P
PRSNT2_N_X1
PER0N
GND
GND
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
PCIE_RX_P1 8
PCIE_RX_N1 8
PCIE_RX_P2 8
PCIE_RX_N2 8
PCIE_RX_P3 8
PCIE_RX_N3 8
PCIE_PRSNT2n_x4
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
PCIE_RX_P4 8
PCIE_RX_N4 8
PCIE_RX_P5 8
PCIE_RX_N5 8
PCIE_RX_P6 8
PCIE_RX_N6 8
PCIE_RX_P7 8
PCIE_RX_N7 8
B
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
PCIE_RX_P0 8
PCIE_RX_N0 8
C
12V_PCIE
PCIE_PRSNT2n_x8
PET1P
X4
PET1N
GND
GND
PET2P
PET2N
GND
GND
PET3P
PET3N
GND
RSVD3
PRSNT2_N_X4
GND
RSVD2
GND
PER1P
PER1N
GND
GND
PER2P
PER2N
GND
GND
PER3P
PER3N
GND
RSVD4
PET4P
X8
PET4N
GND
GND
PET5P
PET5N
GND
GND
PET6P
PET6N
GND
GND
PET7P
PET7N
GND
PRSNT2_N_X8
GND
RSVD5
GND
PER4P
PER4N
GND
GND
PER5P
PER5N
GND
GND
PER6P
PER6N
GND
GND
PER7P
PER7N
GND
3.3V_PCIE
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
PCIE_PRSNT1n
10
10
10
10
PCIE_JTAG_TCK
PCIE_JTAG_TDI
PCIE_JTAG_TDO
PCIE_JTAG_TMS
1
2
3
4
SW5
8
7
6
5
OPEN
3.3V_PCIE
PCIE_PRSNT2n_x1
PCIE_PRSNT2n_x4
PCIE_PRSNT2n_x8
MAX_EN
19
TDA04H0SB1
Link Width DIP Switch
4 PCIE_PERSTn
A12
A13
A14
A15
A16
A17
A18
D
8 PCIE_REFCLK_P
8 PCIE_REFCLK_N
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
PCIE_TX_CP0
PCIE_TX_CN0
0.1uF
0.1uF
C1117
C1116
8 PCIE_TX_P0
8 PCIE_TX_N0
PCIE_TX_CP1
PCIE_TX_CN1
0.1uF
0.1uF
C1115
C1114
8 PCIE_TX_P1
8 PCIE_TX_N1
PCIE_TX_CP2
PCIE_TX_CN2
0.1uF
0.1uF
C1113
C1112
8 PCIE_TX_P2
8 PCIE_TX_N2
PCIE_TX_CP3
PCIE_TX_CN3
0.1uF
0.1uF
C1111
C1110
8 PCIE_TX_P3
8 PCIE_TX_N3
PCIE_TX_CP4
PCIE_TX_CN4
0.1uF
0.1uF
C1109
C1108
8 PCIE_TX_P4
8 PCIE_TX_N4
PCIE_TX_CP5
PCIE_TX_CN5
0.1uF
0.1uF
C1107
C1106
8 PCIE_TX_P5
8 PCIE_TX_N5
PCIE_TX_CP6
PCIE_TX_CN6
0.1uF
0.1uF
C1105
C1104
8 PCIE_TX_P6
8 PCIE_TX_N6
PCIE_TX_CP7
PCIE_TX_CN7
0.1uF
0.1uF
C1103
C1102
8 PCIE_TX_P7
8 PCIE_TX_N7
C
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
B
PCIE_Slot
B5
A
12V_PCIE
C103
0.1uF
PCI BRACKET
3.3V_PCIE
C104
0.1uF
C105
0.1uF
C1120
0.1uF
C1121
0.1uF
C1118
0.1uF
C1119
0.1uF
C106
0.1uF
A
Altera Corporation, 9330 Scranton Rd, San Diego, CA 92121
Title
Copyright (c) 2009 Altera Corporation. All Rights Reserved.
Stratix IV GX FPGA Development Kit Board
Size
B
Date:
8
7
6
5
4
3
Document Number
Rev
150-0310901-B1 (6XX-41284R )
Friday, May 01, 2009
2
Sheet
3
B
of
1
29
8
7
6
5
4
3
Stratix IV Banks 1 and 2
2
1
FLASH & SRAM INTERFACE
16,17 FSM_D[31:0]
16,17 FSM_A[25:0]
U13A
E
D
C
FSM_D3
FSM_D2
FSM_D7
FSM_D6
FSM_D11
FSM_D10
FSM_D13
FSM_D12
K30
J30
N28
M28
J32
H32
C32
B32
FSM_D5
FSM_D4
FSM_D9
FSM_D8
D31
C31
D35
C35
FSM_D15
FSM_D14
FSM_D19
FSM_D18
FSM_D23
FSM_D22
FSM_D25
FSM_D24
N31
M31
N30
M30
N29
M29
F31
E31
FSM_D17
FSM_D16
FSM_D21
FSM_D20
D33
C33
H31
G31
FSM_D1
FSM_D0
D34
C34
USER_LED5
LCD_DATA3
PCIE_WAKEn
PCIE_SMBDAT
SRAM_DQP2
USER_LED8
LCD_DATA4
LCD_DATA6
M32
L32
P31
P32
N33
N34
T30
T31
USER_DIPSW2
SENSE_SDI
LCD_CSn
USER_DIPSW5
J34
J35
K34
K35
16 SRAM_BWn[3:0]
U13B
Stratix IV GX Bank 2
Stratix IV GX Bank 1
Bank 1A
DQ1L/DIFFIO_TX_L2p
DQ1L/DIFFIO_TX_L2n
DQ1L/DIFFIO_TX_L3p
DQ1L/DIFFIO_TX_L3n
DQ2L/DIFFIO_TX_L4p
DQ2L/DIFFIO_TX_L4n
DQ2L/DIFFIO_RX_L4p
DQ2L/DIFFIO_RX_L4n
DQ5L/DIFFIO_TX_L8p
DQ5L/DIFFIO_TX_L8n
DQ5L/DIFFIO_TX_L9p
DQ5L/DIFFIO_TX_L9n
DQ6L/DIFFIO_TX_L10p
DQ6L/DIFFIO_TX_L10n
DQ6L/DIFFIO_RX_L10p
DQ6L/DIFFIO_RX_L10n
DQS1L/DIFFIO_RX_L2p
DQSn1L/DIFFIO_RX_L2n
DQS2L/DIFFIO_RX_L3p
DQSn2L/DIFFIO_RX_L3n
DQS5L/DIFFIO_RX_L8p
DQSn5L/DIFFIO_RX_L8n
DQS6L/DIFFIO_RX_L9p
DQSn6L/DIFFIO_RX_L9n
DQ3L/DIFFIO_TX_L5p
DQ3L/DIFFIO_TX_L5n
DQ3L/DIFFIO_TX_L6p
DQ3L/DIFFIO_TX_L6n
DQ4L/DIFFIO_TX_L7p
DQ4L/DIFFIO_TX_L7n
DQ4L/DIFFIO_RX_L7p
DQ4L/DIFFIO_RX_L7n
DQ7L/DIFFIO_TX_L11p
DQ7L/DIFFIO_TX_L11n
DQ7L/DIFFIO_TX_L12p
DQ7L/DIFFIO_TX_L12n
DQS7L/DIFFIO_RX_L11p
DQSn7L/DIFFIO_RX_L11n
DQS3L/DIFFIO_RX_L5p
DQSn3L/DIFFIO_RX_L5n
DQS4L/DIFFIO_RX_L6p
DQSn4L/DIFFIO_RX_L6n
DIFFIO_TX_L1p
DIFFIO_TX_L1n
DIFFIO_RX_L12p
DIFFIO_RX_L12n
RUP1A/DIFFIO_RX_L1p
RDN1A/DIFFIO_RX_L1n
Bank 1C
DQ8L/DIFFIO_TX_L13p
DQ10L/DIFFIO_TX_L16p
DQ8L/DIFFIO_TX_L13n
DQ10L/DIFFIO_TX_L16n
DQ8L/DIFFIO_TX_L14p
DQ10L/DIFFIO_TX_L17p
DQ8L/DIFFIO_TX_L14n
DQ10L/DIFFIO_TX_L17n
DQ9L/DIFFIO_RX_L15p
DQ11L/DIFFIO_RX_L18p
DQ9L/DIFFIO_RX_L15n
DQ11L/DIFFIO_RX_L18n
DQ9L/DIFFIO_TX_L15p
DQ11L/DIFFIO_TX_L18p
DQ9L/DIFFIO_TX_L15n DIFFIO_TX_L18N on CONFIG BLOCK
DQS8L/DIFFIO_RX_L13p
DQSn8L/DIFFIO_RX_L13n
DQS9L/DIFFIO_RX_L14p
DQSn9L/DIFFIO_RX_L14n
DQS10L/DIFFIO_RX_L16p
DQSn10L/DIFFIO_RX_L16n
DQS11L/DIFFIO_RX_L17p
DQSn11L/DIFFIO_RX_L17n
L31
K31
T28
R28
T27
R27
G35
F35
FSM_D27
FSM_D26
FSM_D31
FSM_D30
MAX2_WEn
MAX2_BEn3
SENSE_ADC_F0
SRAM_DQP0
F32
E32
F34
E34
FSM_D29
FSM_D28
MAX2_BEn1
MAX2_CSn
K32
J33
R29
P29
MAX2_CLK
MAX2_OEn
PCIE_LED_X1
MAX2_BEn2
G33
F33
USER_DIPSW4
USER_LED0
L29
K29
H34
H35
ENET_TX_P
ENET_TX_N
MAX2_BEn0
SENSE_CS1n
R32
R33
W28
V28
U31
V31
R30
PCIE_PERSTn
USER_LED2
SENSE_SDO
USER_LED14
ENET_RESETn
ENET_INTn
M33
M34
L34
L35
ENET_MDIO
USER_PB2
USER_LED3
USER_LED6
EP4SGX230KF40_F1517
Version = 0.4 Preliminary
FSM_A2
FSM_A3
FSM_A6
FSM_A7
FSM_A8
FSM_A9
FSM_A10
FSM_A11
AC26
AD26
AD27
AE27
AT34
AR34
AJ31
AH30
FSM_A4
FSM_A5
FSM_A12
FSM_A13
AN33
AP34
AT33
AU33
FSM_A14
FSM_A15
FSM_A18
FSM_A19
FSM_A20
FSM_A21
FSM_A22
FSM_A23
AK32
AL32
AG29
AH29
AP32
AR32
AK31
AL31
FSM_A16
FSM_A17
FSM_A24
FSM_A25
AP35
AR35
AN30
AP30
S4VCCIO_B1B2
49.9
49.9
R193
R194
AU34
AV34
ENET_RX_P
ENET_RX_N
LCD_D_Cn
SENSE_CS0n
HSMB_SCL
PCIE_LED_G2
SRAM_GWn
AC31
AC32
AB30
AB31
AB27
AB28
AC28
AC29
LCD_DATA1
SRAM_DQP3
ENET_MDC
PCIE_LED_X4
AJ34
AJ35
AH34
AH35
USER_PB0
SRAM_OEn
USER_DIPSW7
AK35
AK34
AG31
AG32
AD28
AD29
AE29
AE28
USER_LED13
PCIE_LED_X8
SENSE_SCK
B
Bank 2A
DQ20L/DIFFIO_TX_L33p
DQ20L/DIFFIO_TX_L33n
DQ20L/DIFFIO_TX_L34p
DQ20L/DIFFIO_TX_L34n
DQ21L/DIFFIO_RX_L35p
DQ21L/DIFFIO_RX_L35n
DQ21L/DIFFIO_TX_L35p
DQ21L/DIFFIO_TX_L35n
DQS20L/DIFFIO_RX_L34p
DQSn20L/DIFFIO_RX_L34n
DQS21L/DIFFIO_RX_L36p
DQSn21L/DIFFIO_RX_L36n
DQ22L/DIFFIO_TX_L36p
DQ22L/DIFFIO_TX_L36n
DQ22L/DIFFIO_TX_L37p
DQ22L/DIFFIO_TX_L37n
DQ23L/DIFFIO_RX_L38p
DQ23L/DIFFIO_RX_L38n
DQ23L/DIFFIO_TX_L38p
DQ23L/DIFFIO_TX_L38n
DQ24L/DIFFIO_TX_L39p
DQ24L/DIFFIO_TX_L39n
DQ24L/DIFFIO_TX_L40p
DQ24L/DIFFIO_TX_L40n
DQ25L/DIFFIO_RX_L41p
DQ25L/DIFFIO_RX_L41n
DQ25L/DIFFIO_TX_L41p
DQ25L/DIFFIO_TX_L41n
DQS24L/DIFFIO_RX_L40p
DQSn24L/DIFFIO_RX_L40n
DQS25L/DIFFIO_RX_L42p
DQSn25L/DIFFIO_RX_L42n
DQ26L/DIFFIO_TX_L42p
DQ26L/DIFFIO_TX_L42n
DQ26L/DIFFIO_TX_L43p
DQ26L/DIFFIO_TX_L43n
DQS26L/DIFFIO_RX_L43p
DQSn26L/DIFFIO_RX_L43n
DQS22L/DIFFIO_RX_L37p
DQSn22L/DIFFIO_RX_L37n
DQS23L/DIFFIO_RX_L39p
DQSn23L/DIFFIO_RX_L39n
DIFFIO_RX_L33p
DIFFIO_RX_L33n
DIFFIO_TX_L44p
DIFFIO_TX_L44n
AE26
AF26
AK30
AL30
AT31
AU31
AG28
AH28
SRAM_CLK
FLASH_CLK
SRAM_BWEn
FLASH_RESETn
FLASH_WEn
FLASH_CEn
SRAM_ADSPn
SRAM_BWn2
AM31
AN31
AR31
AT30
SRAM_ADSCn
FLASH_ADVn
SRAM_BWn1
SRAM_CEn
AG27
AH27
AL29
AM29
FLASH_OEn
SRAM_BWn0
SRAM_BWn3
HSMA_CLK_OUT0
AT32
AU32
FLASH_RDYBSYn
SRAM_ADVn
AN32
AP33
AJ29
AK29
DQ16L/DIFFIO_RX_L27n
DQ16L/DIFFIO_RX_L27p
DQ16L/DIFFIO_TX_L27p
DQ16L/DIFFIO_TX_L27n
DQ17L/DIFFIO_TX_L28p
DQ17L/DIFFIO_TX_L28n
DQ17L/DIFFIO_TX_L29n
DQ17L/DIFFIO_TX_L29p
16,17
16,17
16,17
16,17
16,17
16,17
16,17
FLASH_OEn
FLASH_CLK
FLASH_WEn
FLASH_CEn
FLASH_ADVn
FLASH_RDYBSYn
FLASH_RESETn
18
12
12
12
12
HSMB_TX_LED
HSMA_CLK_OUT0
HSMB_CLK_OUT0
HSMB_SCL
HSMB_SDA
E
D
FSM_A0
FSM_A1
SRAM_ZZ
HSMB_CLK_OUT0
SENSE INTERFACE
Bank 2C
DQS14L/DIFFIO_RX_L25p
DQSn14L/DIFFIO_RX_L25n
DQS15L/DIFFIO_RX_L26p
DQSn15L/DIFFIO_RX_L26n
SRAM_CEn
SRAM_ADSCn
SRAM_ADSPn
SRAM_ADVn
SRAM_BWEn
SRAM_CLK
SRAM_ZZ
SRAM_GWn
SRAM_OEn
SRAM_DQP0
SRAM_DQP1
SRAM_DQP2
SRAM_DQP3
HSMC INTERFACE
RUP2A/DIFFIO_RX_L44p
RDN2A/DIFFIO_RX_L44n
DQ14L/DIFFIO_RX_L24p
DQ14L/DIFFIO_RX_L24n
DQ14L/DIFFIO_TX_L24p
DQ14L/DIFFIO_TX_L24n
DQ15L/DIFFIO_TX_L25p
DQ15L/DIFFIO_TX_L25n
DQ15L/DIFFIO_TX_L26p
DQ15L/DIFFIO_TX_L26n
16
16
16
16
16
16
16,17
16
16
16
16
16
16
DQ18L/DIFFIO_RX_L30p
DQ18L/DIFFIO_RX_L30n
DQ18L/DIFFIO_TX_L30p
DQ18L/DIFFIO_TX_L30n
DQ19L/DIFFIO_TX_L31p
DQ19L/DIFFIO_TX_L31n
DQ19L/DIFFIO_TX_L32p
DQ19L/DIFFIO_TX_L32n
DQS18L/DIFFIO_RX_L31p
DQSn18L/DIFFIO_RX_L31n
DQS19L/DIFFIO_RX_L32p
DQSn19L/DIFFIO_RX_L32n
AN34
AN35
AD30
AD31
AF29
AG30
AE30
AE31
LCD_DATA5
USER_DIPSW3
LCD_DATA7
LCD_DATA0
HSMB_SDA
USER_LED12
USER_LED10
PCIE_SMBCLK
AM34
AM35
AJ32
AK33
USER_LED4
USER_LED7
SRAM_DQP1
USER_LED1
17,25
17,25
17,25
17,25
17,25
17,25
17,25
SENSE_SMB_DATA
SENSE_SDI
SENSE_SDO
SENSE_SCK
SENSE_ADC_F0
SENSE_CS0n
SENSE_CS1n
C
LCD & USER I/O INTERFACES
10,18 LCD_DATA[7:0]
18 LCD_CSn
18 LCD_D_Cn
18 LCD_WEn
9,18 USER_DIPSW[7:0]
9,18 USER_PB[2:0]
DQS16L/DIFFIO_RX_L28p
DQSn16L/DIFFIO_RX_L28n
DQS17L/DIFFIO_RX_L29p
DQSn17L/DIFFIO_RX_L29n
AL34
AL35
AH32
AH33
9,10,18 USER_LED[15:0]
LCD_WEn
USER_DIPSW0
SENSE_SMB_DATA
HSMB_TX_LED
17 MAX2_BEn[3:0]
PCIE INTERFACE
EP4SGX230KF40_F1517
Version = 0.4 Preliminary
ETHERNET INTERFACE
13
13
13
13
13
13
13
13
ENET_RX_P
ENET_RX_N
ENET_INTn
ENET_RESETn
ENET_MDIO
ENET_MDC
ENET_TX_P
ENET_TX_N
18
3
3
18
18
18
3
3
PCIE_LED_G2
PCIE_WAKEn
PCIE_PERSTn
PCIE_LED_X1
PCIE_LED_X4
PCIE_LED_X8
PCIE_SMBCLK
PCIE_SMBDAT
17
17
17
17
MAX2_OEn
MAX2_CSn
MAX2_WEn
MAX2_CLK
B
MAX II CONTROL
A
A
Altera Corporation, 9330 Scranton Rd, San Diego, CA 92121
Title
Copyright (c) 2009 Altera Corporation. All Rights Reserved.
Stratix IV GX FPGA Development Kit Board
Size
B
Date:
8
7
6
5
4
3
Document Number
Rev
150-0310901-B1 (6XX-41284R )
Friday, May 01, 2009
2
Sheet
4
B
of
1
29
8
7
6
5
4
Stratix IV Banks 3 and 4
U13D
E
U13C
S4VCCIO_B3A
D
C
B
HDMI_VSYNC
HDMI_CLK
HDMI_DE
HDMI_HSYNC
HDMI_D22
HDMI_D4
HDMI_D21
HDMI_D2
AE25
AD25
AK27
AE24
AL27
AH26
AJ25
AK25
49.9
R177
49.9
R178
HDMI_D23
HDMI_D6
AF25
AG25
AJ26
AK26
HDMI_D20
HDMI_D0
HDMI_D16
HDMI_D17
HDMI_D12
HDMI_D13
HDMI_D10
HDMI_D11
AW33
AW34
AW31
AV31
AW27
AW28
AV28
AW29
HDMI_D18
HDMI_D19
HDMI_D14
HDMI_D15
AV32
AW32
AV29
AW30
DDR3BOT_DQ51
DDR3BOT_DQ52
DDR3BOT_DQ54
DDR3BOT_DQ49
DDR3BOT_DQ50
DDR3BOT_DQ48
DDR3BOT_DQ55
AN25
AM25
AR25
AP25
AU25
AT25
AV26
AW26
DDR3BOT_DM6
DDR3BOT_DQ53
DDR3BOT_DQS_P6
DDR3BOT_DQS_N6
AN24
AP24
AT26
AU26
DDR3BOT_DQ35
DDR3BOT_DQ33
DDR3BOT_DQ37
DDR3BOT_DQ36
DDR3BOT_DQ38
DDR3BOT_DQ34
DDR3BOT_DQ32
AM23
AN23
AL22
AL21
AP23
AR23
AT23
AU23
DDR3BOT_DM4
DDR3BOT_DQ39
DDR3BOT_DQS_P4
DDR3BOT_DQS_N4
AM22
AN22
AT24
AU24
Stratix IV GX Bank 3
DQ1B/DIFFOUT_B1p
DQ1B/DIFFOUT_B1n
DQ1B/DIFFOUT_B3p
DQ1B/DIFFOUT_B3n
DQ2B/DIFFOUT_B5p
DQ2B/DIFFOUT_B5n
DQ2B/DIFFIO_RX_B3p
DQ2B/DIFFIO_RX_B3n
Bank 3A
RUP3A/DQS1B/DIFFIO_RX_B1p
RDN3A/DQSn1B/DIFFIO_RX_B1n
DQS2B/DIFFIO_RX_B2p
DQSn2B/DIFFIO_RX_B2n
DQ3B/DIFFOUT_B7p
DQ3B/DIFFOUT_B7n
DQ3B/DIFFOUT_B9p
DQ3B/DIFFOUT_B9n
DQ4B/DIFFOUT_B11p
DQ4B/DIFFOUT_B11n
DQ4B/DIFFIO_RX_B6p
DQ4B/DIFFIO_RX_B6n
DQ5B/DIFFOUT_B13p
DQ5B/DIFFOUT_B13n
DQ5B/DIFFOUT_B15p
DQ5B/DIFFOUT_B15n
DQ6B/DIFFOUT_B17p
DQ6B/DIFFOUT_B17n
DQ6B/DIFFIO_RX_B9p
DQ6B/DIFFIO_RX_B9n
DQS5B/DIFFIO_RX_B7p
DQSn5B/DIFFIO_RX_B7n
DQS6B/DIFFIO_RX_B8p
DQSn6B/DIFFIO_RX_B8n
DIFFIO_RX_B10p
DIFFIO_RX_B10n
DIFFOUT_B19p
DIFFOUT_B19n
AP27
AN27
AL25
AP26
AU29
AT29
AT28
AU28
HDMI_D8
HDMI_D9
HDMI_D1
HDMI_D3
HDMI_I2S1
HDMI_I2S0
HDMI_I2S3
HDMI_I2S2
AM26
AN26
AP28
AR28
HDMI_D5
HDMI_D7
HDMI_MCLK
HDMI_SPDIF
AT27
AU27
HDMI_SCL
HDMI_SDA
AH24
AG24
HDMI_SCLK
HDMI_LRCLK
DQS3B/DIFFIO_RX_B4p
DQSn3B/DIFFIO_RX_B4n
DQS4B/DIFFIO_RX_B5p
DQSn4B/DIFFIO_RX_B5n
Bank 3B
DQ7B/DIFFOUT_B21p
DQ7B/DIFFOUT_B21n
DQ7B/DIFFOUT_B23p
DQ7B/DIFFOUT_B23n
DQ8B/DIFFOUT_B25p
DQ8B/DIFFOUT_B25n
DQ8B/DIFFIO_RX_B13p
DQ8B/DIFFIO_RX_B13n
DQ9B/DIFFOUT_B27p
DQ9B/DIFFOUT_B27n
DQ9B/DIFFOUT_B29p
DQ9B/DIFFOUT_B29n
DQ10B/DIFFOUT_B31p
DQ10B/DIFFOUT_B31n
DQ10B/DIFFIO_RX_B16p
DQ10B/DIFFIO_RX_B16n
DQS7B/DIFFIO_RX_B11p
DQSn7B/DIFFIO_RX_B11n
DQS8B/DIFFIO_RX_B12p
DQSn8B/DIFFIO_RX_B12n
DQS9B/DIFFIO_RX_B14p
DQSn9B/DIFFIO_RX_B14n
DQS10B/DIFFIO_RX_B15p
DQSn10B/DIFFIO_RX_B15n
Bank 3C
DQ11B/DIFFOUT_B33p
DQ11B/DIFFOUT_B33n
DQ11B/DIFFOUT_B35p
DQ11B/DIFFOUT_B35n
DQ12B/DIFFOUT_B37p
DQ12B/DIFFOUT_B37n
DQ12B/DIFFIO_RX_B19p
DQ12B/DIFFIO_RX_B19n
DQS11B/DIFFIO_RX_B17p
DQSn11B/DIFFIO_RX_B17n
DQS12B/DIFFIO_RX_B18p
DQSn12B/DIFFIO_RX_B18n
DQ13B/DIFFOUT_B39p
DQ13B/DIFFOUT_B39n
DQ13B/DIFFOUT_B41p
DQ13B/DIFFOUT_B41n
DQS13B/DIFFIO_RX_B20p
DQSn13B/DIFFIO_RX_B20n
DIFFIO_RX_B21p
DIFFIO_RX_B21n
DIFFIO_RX_B22p
DIFFIO_RX_B22n
3
AE23
AH22
AF23
AE22
AJ22
AK24
AH23
AJ23
DDR3BOT_DQ62
DDR3BOT_DQ58
DDR3BOT_DQ63
DDR3BOT_DQ61
DDR3BOT_DQ57
DDR3BOT_DQ59
DDR3BOT_DQ56
AF22
AG22
AK23
AL23
DDR3BOT_DM7
DDR3BOT_DQ60
DDR3BOT_DQS_P7
DDR3BOT_DQS_N7
AT14
AU14
AV14
AW14
AW12
AW11
AT12
AU12
DDR3BOT_DQS_P1
DDR3BOT_DQS_N1
DDR3BOT_DM1
DDR3BOT_DQ14
AV13
AW13
AU11
AV11
DDR3BOT_DQ7
DDR3BOT_DQ2
DDR3BOT_DQ6
DDR3BOT_DQ4
DDR3BOT_DQ5
DDR3BOT_A5
DDR3BOT_DQ3
DDR3BOT_DQ0
AP13
AN14
AP14
AR14
AN13
AL15
AL14
AM14
DDR3BOT_DQS_P0
DDR3BOT_DQS_N0
DDR3BOT_DM0
DDR3BOT_DQ1
AR13
AT13
AL13
AM13
DDR3BOT_DQ26
DDR3BOT_DQ28
AJ16
AM17
AK17
AL17
AH17
AE17
AH16
AG16
DDR3BOT_DQS_P3
DDR3BOT_DQS_N3
DDR3BOT_DM3
DDR3BOT_DQ30
AK16
AL16
AF17
AG17
DDR3BOT_DQ47
DDR3BOT_DQ46
DDR3BOT_DQ44
DDR3BOT_DQ45
AD19
AG19
AG18
AE18
AT17
AW18
AT18
AU18
DDR3BOT_DQS_P5
DDR3BOT_DQS_N5
AE19
AF19
AU17
AV17
DDR3BOT_DQ24
DDR3BOT_DQ25
DDR3BOT_DQ31
DDR3BOT_DQ27
DDR3BOT_DQ29
AD21
AG20
AG21
AE21
AE20
AF20
DDR3BOT_A3
DDR3BOT_DQ13
DDR3BOT_DQ11
DDR3BOT_DQ9
DDR3BOT_DQ15
DDR3BOT_DQ12
DDR3BOT_DQ8
DDR3BOT_DQ10
DDR3BOT_CK_P
DDR3BOT_CK_N
AV25
AW25
AV23
HDMI_INTn
AW23 1.8V driving into 1.5V bank
2
1
E
Stratix IV GX Bank 4
HDMI INTERFACE
Bank 4A
DQ21B/DIFFOUT_B80p
DQ21B/DIFFOUT_B80n
DQ21B/DIFFIO_RX_B40p
DQ21B/DIFFIO_RX_B40n
DQ22B/DIFFOUT_B82p
DQ22B/DIFFOUT_B82n
DQ22B/DIFFOUT_B84p
DQ22B/DIFFOUT_B84n
DQS21B/DIFFIO_RX_B41p
DQSn21B/DIFFIO_RX_B41n
DQS22B/DIFFIO_RX_B42p
DQSn22B/DIFFIO_RX_B42n
DQ25B/DIFFOUT_B92p
DQ25B/DIFFOUT_B92n
DQ25B/DIFFIO_RX_B46p
DQ25B/DIFFIO_RX_B46n
DQ26B/DIFFOUT_B94p
DQ26B/DIFFOUT_B94n
DQ26B/DIFFOUT_B96p
DQ26B/DIFFOUT_B96n
DQS25B/DIFFIO_RX_B47p
DQSn25B/DIFFIO_RX_B47n
RUP4A/DQS26B/DIFFIO_RX_B48p
RDN4A/DQSn26B/DIFFIO_RX_B48n
DQ23B/DIFFOUT_B86p
DQ23B/DIFFOUT_B86n
DQ23B/DIFFIO_RX_B43p
DQ23B/DIFFIO_RX_B43n
DQ24B/DIFFOUT_B88p
DQ24B/DIFFOUT_B88n
DQ24B/DIFFOUT_B90p
DQ24B/DIFFOUT_B90n
DIFFIO_RX_B39p
DIFFIO_RX_B39n
DIFFOUT_B78n
DIFFOUT_B78p
AH13
AK14
AJ13
AK13
AG14
AG15
AD15
AE15
DDR3BOT_A8
DDR3BOT_A9
DDR3BOT_A11
DDR3BOT_A0
DDR3BOT_A6
DDR3BOT_A1
DDR3BOT_BA1
DDR3BOT_BA2
AH14
AJ14
AE14
AF14
DDR3BOT_A2
DDR3BOT_A14
DDR3BOT_A12
DDR3BOT_BA0
AN15
AP15
DDR3BOT_A13
DDR3BOT_A7
AF16
AE16
DDR3BOT_A4
DDR3BOT_A10
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
HDMI_SCL
HDMI_I2S0
HDMI_I2S1
HDMI_I2S2
HDMI_I2S3
HDMI_MCLK
HDMI_SPDIF
HDMI_LRCLK
HDMI_SCLK
HDMI_HSYNC
HDMI_VSYNC
HDMI_CLK
HDMI_DE
HDMI_INTn
HDMI_SDA
D
DDR3 BOTTOM INTERFACE
15 DDR3BOT_DQ[63:0]
15 DDR3BOT_A[14:0]
DQS23B/DIFFIO_RX_B44p
DQSn23B/DIFFIO_RX_B44n
DQS24B/DIFFIO_RX_B45p
DQSn24B/DIFFIO_RX_B45n
15 DDR3BOT_DQS_P[7:0]
15 DDR3BOT_DQS_N[7:0]
Bank 4B
DQ17B/DIFFOUT_B66p
DQ17B/DIFFOUT_B66n
DQ17B/DIFFIO_RX_B33p
DQ17B/DIFFIO_RX_B33n
DQ18B/DIFFOUT_B68p
DQ18B/DIFFOUT_B68n
DQ18B/DIFFOUT_B70p
DQ18B/DIFFOUT_B70n
DQ19B/DIFFOUT_B72p
DQ19B/DIFFOUT_B72n
DQ19B/DIFFIO_RX_B36p
DQ19B/DIFFIO_RX_B36n
DQ20B/DIFFOUT_B74p
DQ20B/DIFFOUT_B74n
DQ20B/DIFFOUT_B76p
DQ20B/DIFFOUT_B76n
DQS17B/DIFFIO_RX_B34p
DQSn17B/DIFFIO_RX_B34n
DQS18B/DIFFIO_RX_B35p
DQSn18B/DIFFIO_RX_B35n
DQS19B/DIFFIO_RX_B37p
DQSn19B/DIFFIO_RX_B37n
DQS20B/DIFFIO_RX_B38p
DQSn20B/DIFFIO_RX_B38n
Bank 4C
DQ14B/DIFFOUT_B56p
DQ14B/DIFFOUT_B56n
DQ14B/DIFFOUT_B58p
DQ14B/DIFFOUT_B58n
DQ15B/DIFFOUT_B60p
DQ15B/DIFFOUT_B60n
DQ15B/DIFFIO_RX_B30p
DQ15B/DIFFIO_RX_B30n
11 HDMI_D[23:0]
DQ16B/DIFFOUT_B62p
DQ16B/DIFFOUT_B62n
DQ16B/DIFFOUT_B64p
DQ16B/DIFFOUT_B64n
DQS16B/DIFFIO_RX_B32p
DQSn16B/DIFFIO_RX_B32n
DQS14B/DIFFIO_RX_B29p
DQSn14B/DIFFIO_RX_B29n
DQS15B/DIFFIO_RX_B31p
DQSn15B/DIFFIO_RX_B31n
DIFFIO_RX_B27p
DIFFIO_RX_B27n
DIFFIO_RX_B28p
DIFFIO_RX_B28n
AN16
AN17
AP17
AR17
AW16
AT16
AU15
AT15
DDR3BOT_DQ18
15 DDR3BOT_DM[7:0]
DDR3BOT_DQ20
DDR3BOT_DQ22
DDR3BOT_DQ17
DDR3BOT_DQ16
DDR3BOT_DQ23
DDR3BOT_DQ21
15 DDR3BOT_BA[2:0]
AP16
AR16
AU16
AV16
DDR3BOT_DQS_P2
DDR3BOT_DQS_N2
DDR3BOT_DM2
DDR3BOT_DQ19
AN19
AM19
AR19
AP19
DDR3BOT_DQ43
AN18
AP18
DDR3BOT_DM5
DDR3BOT_DQ42
AU20
AV20
AT19
AU19
DDR3BOT_ODT
15 DDR3BOT_CK_P
15 DDR3BOT_CK_N
15 DDR3BOT_ODT
C
DDR3BOT_DQ40
DDR3BOT_DQ41
B
EP4SGX230KF40_F1517
Version = 0.4 Preliminary
EP4SGX230KF40_F1517
Version = 0.4 Preliminary
A
A
Altera Corporation, 9330 Scranton Rd, San Diego, CA 92121
Title
Copyright (c) 2009 Altera Corporation. All Rights Reserved.
Stratix IV GX FPGA Development Kit Board
Size
B
Date:
8
7
6
5
4
3
Document Number
Rev
150-0310901-B1 (6XX-41284R )
Friday, May 01, 2009
2
Sheet
5
B
of
1
29
8
7
6
5
Stratix IV Banks 5 and 6
4
3
2
1
E
E
U13E
D
HSMB_D1
HSMB_D0
SDI_CLK148_DN
HSMA_SDA
HSMA_D1
HSMA_D0
HSMA_PRSNTn
SDI_CLK148_UP
AN10
AP10
AH11
AJ11
AV10
AW10
AG12
AH12
HSMB_D3
HSMB_D2
HSMB_RX_LED
AV8
AW8
AT10
AU10
HSMA_CLK_OUT_P2
HSMA_CLK_OUT_N2
HSMA_TX_D_P0
HSMA_TX_D_N0
HSMA_RX_D_P2
HSMA_RX_D_N2
HSMA_TX_D_P1
HSMA_TX_D_N1
AF13
AG13
AN9
AP9
AP8
AR8
AN7
AP7
AT9
AU9
AT8
AU8
HSMA_RX_D_P0
HSMA_RX_D_N0
HSMA_RX_D_P1
HSMA_RX_D_N1
C
B
HSMA_TX_D_P7
HSMA_TX_D_N7
HSMA_TX_D_P5
HSMA_TX_D_N5
HSMA_RX_D_P9
HSMA_RX_D_N9
HSMA_TX_D_P12
HSMA_TX_D_N12
AH9
AH8
AK8
AK7
AN6
AN5
AE11
AE10
HSMA_RX_D_P8
HSMA_RX_D_N8
HSMA_RX_D_P10
HSMA_RX_D_N10
AP6
AP5
AM6
AM5
HSMA_TX_D_P10
HSMA_TX_D_N10
HSMA_TX_D_P9
HSMA_TX_D_N9
HSMA_RX_D_P13
HSMA_RX_D_N13
HSMA_TX_D_P11
HSMA_TX_D_N11
AF11
AF10
AG10
AG9
AJ6
AJ5
AD10
AD9
HSMA_RX_D_P11
HSMA_RX_D_N11
HSMA_RX_D_P12
HSMA_RX_D_N12
AL6
AL5
AK6
AK5
U13F
Stratix IV GX Bank 5
Bank 5A
DQ1R/DIFFIO_TX_R2p
DQ1R/DIFFIO_TX_R2n
DQ1R/DIFFIO_TX_R3p
DQ1R/DIFFIO_TX_R3n
DQ2R/DIFFIO_RX_R4p
DQ2R/DIFFIO_RX_R4n
DQ2R/DIFFIO_TX_R4p
DQ2R/DIFFIO_TX_R4n
DQ5R/DIFFIO_TX_R8p
DQ5R/DIFFIO_TX_R8n
DQ5R/DIFFIO_TX_R9p
DQ5R/DIFFIO_TX_R9n
DQ6R/DIFFIO_RX_R10p
DQ6R/DIFFIO_RX_R10n
DQ6R/DIFFIO_TX_R10p
DQ6R/DIFFIO_TX_R10n
DQS1R/DIFFIO_RX_R2p
DQSn1R/DIFFIO_RX_R2n
DQS2R/DIFFIO_RX_R3p
DQSn2R/DIFFIO_RX_R3n
DQS5R/DIFFIO_RX_R8p
DQSn5R/DIFFIO_RX_R8n
DQS6R/DIFFIO_RX_R9p
DQSn6R/DIFFIO_RX_R9n
DQ3R/DIFFIO_TX_R5p
DQ3R/DIFFIO_TX_R5n
DQ3R/DIFFIO_TX_R6p
DQ3R/DIFFIO_TX_R6n
DQ4R/DIFFIO_RX_R7p
DQ4R/DIFFIO_RX_R7n
DQ4R/DIFFIO_TX_R7p
DQ4R/DIFFIO_TX_R7n
DQ7R/DIFFIO_TX_R11p
DQ7R/DIFFIO_TX_R11n
DQ7R/DIFFIO_TX_R12p
DQ7R/DIFFIO_TX_R12n
DQS7R/DIFFIO_RX_R11p
DQSn7R/DIFFIO_RX_R11n
DQS3R/DIFFIO_RX_R5p
DQSn3R/DIFFIO_RX_R5n
DQS4R/DIFFIO_RX_R6p
DQSn4R/DIFFIO_RX_R6n
RUP5A/DIFFIO_RX_R1p
RDN5A/DIFFIO_RX_R1n
DIFFIO_TX_R1p
DIFFIO_TX_R1n
DIFFIO_RX_R12p
DIFFIO_RX_R12n
Bank 5C
DQ8R/DIFFIO_TX_R13p
DQ8R/DIFFIO_TX_R13n
DQ8R/DIFFIO_TX_R14p
DQ8R/DIFFIO_TX_R14n
DQ9R/DIFFIO_RX_R15p
DQ9R/DIFFIO_RX_R15n
DQ9R/DIFFIO_TX_R15p
DQ9R/DIFFIO_TX_R15n
DQ12R/DIFFIO_TX_R19p
DQ12R/DIFFIO_TX_R19n
DQ12R/DIFFIO_TX_R20p
DQ12R/DIFFIO_TX_R20n
DQ13R/DIFFIO_RX_R21p
DQ13R/DIFFIO_RX_R21n
DQ13R/DIFFIO_TX_R21p
DQ13R/DIFFIO_TX_R21n
DQS8R/DIFFIO_RX_R13p
DQSn8R/DIFFIO_RX_R13n
DQS9R/DIFFIO_RX_R14p
DQSn9R/DIFFIO_RX_R14n
DQS12R/DIFFIO_RX_R19p
DQSn12R/DIFFIO_RX_R19n
DQS13R/DIFFIO_RX_R20p
DQSn13R/DIFFIO_RX_R20n
AK9
AL9
AL8
AM8
AV5
AW4
AH10
AJ10
HSMA_TX_D_P4
HSMA_TX_D_N4
HSMA_TX_D_P3
HSMA_TX_D_N3
HSMA_RX_D_P4
HSMA_RX_D_N4
HSMA_TX_D_P6
HSMA_TX_D_N6
HSMB_TX_D_P15
HSMB_TX_D_N15
HSMB_TX_D_P12
HSMB_TX_D_N12
HSMB_RX_D_P11
HSMB_RX_D_N11
HSMB_TX_D_P16
HSMB_TX_D_N16
T13
T12
H7
G7
G5
F5
R13
P13
AT7
AU7
AT6
AU6
HSMA_RX_D_P5
HSMA_RX_D_N5
HSMA_RX_D_P6
HSMA_RX_D_N6
HSMB_RX_D_P12
HSMB_RX_D_N12
HSMB_RX_D_P10
HSMB_RX_D_N10
F7
E7
G6
F6
AE13
AE12
AD13
AD12
HSMA_TX_D_P2
HSMA_TX_D_N2
HSMA_TX_D_P13
HSMA_TX_D_N13
AR5
AT5
HSMA_RX_D_P7
HSMA_RX_D_N7
HSMB_TX_D_P14
HSMB_TX_D_N14
HSMB_TX_D_P7
HSMB_TX_D_N7
HSMB_RX_D_P16
HSMB_RX_D_N16
HSMB_TX_D_P13
HSMB_TX_D_N13
R12
R11
N11
N10
F10
E10
M10
L10
AV7
AW7
AL10
AM10
AW6
AW5
HSMA_D3
HSMA_D2
HSMA_CLK_OUT_P1
HSMA_CLK_OUT_N1
HSMA_RX_D_P3
HSMA_RX_D_N3
HSMB_RX_D_P13
HSMB_RX_D_N13
HSMB_RX_D_P14
HSMB_RX_D_N14
G9
F9
D7
C7
AG8
AG7
AB11
AB10
AG6
AG5
AB13
AB12
HSMA_TX_D_P8
HSMA_TX_D_N8
HSMA_TX_D_P15
HSMA_TX_D_N15
HSMA_RX_D_P15
HSMA_RX_D_N15
HSMA_TX_D_P14
HSMA_TX_D_N14
HSMB_TX_D_P1
HSMB_TX_D_N1
HSMB_RX_D_P0
HSMB_RX_D_N0
HSMB_TX_D_P3
HSMB_TX_D_N3
HSMB_TX_D_P2
HSMB_TX_D_N2
V12
V11
W8
W7
U10
T9
V10
V9
AB9
AC8
AH6
AH5
HSMA_RX_D_P16
HSMA_RX_D_N16
HSMA_RX_D_P14
HSMA_RX_D_N14
HSMB_RX_D_P1
HSMB_RX_D_N1
HSMB_RX_D_P3
HSMB_RX_D_N3
V6
U5
R6
R5
HSMB_RX_D_P2
HSMB_RX_D_N2
HSMB_TX_D_P6
HSMB_TX_D_N6
HSMB_TX_D_P4
HSMB_TX_D_N4
HSMB_TX_D_P5
HSMB_TX_D_N5
R7
P6
N9
P8
T10
R10
R9
R8
HSMB_RX_D_P4
HSMB_RX_D_N4
HSMB_RX_D_P6
HSMB_RX_D_N6
N6
N5
M6
L5
DQ10R/DIFFIO_TX_R16p
DQ10R/DIFFIO_TX_R16n
DQ10R/DIFFIO_TX_R17p
DQ10R/DIFFIO_TX_R17n
DQ11R/DIFFIO_RX_R18p
DQ11R/DIFFIO_RX_R18n
DQ11R/DIFFIO_TX_R18p
DQ11R/DIFFIO_TX_R18n
DQS10R/DIFFIO_RX_R16p
DQSn10R/DIFFIO_RX_R16n
DQS11R/DIFFIO_RX_R17p
DQSn11R/DIFFIO_RX_R17n
EP4SGX230KF40_F1517
Version = 0.4 Preliminary
SDI INTERFACE
Stratix IV GX Bank 6
Bank 6A
DQ20R/DIFFIO_TX_R33p
DQ20R/DIFFIO_TX_R33n
DQ20R/DIFFIO_TX_R34p
DQ20R/DIFFIO_TX_R34n
DQ21R/DIFFIO_RX_R35p
DQ21R/DIFFIO_RX_R35n
DQ21R/DIFFIO_TX_R35p
DQ21R/DIFFIO_TX_R35n
DQ24R/DIFFIO_TX_R39p
DQ24R/DIFFIO_TX_R39n
DQ24R/DIFFIO_TX_R40p
DQ24R/DIFFIO_TX_R40n
DQ25R/DIFFIO_RX_R41p
DQ25R/DIFFIO_RX_R41n
DQ25R/DIFFIO_TX_R41p
DQ25R/DIFFIO_TX_R41n
DQS20R/DIFFIO_RX_R34p
DQSn20R/DIFFIO_RX_R34n
DQS21R/DIFFIO_RX_R36p
DQSn21R/DIFFIO_RX_R36n
DQ22R/DIFFIO_TX_R36p
DQ22R/DIFFIO_TX_R36n
DQ22R/DIFFIO_TX_R37p
DQ22R/DIFFIO_TX_R37n
DQ23R/DIFFIO_RX_R38p
DQ23R/DIFFIO_RX_R38n
DQ23R/DIFFIO_TX_R38p
DQ23R/DIFFIO_TX_R38n
DQS24R/DIFFIO_RX_R40p
DQSn24R/DIFFIO_RX_R40n
DQS25R/DIFFIO_RX_R42p
DQSn25R/DIFFIO_RX_R42n
DQ26R/DIFFIO_TX_R42p
DQ26R/DIFFIO_TX_R42n
DQ26R/DIFFIO_TX_R43p
DQ26R/DIFFIO_TX_R43n
DQS26R/DIFFIO_RX_R43p
DQSn26R/DIFFIO_RX_R43n
DQS22R/DIFFIO_RX_R37p
DQSn22R/DIFFIO_RX_R37n
DQS23R/DIFFIO_RX_R39p
DQSn23R/DIFFIO_RX_R39n
DIFFIO_RX_R33p
DIFFIO_RX_R33n
DIFFIO_TX_R44p
DIFFIO_TX_R44n
RUP6A/DIFFIO_RX_R44p
RDN6A/DIFFIO_RX_R44n
DQS14R/DIFFIO_RX_R25p
DQSn14R/DIFFIO_RX_R25n
DQS15R/DIFFIO_RX_R26p
DQSn15R/DIFFIO_RX_R26n
HSMB_TX_D_P11
HSMB_TX_D_N11
HSMB_CLK_OUT_P1
HSMB_CLK_OUT_N1
HSMB_PRSNTn
D8
C8
D5
C5
HSMB_RX_D_P15
HSMB_RX_D_N15
HSMA_TX_LED
N12
M12
K10
J10
9 SDI_CLK148_UP
9 SDI_CLK148_DN
HSMC PORT A INTERFACE
9,12 HSMA_TX_D_P[16:0]
HSMA_SCL
9,12 HSMA_TX_D_N[16:0]
12 HSMA_RX_D_P[16:0]
12 HSMA_RX_D_N[16:0]
D
12 HSMA_D[3:0]
12 HSMA_CLK_OUT_P[2:1]
HSMB_CLK_OUT_P2
HSMB_CLK_OUT_N2
D10
C10
G8
F8
H10
G10
D6
C6
HSMB_RX_D_P9
HSMB_RX_D_N9
N8
N7
M8
M7
L8
L7
K7
J7
HSMB_RX_D_P5
HSMB_RX_D_N5
HSMB_TX_D_P8
HSMB_TX_D_N8
HSMB_TX_D_P9
HSMB_TX_D_N9
HSMB_TX_D_P10
HSMB_TX_D_N10
K6
K5
J6
J5
HSMB_RX_D_P7
HSMB_RX_D_N7
HSMB_RX_D_P8
HSMB_RX_D_N8
12 HSMA_CLK_OUT_N[2:1]
12,17,18
12
12
18
18
HSMA_PRSNTn
HSMA_SDA
HSMA_SCL
HSMA_RX_LED
HSMA_TX_LED
HSMC PORT B INTERFACE
HSMA_RX_LED
9,12 HSMB_TX_D_P[16:0]
9,12 HSMB_TX_D_N[16:0]
Bank 6C
DQ14R/DIFFIO_TX_R24p
DQ14R/DIFFIO_TX_R24n
DQ14R/DIFFIO_RX_R24p
DQ14R/DIFFIO_RX_R24n
DQ15R/DIFFIO_TX_R25p
DQ15R/DIFFIO_TX_R25n
DQ15R/DIFFIO_TX_R26p
DQ15R/DIFFIO_TX_R26n
K9
J9
K8
J8
D9
C9
M11
L11
DQ18R/DIFFIO_RX_R30p
DQ18R/DIFFIO_RX_R30n
DQ18R/DIFFIO_TX_R30p
DQ18R/DIFFIO_TX_R30n
DQ19R/DIFFIO_TX_R31p
DQ19R/DIFFIO_TX_R31n
DQ19R/DIFFIO_TX_R32p
DQ19R/DIFFIO_TX_R32n
DQS18R/DIFFIO_RX_R31p
DQSn18R/DIFFIO_RX_R31n
DQS19R/DIFFIO_RX_R32p
DQSn19R/DIFFIO_RX_R32n
C
12 HSMB_RX_D_P[16:0]
12 HSMB_RX_D_N[16:0]
12 HSMB_CLK_OUT_P[2:1]
12 HSMB_CLK_OUT_N[2:1]
12,17,18 HSMB_PRSNTn
18 HSMB_RX_LED
12 HSMB_D[3:0]
DQ16R/DIFFIO_RX_R27p
DQ16R/DIFFIO_RX_R27n
DQ16R/DIFFIO_TX_R27p
DQ16R/DIFFIO_TX_R27n
DQ17R/DIFFIO_TX_R28p
DQ17R/DIFFIO_TX_R28n
DQ17R/DIFFIO_TX_R29p
DQ17R/DIFFIO_TX_R29n
B
DQS16R/DIFFIO_RX_R28p
DQSn16R/DIFFIO_RX_R28n
DQS17R/DIFFIO_RX_R29p
DQSn17R/DIFFIO_RX_R29n
EP4SGX230KF40_F1517
Version = 0.4 Preliminary
A
A
Altera Corporation, 9330 Scranton Rd, San Diego, CA 92121
Title
Copyright (c) 2009 Altera Corporation. All Rights Reserved.
Stratix IV GX FPGA Development Kit Board
Size
B
Date:
8
7
6
5
4
3
Document Number
Rev
150-0310901-B1 (6XX-41284R )
Friday, May 01, 2009
2
Sheet
6
B
of
1
29
8
7
6
5
4
3
Stratix IV Banks 7 and 8
2
1
DDR3 TOP INTERFACE
11 DDR3TOP_DQ[15:0]
11 DDR3TOP_DQS_P[1:0]
E
U13G
D
C
B
QDR2TOP1_Q17
QDR2TOP1_Q11
QDR2TOP1_Q15
QDR2TOP1_Q16
QDR2TOP1_Q13
QDR2TOP1_Q3
QDR2TOP1_Q9
QDR2TOP1_Q10
N13
M13
R14
N15
M14
K12
L14
K14
QDR2TOP1_Q14
QDR2TOP1_Q12
QDR2TOP1_CQ_N
QDR2TOP1_Q1
P14
N14
L13
K13
QDR2TOP1_Q2
QDR2TOP1_Q0
QDR2TOP1_Q4
QDR2TOP1_Q5
QDR2TOP1_Q6
QDR2TOP1_QVLD
QDR2TOP1_Q7
QDR2TOP1_Q8
J12
J13
H14
G14
F12
D13
F14
E14
QDR2TOP1_CQ_P
H13
G13
F13
E13
QDR2TOP1_D15
QDR2TOP1_D17
QDR2TOP1_D16
QDR2TOP1_D8
QDR2TOP1_D14
QDR2TOP1_D10
QDR2TOP1_D12
QDR2TOP1_D11
E16
G15
F15
G17
D16
A16
C16
B16
QDR2TOP1_D9
QDR2TOP1_A10
DDR3TOP_CSn
QDR2TOP1_D13
G16
F16
D15
C15
QDR2TOP1_A11
QDR2TOP1_A0
QDR2TOP1_WPSn
QDR2TOP1_A4
QDR2TOP1_A19
QDR2TOP1_A17
QDR2TOP1_A5
QDR2TOP1_RPSn
F17
C17
D18
C18
F20
G20
G19
F19
QDR2TOP1_A16
QDR2TOP1_A8
QDR2TOP1_A7
QDR2TOP1_A12
E17
D17
G18
F18
U13H
Stratix IV GX Bank 7
Bank 7A
DQ1T/DIFFOUT_T1p
DQ1T/DIFFOUT_T1n
DQ1T/DIFFOUT_T3p
DQ1T/DIFFOUT_T3n
DQ2T/DIFFOUT_T5p
DQ2T/DIFFOUT_T5n
DQ2T/DIFFIO_RX_T3p
DQ2T/DIFFIO_RX_T3n
DQ5T/DIFFOUT_T13p
DQ5T/DIFFOUT_T13n
DQ5T/DIFFOUT_T15p
DQ5T/DIFFOUT_T15n
DQ6T/DIFFOUT_T17p
DQ6T/DIFFOUT_T17n
DQ6T/DIFFIO_RX_T9p
DQ6T/DIFFIO_RX_T9n
RUP7A/DQS1T/DIFFIO_RX_T1p
RDN7A/DQSn1T/DIFFIO_RX_T1n
DQS2T/DIFFIO_RX_T2p
DQSn2T/DIFFIO_RX_T2n
DQS5T/DIFFIO_RX_T7p
DQSn5T/DIFFIO_RX_T7n
DQS6T/DIFFIO_RX_T8p
DQSn6T/DIFFIO_RX_T8n
DQ3T/DIFFOUT_T7p
DQ3T/DIFFOUT_T7n
DQ3T/DIFFOUT_T9p
DQ3T/DIFFOUT_T9n
DQ4T/DIFFOUT_T11p
DQ4T/DIFFOUT_T11n
DQ4T/DIFFIO_RX_T6p
DQ4T/DIFFIO_RX_T6n
DIFFIO_RX_T10p
DIFFIO_RX_T10n
DIFFOUT_T19p
DIFFOUT_T19n
A10
C11
D11
B10
C12
C13
B13
A13
DDR3TOP_DQ0
DDR3TOP_DQ4
DDR3TOP_DQ1
DDR3TOP_DQ2
DDR3TOP_DQ3
DDR3TOP_DQ5
DDR3TOP_DQ7
B11
A11
D14
C14
DDR3TOP_DM0
DDR3TOP_DQ6
DDR3TOP_DQS_P0
DDR3TOP_DQS_N0
B14
A14
DDR3TOP_BA0
DDR3TOP_BA2
K15
J15
DDR3TOP_ODT
DQS3T/DIFFIO_RX_T4p
DQSn3T/DIFFIO_RX_T4n
DQS4T/DIFFIO_RX_T5p
DQSn4T/DIFFIO_RX_T5n
Bank 7B
DQ7T/DIFFOUT_T21p
DQ7T/DIFFOUT_T21n
DQ7T/DIFFOUT_T23p
DQ7T/DIFFOUT_T23n
DQ8T/DIFFOUT_T25p
DQ8T/DIFFOUT_T25n
DQ8T/DIFFIO_RX_T13p
DQ8T/DIFFIO_RX_T13n
DQ9T/DIFFOUT_T27p
DQ9T/DIFFOUT_T27n
DQ9T/DIFFOUT_T29p
DQ9T/DIFFOUT_T29n
DQ10T/DIFFOUT_T31p
DQ10T/DIFFOUT_T31n
DQ10T/DIFFIO_RX_T16p
DQ10T/DIFFIO_RX_T16n
DQS7T/DIFFIO_RX_T11p
DQSn7T/DIFFIO_RX_T11n
DQS8T/DIFFIO_RX_T12p
DQSn8T/DIFFIO_RX_T12n
DQS9T/DIFFIO_RX_T14p
DQSn9T/DIFFIO_RX_T14n
DQS10T/DIFFIO_RX_T15p
DQSn10T/DIFFIO_RX_T15n
Bank 7C
DQ11T/DIFFOUT_T33p
DQ11T/DIFFOUT_T33n
DQ11T/DIFFOUT_T35p
DQ11T/DIFFOUT_T35n
DQ12T/DIFFOUT_T37p
DQ12T/DIFFOUT_T37n
DQ12T/DIFFIO_RX_T19p
DQ12T/DIFFIO_RX_T19n
DQ13T/DIFFOUT_T39p
DQ13T/DIFFOUT_T39n
DQ13T/DIFFOUT_T41p
DQ13T/DIFFOUT_T41n
DQS13T/DIFFIO_RX_T20p
DQSn13T/DIFFIO_RX_T20n
DQS11T/DIFFIO_RX_T17p
DQSn11T/DIFFIO_RX_T17n
DQS12T/DIFFIO_RX_T18p
DQSn12T/DIFFIO_RX_T18n
DIFFIO_RX_T21p
DIFFIO_RX_T21n
DIFFIO_RX_T22p
DIFFIO_RX_T22n
P17
P16
M17
N17
L16
K17
J17
H17
QDR2TOP1_D4
QDR2TOP1_D0
QDR2TOP1_D1
QDR2TOP1_D2
QDR2TOP1_D5
QDR2TOP1_D3
QDR2TOP1_BWSn1
QDR2TOP1_BWSn0
N16
M16
K16
J16
QDR2TOP1_K_P
QDR2TOP1_K_N
QDR2TOP1_D6
QDR2TOP1_D7
J18
R18
P18
H19
QDR2TOP1_A15
QDR2TOP1_A13
QDR2TOP1_A9
QDR2TOP1_A1
B17
A17
QDR2TOP1_A18
QDR2TOP1_A2
B19
A18
D19
C19
DDR3TOP_CASn
QDR2TOP1_A3
DDR3TOP_A0
DDR3TOP_WEn
QDR2TOP0_RPSn
QDR2TOP0_A5
QDR2TOP0_A19
QDR2TOP0_A3
QDR2TOP0_A7
QDR2TOP0_A10
QDR2TOP0_A14
QDR2TOP0_A15
C27
D27
A28
A27
B31
A31
C29
C30
QDR2TOP0_A17
QDR2TOP0_A13
QDR2TOP0_A6
QDR2TOP0_A9
C28
B28
B29
A29
QDR2TOP0_Q11
QDR2TOP0_Q12
QDR2TOP0_Q7
QDR2TOP0_Q10
QDR2TOP0_Q13
QDR2TOP0_QVLD
QDR2TOP0_Q5
QDR2TOP0_Q6
D28
F27
F28
E28
G27
H26
J26
G29
QDR2TOP0_Q8
QDR2TOP0_Q9
QDR2TOP0_CQ_P
QDR2TOP0_A16
E29
D29
H28
G28
QDR2TOP0_BWSn1
QDR2TOP0_D14
QDR2TOP0_WPSn
QDR2TOP0_A18
QDR2TOP0_D12
QDR2TOP0_D10
QDR2TOP0_D9
QDR2TOP0_D11
J25
M24
K24
J24
M23
N22
P22
R22
QDR2TOP0_BWSn0
QDR2TOP0_D13
QDR2TOP0_K_P
QDR2TOP0_K_N
L23
K23
P23
N23
DDR3TOP_A9
DDR3TOP_A3
QDR2TOP0_A0
DDR3TOP_A13
DDR3TOP_DQ12
DDR3TOP_DQ8
DDR3TOP_DQ10
DDR3TOP_DQ14
M21
R20
N21
M22
G22
K22
J22
H22
DDR3TOP_CK_P
DDR3TOP_CK_N
DDR3TOP_DQS_P1
DDR3TOP_DQS_N1
D24
C24
J23
H23
E
11 DDR3TOP_DQS_N[1:0]
Stratix IV GX Bank 8
Bank 8A
DQ21T/DIFFOUT_T80p
DQ21T/DIFFOUT_T80n
DQ21T/DIFFIO_RX_T40p
DQ21T/DIFFIO_RX_T40n
DQ22T/DIFFOUT_T82p
DQ22T/DIFFOUT_T82n
DQ22T/DIFFOUT_T84p
DQ22T/DIFFOUT_T84n
11 DDR3TOP_DM[1:0]
DQ25T/DIFFOUT_T92p
DQ25T/DIFFOUT_T92n
DQ25T/DIFFIO_RX_T46p
DQ25T/DIFFIO_RX_T46n
DQ26T/DIFFOUT_T94p
DQ26T/DIFFOUT_T94n
DQ26T/DIFFOUT_T96p
DQ26T/DIFFOUT_T96n
DQS21T/DIFFIO_RX_T41p
DQS25T/DIFFIO_RX_T47p
DQSn21T/DIFFIO_RX_T41n
DQSn25T/DIFFIO_RX_T47n
DQS22T/DIFFIO_RX_T42p RUP8A/DQS26T/DIFFIO_RX_T48p
DQSn22T/DIFFIO_RX_T42n RDN8A/DQSn26T/DIFFIO_RX_T48n
DQ23T/DIFFOUT_T86p
DQ23T/DIFFOUT_T86n
DQ23T/DIFFIO_RX_T43p
DQ23T/DIFFIO_RX_T43n
DQ24T/DIFFOUT_T88p
DQ24T/DIFFOUT_T88n
DQ24T/DIFFOUT_T90p
DQ24T/DIFFOUT_T90n
DIFFIO_RX_T39p
DIFFIO_RX_T39n
DIFFOUT_T78p
DIFFOUT_T78n
L25
K28
L26
K26
M25
N25
P25
M27
QDR2TOP0_Q16
QDR2TOP0_Q1
QDR2TOP0_Q2
QDR2TOP0_Q4
QDR2TOP0_Q17
QDR2TOP0_Q15
QDR2TOP0_Q14
QDR2TOP0_Q0
K27
J27
P26
N26
QDR2TOP0_CQ_N
S4VCCIO_B7B8
QDR2TOP0_Q3
49.9
R183
49.9
R176
G26
F26
QDR2TOP0_A2
QDR2TOP0_A4
P24
R24
QDR2TOP0_A1
QDR2TOP0_A12
9,11 DDR3TOP_A[14:0]
11 DDR3TOP_BA[2:0]
DQS14T/DIFFIO_RX_T29p
DQSn14T/DIFFIO_RX_T29n
DQS15T/DIFFIO_RX_T31p
DQSn15T/DIFFIO_RX_T31n
11 DDR3TOP_WEn
11 DDR3TOP_RASn
D
14 QDR2TOP0_D[17:0]
14 QDR2TOP0_Q[17:0]
DQ19T/DIFFOUT_T72n
DQ19T/DIFFOUT_T72p
DQ19T/DIFFIO_RX_T36p
DQ19T/DIFFIO_RX_T36n
DQ20T/DIFFOUT_T74n
DQ20T/DIFFOUT_T74p
DQ20T/DIFFOUT_T76n
DQ20T/DIFFOUT_T76p
DQS19T/DIFFIO_RX_T37p
DQSn19T/DIFFIO_RX_T37n
DQS20T/DIFFIO_RX_T38p
DQSn20T/DIFFIO_RX_T38n
Bank 8C
DQ14T/DIFFOUT_T56p
DQ14T/DIFFOUT_T56n
DQ14T/DIFFOUT_T58p
DQ14T/DIFFOUT_T58n
DQ15T/DIFFOUT_T60p
DQ15T/DIFFOUT_T60n
DQ15T/DIFFIO_RX_T30p
DQ15T/DIFFIO_RX_T30n
11 DDR3TOP_CSn
11 DDR3TOP_ODT
9,14 QDR2TOP0_A[19:0]
Bank 8B
DQS17T/DIFFIO_RX_T34p
DQSn17T/DIFFIO_RX_T34n
DQS18T/DIFFIO_RX_T35p
DQSn18T/DIFFIO_RX_T35n
DDR3TOP_CKE
DDR3TOP_CK_N
DDR3TOP_CK_P
DDR3TOP_CASn
QDRII TOP0 INTERFACE
DQS23T/DIFFIO_RX_T44p
DQSn23T/DIFFIO_RX_T44n
DQS24T/DIFFIO_RX_T45p
DQSn24T/DIFFIO_RX_T45n
DQ17T/DIFFOUT_T66n
DQ17T/DIFFOUT_T66p
DQ17T/DIFFIO_RX_T33p
DQ17T/DIFFIO_RX_T33n
DQ18T/DIFFOUT_T68n
DQ18T/DIFFOUT_T68p
DQ18T/DIFFOUT_T70n
DQ18T/DIFFOUT_T70p
11
11
11
11
DQ16T/DIFFOUT_T62p
DQ16T/DIFFOUT_T62n
DQ16T/DIFFOUT_T64p
DQ16T/DIFFOUT_T64n
DQS16T/DIFFIO_RX_T32p
DQSn16T/DIFFIO_RX_T32n
DIFFIO_RX_T27p
DIFFIO_RX_T27n
DIFFIO_RX_T28p
DIFFIO_RX_T28n
D25
G25
G24
F24
B25
C25
D26
A26
QDR2TOP0_D4
QDR2TOP0_D1
QDR2TOP0_D16
QDR2TOP0_D15
QDR2TOP0_D17
QDR2TOP0_D6
QDR2TOP0_D3
QDR2TOP0_D8
F25
E25
C26
B26
QDR2TOP0_D0
QDR2TOP0_D2
QDR2TOP0_D5
QDR2TOP0_D7
E22
D22
G23
F23
DDR3TOP_DQ11
DDR3TOP_DQ9
DDR3TOP_DM1
DDR3TOP_DQ13
E23
D23
DDR3TOP_BA1
DDR3TOP_DQ15
D21
C22
A25
A24
DDR3TOP_A4
DDR3TOP_A1
DDR3TOP_CKE
DDR3TOP_RASn
14
14
14
14
14
14
14
QDR2TOP0_QVLD
QDR2TOP0_CQ_P
QDR2TOP0_CQ_N
QDR2TOP0_K_P
QDR2TOP0_K_N
QDR2TOP0_BWSn0
QDR2TOP0_BWSn1
14
14
14
14
QDR2TOP1_WPSn
QDR2TOP1_RPSn
QDR2TOP0_RPSn
QDR2TOP0_WPSn
C
QDRII TOP1 INTERFACE
9,14 QDR2TOP1_A[19:0]
14 QDR2TOP1_D[17:0]
14 QDR2TOP1_Q[17:0]
14
14
14
14
14
14
14
QDR2TOP1_CQ_P
QDR2TOP1_CQ_N
QDR2TOP1_BWSn0
QDR2TOP1_BWSn1
QDR2TOP1_K_P
QDR2TOP1_K_N
QDR2TOP1_QVLD
B
EP4SGX230KF40_F1517
Version = 0.4 Preliminary
EP4SGX230KF40_F1517
Version = 0.4 Preliminary
A
A
Altera Corporation, 9330 Scranton Rd, San Diego, CA 92121
Title
Copyright (c) 2009 Altera Corporation. All Rights Reserved.
Stratix IV GX FPGA Development Kit Board
Size
B
Date:
8
7
6
5
4
3
Document Number
Rev
150-0310901-B1 (6XX-41284R )
Friday, May 01, 2009
2
Sheet
7
B
of
1
29
7
6
PCIE_RX_P0
PCIE_RX_N0
PCIE_RX_P1
PCIE_RX_N1
PCIE_RX_P2
PCIE_RX_N2
PCIE_RX_P3
PCIE_RX_N3
E
PCIE_REFCLK_P
PCIE_REFCLK_N
PCIE_RX_P4
PCIE_RX_N4
PCIE_RX_P5
PCIE_RX_N5
PCIE_RX_P6
PCIE_RX_N6
PCIE_RX_P7
PCIE_RX_N7
AU38
AU39
AR38
AR39
AJ38
AJ39
AG38
AG39
3
3
3
3
3
3
3
3
AN38
AN39
AL38
AL39
3
3
AE38
AE39
AC38
AC39
U38
U39
R38
R39
3
3
3
3
3
3
3
3
D
AA38
AA39
W38
W39
HSMB_RX_P0
HSMB_RX_N0
HSMB_RX_P1
HSMB_RX_N1
HSMB_RX_P2
HSMB_RX_N2
HSMB_RX_P3
HSMB_RX_N3
C
N38
N39
L38
L39
E38
E39
C38
C39
12
12
12
12
12
12
12
12
CLK_155_P 9
CLK_155_N 9
CLKINLT_100_P 9
CLKINLT_100_N 9
J38
J39
G38
G39
HSMA_RX_P0
HSMA_RX_N0
HSMA_RX_P1
HSMA_RX_N1
HSMA_RX_P2
HSMA_RX_N2
HSMA_RX_P3
HSMA_RX_N3
AU2
AU1
AR2
AR1
AJ2
AJ1
AG2
AG1
12
12
12
12
12
12
12
12
AN2
AN1
AL2
AL1
CLK_148_P 9
CLK_148_N 9
HSMA_RX_P4
HSMA_RX_N4
HSMA_RX_P5
HSMA_RX_N5
HSMA_RX_P6
HSMA_RX_N6
HSMA_RX_P7
HSMA_RX_N7
B
AE2
AE1
AC2
AC1
U2
U1
R2
R1
12
12
12
12
12
12
12
12
AA2
AA1
W2
W1
CLK_156_P 9
CLK_156_N 9
10.0K
R205
10.0K
R131
SDI_RX_P 20
SDI_RX_N 20
HSMB_RX_P5
HSMB_RX_N5
HSMB_RX_P4
HSMB_RX_N4
N2
N1
L2
L1
E2
E1
C2
C1
12
12
12
12
J2
J1
G2
G1
CLK_125_P0 9
CLK_125_N0 9
CLKINRT_100_P 9
CLKINRT_100_N 9
A
2.00K
2.00K
R206
R192
AW38
A34
RREF_L0
RREF_L1
7
3
2
Stratix IV GX Transceivers I/O and Power
1
Stratix IV GX Transceivers
GXB_RX_L0p
GXB_RX_L0n
GXB_RX_L1p
GXB_RX_L1n
GXB_RX_L2p
GXB_RX_L2n
GXB_RX_L3p
GXB_RX_L3n
Bank QL0
REFCLK_L0p/GXB_CMURX_L0p
REFCLK_L0n/GXB_CMURX_L0n
REFCLK_L1p/GXB_CMURX_L1p
REFCLK_L1n/GXB_CMURX_L1n
GXB_RX_L4p
GXB_RX_L4n
GXB_RX_L5p
GXB_RX_L5n
GXB_RX_L6p
GXB_RX_L6n
GXB_RX_L7p
GXB_RX_L7n
Bank QL1
REFCLK_L2p/GXB_CMURX_L2p
REFCLK_L2n/GXB_CMURX_L2n
REFCLK_L3p/GXB_CMURX_L3p
REFCLK_L3n/GXB_CMURX_L3n
GXB_RX_L8p
GXB_RX_L8n
GXB_RX_L9p
GXB_RX_L9n
GXB_RX_L10p
GXB_RX_L10n
GXB_RX_L11p
GXB_RX_L11n
Bank QL2
REFCLK_L4p/GXB_CMURX_L4p
REFCLK_L4n/GXB_CMURX_L4n
REFCLK_L5p/GXB_CMURX_L5p
REFCLK_L5n/GXB_CMURX_L5n
GXB_RX_R0p
GXB_RX_R0n
GXB_RX_R1p
GXB_RX_R1n
GXB_RX_R2p
GXB_RX_R2n
GXB_RX_R3p
GXB_RX_R3n
Bank QR0
REFCLK_R0p/GXB_CMURX_R0p
REFCLK_R0n/GXB_CMURX_R0n
REFCLK_R1p/GXB_CMURX_R1p
REFCLK_R1n/GXB_CMURX_R1n
GXB_RX_R4p
GXB_RX_R4n
GXB_RX_R5p
GXB_RX_R5n
GXB_RX_R6p
GXB_RX_R6n
GXB_RX_R7p
GXB_RX_R7n
Bank QR1
REFCLK_R2p/GXB_CMURX_R2p
REFCLK_R2n/GXB_CMURX_R2n
REFCLK_R3p/GXB_CMURX_R3p
REFCLK_R3n/GXB_CMURX_R3n
GXB_RX_R8p
GXB_RX_R8n
GXB_RX_R9p
GXB_RX_R9n
GXB_RX_R10p
GXB_RX_R10n
GXB_RX_R11p
GXB_RX_R11n
Bank QR2
REFCLK_R4p/GXB_CMURX_R4p
REFCLK_R4n/GXB_CMURX_R4n
REFCLK_R5p/GXB_CMURX_R5p
REFCLK_R5n/GXB_CMURX_R5n
RREF_L0
RREF_L1
EP4SGX230KF40_F1517
8
4
GXB_TX_L0p
GXB_TX_L0n
GXB_TX_L1p
GXB_TX_L1n
GXB_TX_L2p
GXB_TX_L2n
GXB_TX_L3p
GXB_TX_L3n
GXB_CMUTX_L0p
GXB_CMUTX_L0n
GXB_CMUTX_L1p
GXB_CMUTX_L1n
GXB_TX_L4p
GXB_TX_L4n
GXB_TX_L5p
GXB_TX_L5n
GXB_TX_L6p
GXB_TX_L6n
GXB_TX_L7p
GXB_TX_L7n
GXB_CMUTX_L2p
GXB_CMUTX_L2n
GXB_CMUTX_L3p
GXB_CMUTX_L3n
GXB_TX_L8p
GXB_TX_L8n
GXB_TX_L9p
GXB_TX_L9n
GXB_TX_L10p
GXB_TX_L10n
GXB_TX_L11p
GXB_TX_L11n
GXB_CMUTX_L4p
GXB_CMUTX_L4n
GXB_CMUTX_L5p
GXB_CMUTX_L5n
GXB_TX_R0p
GXB_TX_R0n
GXB_TX_R1p
GXB_TX_R1n
GXB_TX_R2p
GXB_TX_R2n
GXB_TX_R3p
GXB_TX_R3n
GXB_CMUTX_R0p
GXB_CMUTX_R0n
GXB_CMUTX_R1p
GXB_CMUTX_R1n
GXB_TX_R4p
GXB_TX_R4n
GXB_TX_R5p
GXB_TX_R5n
GXB_TX_R6p
GXB_TX_R6n
GXB_TX_R7p
GXB_TX_R7n
GXB_CMUTX_R2p
GXB_CMUTX_R2n
GXB_CMUTX_R3p
GXB_CMUTX_R3n
GXB_TX_R8p
GXB_TX_R8n
GXB_TX_R9p
GXB_TX_R9n
GXB_TX_R10p
GXB_TX_R10n
GXB_TX_R11p
GXB_TX_R11n
GXB_CMUTX_R4p
GXB_CMUTX_R4n
GXB_CMUTX_R5p
GXB_CMUTX_R5n
RREF_R0
RREF_R1
AT36
AT37
AP36
AP37
AH36
AH37
AF36
AF37
3
3
3
3
3
3
3
3
PCIE_TX_P0
PCIE_TX_N0
PCIE_TX_P1
PCIE_TX_N1
PCIE_TX_P2
PCIE_TX_N2
PCIE_TX_P3
PCIE_TX_N3
U13Q
S4VCCA_GXB
(3.0V)
AM36
AM37
AK36
AK37
AF35
M35
AF5
M5
3
3
3
3
3
3
3
3
Y35
T35
AD35
Y5
T5
AD5
PCIE_TX_P4
PCIE_TX_N4
PCIE_TX_P5
PCIE_TX_N5
PCIE_TX_P6
PCIE_TX_N6
PCIE_TX_P7
PCIE_TX_N7
V35
P35
AB35
V5
P5
AB5
Y36
Y37
V36
V37
M36
M37
K36
K37
D36
D37
B36
B37
12
12
12
12
12
12
12
12
HSMB_TX_P0
HSMB_TX_N0
HSMB_TX_P1
HSMB_TX_N1
HSMB_TX_P2
HSMB_TX_N2
HSMB_TX_P3
HSMB_TX_N3
Receiver Analog Power
VCCR_L
VCCR_L
VCCR_L
VCCR_R
VCCR_R
VCCR_R
VCCL_GXBL0
VCCL_GXBL0
VCCL_GXBL1
VCCL_GXBL1
VCCL_GXBL2
VCCL_GXBL2
VCCL_GXBR0
VCCL_GXBR0
VCCL_GXBR1
VCCL_GXBR1
VCCL_GXBR2
VCCL_GXBR2
1.1V
Transmitter Analog Power Transmitter Clock Power
VCCT_L
VCCT_L
VCCT_L
VCCT_R
VCCT_R
VCCT_R
1.4V
OR
1.5V
1.1V
VCCH_GXBL0
VCCH_GXBL1
VCCH_GXBR0
VCCH_GXBL2
VCCH_GXBR1
VCCH_GXBR2
PCI/IP Digital Power
0.9V
H36
H37
F36
F37
VCCHIP_L
VCCHIP_L
VCCHIP_L
VCCHIP_R
VCCHIP_R
VCCHIP_R
AE33
AD33
Y33
AA33
T33
U33
AD7
AE7
AA7
Y7
T7
U7
AE34
AA34
AE6
U34
AA6
U6
Y31
W31
AA31
Y9
W9
AA9
S4VCCH_GXB
D
(1.4V)
S4VCC
EP4SGX230KF40_F1517
Version = 0.4 Preliminary
AT4
AT3
AP4
AP3
AH4
AH3
AF4
AF3
12
12
12
12
12
12
12
12
HSMA_TX_P0
HSMA_TX_N0
HSMA_TX_P1
HSMA_TX_N1
HSMA_TX_P2
HSMA_TX_N2
HSMA_TX_P3
HSMA_TX_N3
12
12
12
12
12
12
12
12
HSMA_TX_P4
HSMA_TX_N4
HSMA_TX_P5
HSMA_TX_N5
HSMA_TX_P6
HSMA_TX_N6
HSMA_TX_P7
HSMA_TX_N7
C
AM4
AM3
AK4
AK3
AD4
AD3
AB4
AB3
T4
T3
P4
P3
B
Y4
Y3
V4
V3
M4
M3
K4
K3
D4
D3
B4
B3
1
20
20
12
12
12
12
SMA_TX_P
SMA_TX_N
SDI_TX_P
SDI_TX_N
HSMB_TX_P5
HSMB_TX_N5
HSMB_TX_P4
HSMB_TX_N4
J12
1
J13
H4
H3
F4
F3
AW2
A6
A
Altera Corporation, 9330 Scranton Rd, San Diego, CA 92121
Title
RREF_R0
RREF_R1
R135
R143
Size
B
Date:
5
Copyright (c) 2009 Altera Corporation. All Rights Reserved.
Stratix IV GX FPGA Development Kit Board
2.00K
2.00K
Version = 0.4 Preliminary
6
1.1V
E
S4VCCL_GXB
Transceiver Clock Power
High Voltage Power
2.5V
OR
3.0V
VCCA_L
VCCA_L
VCCA_R
VCCA_R
S4VCC_GXB
AD36
AD37
AB36
AB37
T36
T37
P36
P37
Stratix IV GX
Transceiver Power
2
3
4
5
U13P
5
2
3
4
5
8
4
3
Document Number
Rev
150-0310901-B1 (6XX-41284R )
Friday, May 01, 2009
2
Sheet
8
B
of
1
29
8
7
3.3V
7
8
OE
VCC
SDA
CLK-
SCL
3
CLK+
GND
NC
100MHz
Si570 Programmable Oscillator
Use Clock Control GUI
(Default 100MHz)
1 CLKIN_SMA_P
LTI-SASF546-P26-X1
5
4
3
2
J15
100, 1%
100, 1%
D
100M_OSC_P
5
1
100M_OSC_N
CLKIN_SMA_CP
CLKIN_SMA_CN
R255
R256
3.3V
5
4
3
2
LVPECL INPUT CLOCK
Can also operate single-ended
1.0V pk-pk MAX
SDI_CLK148_UP 6
R90
SDI_CLK148_DN 6
R91
CLK148_EN 17
Active Low Enable From EPM2210
Q0p
Q0n
Q1p
Q1n
PCLKp
PCLKn
C1060
0.1uF
0.1uF
2.2uF
SENSE_SMB_CLK
USER_LED9
HSMA_CLK_IN0
HSMB_CLK_IN0
20
19
CLKINTOP_100_P
CLKINTOP_100_N
17
16
CLKINBOT_100_P
CLKINBOT_100_N
C914
0.1uF
8
R216
DNI
C915
0.1uF 8
15
14
Q2p
Q2n
CLK_SEL
ICS8543
12
11
Q3p
Q3n
C975
DNI
R217
0.1uF
C976
0.1uF
To REFCLK
CLKINRT_100_P
R247
R245
CLKIN_SMA_CP
CLKIN_SMA_CN
124
124
R246
R248
8
CLKINLT_100_P
8
CLKINLT_100_N
4.99K
4.99K
SDI_CLK_CTL
1
OUTQp
OUTQn
CTL V
2
R89
180K
C
X3
VCC
ENABLE
GND
5
4
C909
C1015
0.1uF
0.1uF
CLK_148_CP C266 0.1uF 8
CLK_148_P
CLK_148_CN C265 0.1uF 8
CLK_148_N
3
C245
0.1uF
C243
0.1uF
R122
R179
R132
R170
HSMA_CLK_IN_P1
CLKINBOT_100_P
HSMB_CLK_IN_P1
CLKINTOP_100_P
2.5V
LVDS
LVDS Requires 100ohm Rp OCT in FPGA
148.5MHz
C244
0.001uF
100, 1%
100, 1%
100, 1%
100, 1%
HSMA_CLK_IN_N1
CLKINBOT_100_N
HSMB_CLK_IN_N1
CLKINTOP_100_N
R213 R212
CLK155_EN 17
2.5V
From EPM2210
1
2
6
B
C935
C995
0.1uF
10uF
X7
EN
NC
VCC
OUT
OUTn
4
CLK_155_CP
5
CLK_155_CN
240
3
GND
240
C937
0.1uF 8
CLK_155_P
C936
0.1uF 8
CLK_155_N
LVPECL
R219 R218 LVPECL Requires 100ohm Rp OCT in FPGA
NIOS CPU Clock
155.52MHz
62.0
CLK50_EN 17 1
62.0
2
From EPM2210
CLK156_EN 17
From EPM2210
2.5V
1
2
6
C262
C242
0.1uF
10uF
CLK125_EN 17
A
From EPM2210
2.5V
C263
0.1uF
10uF
EN
NC
VCC
OUT
OUTn
4
CLK_156_CP
C256
0.1uF 8
CLK_156_P
5
CLK_156_CN
C257
0.1uF 8
CLK_156_N
3
GND
1
2
EN
OUT
NC
OUTn
VCC
4
CK_125_P
5
CK_125_N
3
GND
125.0MHz
Bank 1C
CLK0p/DIFFIO_RX_L22p
CLK0n/DIFFIO_RX_L22n
CLK1p (Input)
CLK1n (Input)
PLL_L2_FB_CLKOUT0p/DIFFIO_TX_L22p
PLL_L2_CLKOUT0n/DIFFIO_TX_L22n
CLK2p/DIFFIO_RX_L23p
CLK2n/DIFFIO_RX_L23n
CLK3p (Input)
CLK3n (Input)
PLL_L3_FB_CLKOUT0p/DIFFIO_TX_L23p
PLL_L3_CLKOUT0n/DIFFIO_TX_L23n
CLKINBOT_100_P
CLKINBOT_100_N
AR22
AT21
AV22
AW22
DDR3BOT_WEn
DDR3BOT_RASn
DDR3BOT_CASn
DDR3BOT_CKE
AW20
AW21
AV19
AW19
Bank 2C
Bank 3C
CLK4p/DIFFIO_RX_B24p
CLK4n/DIFFIO_RX_B24n
CLK5p
CLK5n
5
13
14
15
16
11
12
9
10
PLL_B1_CLKOUT0p
PLL_B1_CLKOUT0n
PLL_B1_CLKOUT3
PLL_B1_CLKOUT4
PLL_B1_FBp/CLKOUT1/DIFFIO_RX_B23p
PLL_B1_FBn/CLKOUT2/DIFFIO_RX_B23n
X8
EN
VCC
GND
OUT
HSMA_CLK_IN_P1
HSMA_CLK_IN_N1
HSMA_CLK_IN_P2
HSMA_CLK_IN_N2
AC6
AC5
AF6
AE5
HSMB_CLK_IN_P1
HSMB_CLK_IN_N1
HSMB_CLK_IN_P2
HSMB_CLK_IN_N2
AB6
AA5
W6
W5
CLKINTOP_100_P
CLKINTOP_100_N
DDR3TOP_A14
DDR3TOP_A11
A21
A20
B20
A19
QDR2TOP0_DOFFn
QDR2TOP0_ODT
DDR3TOP_A10
DDR3TOP_A12
B22
A22
B23
A23
PLL_B2_CLKOUT0p
PLL_B2_CLKOUT0n
PLL_B2_CLKOUT3
PLL_B2_CLKOUT4
PLL_B2_FBp/CLKOUT1/DIFFIO_RX_B26p
PLL_B2_FBn/CLKOUT2/DIFFIO_RX_B26n
CLK8p (Input)
CLK8n (Input)
CLK9p/DIFFIO_RX_R22p
CLK9n/DIFFIO_RX_R22n
PLL_R3_FB_CLKOUT0p/DIFFIO_TX_R22p
PLL_R3_CLKOUT0n/DIFFIO_TX_R22n
CLK10p (Input)
CLK10n (Input)
CLK11p/DIFFIO_RX_R23p
CLK11n/DIFFIO_RX_R23n
PLL_R2_FB_CLKOUT0p/DIFFIO_TX_R23p
PLL_R2_CLKOUT0n/DIFFIO_TX_R23n
Bank 5C
Bank 6C
17
50MHz
CLKIN_50
C1062
LVDS
2.2uF
C979 To FPGA and
EPM2210
0.1uF
U55
Bank 8C
CLK14p/DIFFIO_RX_T25p
CLK14n/DIFFIO_RX_T25n
CLK15p
CLK15n
VCC
VCC
VCC
VCC
VCC
D
VTD
VTD
D
Q0
Q0
Q1
Q1
1
2
CK_125_P0
CK_125_N0
3
4
CLK_125_P1
CLK_125_N1
6
7
8
17
2.5V
0.1uF 8
CLK_125_P0
C339
0.1uF 8
CLK_125_N0
PLL_T1_CLKOUT0p
PLL_T1_CLKOUT0n
PLL_T1_CLKOUT3
PLL_T1_CLKOUT4
PLL_T1_FBp/CLKOUT1/DIFFIO_RX_T26p
PLL_T1_FBn/CLKOUT2/DIFFIO_RX_T26n
EP4SGX230KF40_F1517
Version = 0.4 Preliminary
1
E
AG34
AG35
USER_DIPSW6
LTI-SASF546-P26-X1
AN21
AP21
AH20
AJ20
AT22
AU22
12 HSMA_CLK_IN_P[2:1]
12 HSMA_CLK_IN_N[2:1]
15
15
15
15
15
15
DDR3BOT_CASn
DDR3BOT_CKE
DDR3BOT_RSTn
DDR3BOT_CSn
DDR3BOT_WEn
DDR3BOT_RASn
NC
GND
GND
EP_GND
C1081
C1048
C1082
C1047
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
6
5
12 HSMB_CLK_IN_P[2:1]
HSMA_TX_D_P16
HSMA_TX_D_N16
W12
W11
HSMB_TX_D_P0
HSMB_TX_D_N0
P19
N19
L19
M19
D20
C20
DDR3TOP_A5
DDR3TOP_A2
QDR2TOP1_A6
QDR2TOP1_A14
QDR2TOP1_DOFFn
QDR2TOP1_ODT
M20
L20
N20
P20
G21
F21
DDR3TOP_A7
DDR3TOP_RSTn
QDR2TOP0_A11
QDR2TOP0_A8
DDR3TOP_A6
DDR3TOP_A8
B
14 QDR2TOP0_DOFFn
14 QDR2TOP0_ODT
14 QDR2TOP1_DOFFn
14 QDR2TOP1_ODT
7,11 DDR3TOP_A[14:0]
11 DDR3TOP_RSTn
17,25 SENSE_SMB_CLK
4,18 USER_DIPSW[7:0]
12 HSMB_CLK_IN_N[2:1]
4,10,18 USER_LED[15:0]
A
Altera Corporation, 9330 Scranton Rd, San Diego, CA 92121
Title
Copyright (c) 2009 Altera Corporation. All Rights Reserved.
Stratix IV GX FPGA Development Kit Board
12 HSMB_CLK_IN0
Size
B
4
AC11
AC10
D
4,18 USER_PB[2:0]
6,12 HSMB_TX_D_N[16:0]
C1046
DDR3BOT_CSn
DDR3BOT_RSTn
7,14 QDR2TOP1_A[19:0]
12 HSMA_CLK_IN0
LVDS Requires 100ohm Rp OCT in FPGA
AN20
AP20
AH18
AH19
AR20
AT20
7,14 QDR2TOP0_A[19:0]
DDR3 INTERFACE
6,12 HSMB_TX_D_P[16:0]
NB6L11SMNG
7
J9
USER_PB1
CLKOUT_SMA
QDRII & USER I/O INTERFACES
HSM INTERFACE
6,12 HSMA_TX_D_P[16:0]
C340
PLL_T2_CLKOUT0p
PLL_T2_CLKOUT0n
PLL_T2_CLKOUT3
PLL_T2_CLKOUT4
PLL_T2_FBp/CLKOUT1/DIFFIO_RX_T23p
PLL_T2_FBn/CLKOUT2/DIFFIO_RX_T23n
Date:
8
W32
W33
C
Bank 7C
CLK12p/DIFFIO_RX_T24p
CLK12n/DIFFIO_RX_T24n
CLK13p
CLK13n
2.5V
4
3
Bank 4C
CLK6p/DIFFIO_RX_B25p
CLK6n/DIFFIO_RX_B25n
CLK7p
CLK7n
6,12 HSMA_TX_D_N[16:0]
2.5V
X1
AF34
AE35
AC34
AC35
LVDS Requires 100ohm Rp OCT in FPGA
156.25MHz
6
C255
X2
1
Stratix IV GX Clocks
To REFCLK
Dedicated GX Reference Clocks
6
W34
W35
AB34
AA35
CLK_125_P1
CLK_125_N1
CLKIN_50
USER_DIPSW1
CLKINRT_100_N
3.3V
84.5
84.5
3.3V
From FPGA
6
7
CLK_SEL DIP Setting
OSC
'0' = ON
SMA
'1' = OFF
Board Settings DIP Switch
C1078
0.1uF
LVDS
CLKp
CLKn
CLK_SEL 17,18 3
C1077
0.1uF
1 CLKIN_SMA_N
LTI-SASF546-P26-X1
J14
OE
CLK_EN
4
5
LVDS
R244
100, 1%
4
U53
8
2
C1043
U13I
2
2
3
4
5
6
4.7K
4.7K
VDD
VDD
2
R249
R243
C912
3
1
9
13
X6
3.3V
10
18
C1039 C886
4
Stratix IV GX Clocks
2.5V
0.1uF 10uF
E
5
GND
GND
GND
From EPM2210
CLK100_EN 17
CLK100_SDA 17
CLK100_SCL 17
6
3
Document Number
Rev
150-0310901-B1 (6XX-41284R )
Friday, November 06, 2009
2
Sheet
9
B
of
1
29
8
7
6
5
4
3
Stratix IV GX Configuration
2
2.5V
2.5V
E
10K
10K
10K
10K
U13J
FPGA_DCLK 17
AR11
FPGA_nSTATUS 17
FPGA_nCONFIG 17
FPGA_CONF_DONE 17
AW35
AW36
AV35
LCD_DATA2
SDI_TX_SD_HDn 20
FPGA_CONFIG_D[7:0]
LCD_DATA[7:0]
USER_LED[15:0]
D
2.5V
17
4,18
4,9,18
CPU_RESETn 17,18
R31
V29
FPGA_CONFIG_D0
FPGA_CONFIG_D1
FPGA_CONFIG_D2
FPGA_CONFIG_D3
FPGA_CONFIG_D4
FPGA_CONFIG_D5
FPGA_CONFIG_D6
FPGA_CONFIG_D7
W30
W29
N35
P34
V27
W26
R35
R34
CPU_RESETn
USER_LED15
V34
U35
USER_LED11
V30
10K
10K
Stratix IV GX Configuration
DCLK
TCK
TMS
TDO
TDI
TRST
nSTATUS
nCONFIG
CONF_DONE
CLKUSR/DQ11L/DIFFIO_TX_L18n
CRC_ERROR/DQ13L/DIFFIO_TX_L21p
DATA0/DQ12L/DIFFIO_TX_L19n
DATA1/DQ12L/DIFFIO_TX_L19p
DATA2/DQSn12L/DIFFIO_RX_L19n
DATA3/DQS12L/DIFFIO_RX_L19p
DATA4/DQ12L/DIFFIO_TX_L20n
DATA5/DQ12L/DIFFIO_TX_L20p
DATA6/DQSn13L/DIFFIO_RX_L20n
DATA7/DQS13L/DIFFIO_RX_L20p
DEV_CLRn/DQ13L/DIFFIO_RX_L21p
DEV_OE/DQ13L/DIFFIO_RX_L21n
INIT_DONE/DQ13L/DIFFIO_TX_L21n
Bank 1C
ASDO
TEMPDIODEp
TEMPDIODEn
MSEL0
MSEL1
MSEL2
PORSEL
nCSO
nIO_PULLUP
other DQ pins are in bank 1 section
AN29
DNU
nCE
nCEO
G30
N27
F30
J29
A32
When Pins 4 & 8 are:
LOW --> Pins 5 & 7 = ON and Pins 2 & 10 = OFF
HIGH --> Pins 2 &10 = ON and Pins 5 & 7 = OFF
AN11
EPM2210_JTAG_EN
25 TEMPDIODE_P
25 TEMPDIODE_N
J11
H11
A8
2.5V
HSMA_JTAG_EN
2
4
3
1
2
3
4
2.5V
9
12 HSMB_JTAG_TDI
8
7
6
5
EPM2210_JTAG_EN
HSMA_JTAG_EN
HSMB_JTAG_EN
PCIE_JTAG_EN
U56
VCCA
A1
A2
A3
A4
NC1
EN
VCCY
Y1
Y2
Y3
Y4
NC2
GND
14
13
12
11
10
9
7
3
3
3
3
ISL54050
2.5V
JTAG Chain Control
SW6
R228
R229
R230
R231
1.00k
1.00k
1.00k
10.0K
2.5V
R251
100, 1%
C1023
ON = not-in-chain
OFF = in-chain
0.1uF
U54
0.1uF
1
C
5
C1024
HSMB_JTAG_EN
PCIE_JTAG_TCK
PCIE_JTAG_TDI
PCIE_JTAG_TDO
PCIE_JTAG_TMS
2
4
3
PCIE_JTAG_EN
10
8
6
A/C termination DNI by default
JTAG_TCK
USB Blaster Programming Header
(uses JTAG mode only)
JTAG_PCIE_TDI
R76
DNI
C88
JTAG_PCIE_TDO
9 19 JTAG_BLASTER_TDI
Do not enable, will break chain
Not Installed
B
12 HSMB_JTAG_TDO
7
DNI
ISL54050
DNI
B
R74
1.00k
2.5V
2.5V
USB_DISABLEn
12 HSMA_JTAG_TDI
10 12 HSMA_JTAG_TDO
8
3.3V_PCIE
C1084
PCIE_JTAG_EN
17 JTAG_EPM2210_TDO
7
6
AT11
JTAG_TCK
JTAG_PCIE_TDI
JTAG_PCIE_TDO
JTAG_TMS
JTAG_FPGA_TDO
D
AA20
1
2
3
4
5
6
8
1
5
AP29
AP11
AM11
TDA04H0SB1
0.1uF
U58
E
Logic 0 = pin 5 --> pin 3 (EPM2210 Bypass)
Logic 1 = pin 2 --> pin 3 (EPM2210 Enable)
EP4SGX230KF40_F1517
Version = 0.4 Preliminary
C
0.1uF
ISL54050 Switch Functions
JTAG_TCK
JTAG_TMS
17 JTAG_FPGA_TDO
19 JTAG_BLASTER_TDO
A9
E11
R254
100, 1%
C1022
R182
R188
OPEN
R195
R198
R199
R80
1
17,18,19 2
4
6
8
10
J8
12,17,19
1
3
12,17,19
5
7
9
JTAG_TCK
JTAG_BLASTER_TDI
JTAG_TMS
JTAG_BLASTER_TDO
R78
R85
1.00k
1.00k
70247-1051
A
A
Altera Corporation, 9330 Scranton Rd, San Diego, CA 92121
Title
Copyright (c) 2009 Altera Corporation. All Rights Reserved.
Stratix IV GX FPGA Development Kit Board
Size
B
Date:
8
7
6
5
4
3
Document Number
Rev
150-0310901-B1 (6XX-41284R )
Friday, November 06, 2009
2
Sheet
10
B
of
1
29
7
D
R215
HDMI_D0
HDMI_D1
HDMI_D2
HDMI_D3
HDMI_D4
HDMI_D5
HDMI_D6
HDMI_D7
B1
A1
B2
A2
B3
A3
B4
A4
HDMI_D8
HDMI_D9
HDMI_D10
HDMI_D11
HDMI_D12
HDMI_D13
HDMI_D14
HDMI_D15
B5
A5
B6
A6
B7
A7
B8
A8
HDMI_D16
HDMI_D17
HDMI_D18
HDMI_D19
HDMI_D20
HDMI_D21
HDMI_D22
HDMI_D23
B9
A9
B10
A10
C9
C10
D9
D10
HDMI_CLK 5
HDMI_DE 5
HDMI_HSYNC 5
HDMI_VSYNC 5
HDMI_EXT_SWG
HDMI_HPD
HDMI_SPDIF 5
HDMI_MCLK 5
887
HDMI_I2S0
HDMI_I2S1
HDMI_I2S2
HDMI_I2S3
C
5
5
5
5
AD9889B
HDMI_TX_D8
HDMI_TX_D9
HDMI_TX_D10
HDMI_TX_D11
HDMI_TX_D12
HDMI_TX_D13
HDMI_TX_D14
HDMI_TX_D15
HDMI_TX_D16
HDMI_TX_D17
HDMI_TX_D18
HDMI_TX_D19
HDMI_TX_D20
HDMI_TX_D21
HDMI_TX_D22
HDMI_TX_D23
D1
C2
C1
D2
J3
K3
E2
E1
3
2
HDMI_TX_CLK_P
HDMI_TX_CLK_N
HDMI_TX_P0
HDMI_TX_N0
HDMI_TX_P1
HDMI_TX_N1
HDMI_TX_P2
HDMI_TX_N2
HDMI_TX_INT
HDMI_TX_SDA
HDMI_TX_SCL
HDMI_TX_MDA
HDMI_TX_MCL
HDMI_TX_DDCSCL
HDMI_TX_DDCSDA
J11
K2
K1
TMDS_CLKp
TMDS_CLKn
K5
K4
K8
K7
J10
K10
TMDS_DATA_P0
TMDS_DATA_N0
TMDS_DATA_P1
TMDS_DATA_N1
TMDS_DATA_P2
TMDS_DATA_N2
H10
5
HDMI_INTn
F9
F10
E10
E9
G10
G9
5
5
HDMI_SDA
HDMI_SCL
18
7
9
8
4
6
5
1
3
2
10
12
11
DDCSCL
DDCSDA
HDMI 19-Pin Connector
5V_VCC
RESERVED_NC
TMDS_DATA_P0
DDC_CEC_GND
TMDS_DATA_N0
TMDS_DATA_SHLD0
SDA
TMDS_DATA_P1
SCL
TMDS_DATA_N1
CEC
TMDS_DATA_SHLD1
HOT_PLUG_DETECT
TMDS_DATA_P2
TMDS_DATA_N2
TMDS_DATA_SHLD2
2.00K
R184
HDMI_SDA
HDMI_SCL
2.00K
2.00K
R235
R234
E
17
5.0V
16
15
13
DDCSDA
DDCSCL
19
HDMI_HPD
HDMI_PVDD
HDMI-19-01-F-SM
HDMI_TX_I2S_0
HDMI_TX_I2S_1
HDMI_TX_I2S_2
HDMI_TX_I2S_3
HDMI_TX_SCLK
HDMI_TX_LRCLK
HDMI_TX_PD_A0
7 DDR3TOP_BA[2:0]
7 DDR3TOP_DM[1:0]
7 DDR3TOP_DQS_P[1:0]
HDMI_DVDD
B
HDMI_PVDD
7 DDR3TOP_DQ[15:0]
U25B
J2
J5
J8
K9
AVDD
AVDD
AVDD
AVDD
D5
D6
D7
E7
DVDD
DVDD
DVDD
DVDD
G4
G5
J1
PVDD
PVDD
PVDD
240
AD9889B
DDR3TOP_CK_P
100, 1%
Place near HDMI
A
HDMI_DVDD
DDR3TOP_CK_N
R166
Place near DDR3 (U15)
1.5V
HDMI_AVDD
R175
7,9 DDR3TOP_A[14:0]
D4
J4
G6
J6
E4
K6
F7
G7
H9
J9
F4
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
10.0K
R79
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
DDR3TOP_A0
DDR3TOP_A1
DDR3TOP_A2
DDR3TOP_A3
DDR3TOP_A4
DDR3TOP_A5
DDR3TOP_A6
DDR3TOP_A7
DDR3TOP_A8
DDR3TOP_A9
DDR3TOP_A10
DDR3TOP_A11
DDR3TOP_A12
7 DDR3TOP_DQS_N[1:0]
AD9889B
R238
R242
DDR3TOP_DM0
DDR3TOP_DM1
E7
D3
DDR3TOP_CSn 7
DDR3TOP_WEn 7
DDR3TOP_RASn 7
DDR3TOP_CASn 7
L2
L3
J3
K3
C968
C990
C992
C988
C966
C965
C989
C967
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
C548
C547
C546
C545
C631
C544
C632
C629
C630
C677
C676
C678
0.47uF
0.47uF
0.47uF
0.47uF
0.47uF
0.47uF
0.1uF
0.01uF
0.1uF
0.01uF
0.01uF
4.7nF
CKE
CK_P
CK_N
DM0
DM1
CS
WE
RAS
CAS
M2
DDR3TOP_BA0
N8
DDR3TOP_BA1
M3
DDR3TOP_BA2
DDR3TOP_RSTn 9 T2
DDR3TOP_ODT 7 K1
L8
DDR3TOP_ZQ
VREF_B7B8
H1
M8
C687
B2
D9
0.1uF
G7
K2
K8
N1
N9
R1
R9
1.5V
A1
A8
C1
C9
D2
E9
F1
H2
H9
HDMI_PVDD
DDR3 Device
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BCn
DDR3TOP_CKE 7 K9
DDR3TOP_CK_P 7 J7
DDR3TOP_CK_N 7 K7
AD9889B
HDMI_AVDD
2.00K
2.00K
U14
TMDS_CLK_P
TMDS_CLK_N
TMDS_DATA_SHLD_CLK
S4VCCIO_B3A
HDMI_INTn
14
HDMI_TX_CLK
HDMI_TX_DE
HDMI_TX_HSYNC
HDMI_TX_VSYNC
HDMI_TX_EXT_SWG
HDMI_TX_HPD
HDMI_TX_S_PDIF
HDMI_TX_MCLK
H2
H1
J7
1
5.0V
HDMI_TX_D0
HDMI_TX_D1
HDMI_TX_D2
HDMI_TX_D3
HDMI_TX_D4
HDMI_TX_D5
HDMI_TX_D6
HDMI_TX_D7
F2
F1
G2
G1
HDMI_SCLK 5
HDMI_LRCLK 5
4
HDMI Video Output & 128MB DDR3 Top Port
5
U25A
E
5
MTG1
MTG2
MTG3
MTG4
HDMI_D[23:0]
6
G1
G2
G3
G4
8
BA0
BA1
BA2
RESETn
ODT
ZQ
VREFDQ
VREFCA
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS0p
DQS0n
DQS1p
DQS1n
NC_J1
NC_J9
NC_L1
NC_L9
NC/A13
NC/A14
NC/A15
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
DDR3TOP_DQ0
DDR3TOP_DQ1
DDR3TOP_DQ2
DDR3TOP_DQ3
DDR3TOP_DQ4
DDR3TOP_DQ5
DDR3TOP_DQ6
DDR3TOP_DQ7
DDR3TOP_DQ8
DDR3TOP_DQ9
DDR3TOP_DQ10
DDR3TOP_DQ11
DDR3TOP_DQ12
DDR3TOP_DQ13
DDR3TOP_DQ14
DDR3TOP_DQ15
F3
G3
C7
B7
DDR3TOP_DQS_P0
DDR3TOP_DQS_N0
DDR3TOP_DQS_P1
DDR3TOP_DQS_N1
D
J1
J9
L1
L9
T3
T7
M7
C
DDR3TOP_A13
DDR3TOP_A14
B1
B9
D1
D8
E2
E8
F9
G1
G9
B
J2
J8
A9
M1
M9
B3
P1
P9
E1
T1
T9
G8
MT41J64M16LA
A
Altera Corporation, 9330 Scranton Rd, San Diego, CA 92121
Title
Copyright (c) 2009 Altera Corporation. All Rights Reserved.
Stratix IV GX FPGA Development Kit Board
Size
B
Date:
8
7
6
5
4
3
Document Number
Rev
150-0310901-B1 (6XX-41284R )
Wednesday, February 25, 2009
2
Sheet
11
B
of
1
29
6
5
J1
R257
R258
R259
R260
R261
R262
R263
R264
R265
R266
R267
R268
R269
R270
R271
R272
0 HSMA_TX_CP7 1
0 HSMA_TX_CN7 3
0 HSMA_TX_CP6 5
0 HSMA_TX_CN6 7
0 HSMA_TX_CP5 9
0 HSMA_TX_CN511
0 HSMA_TX_CP413
0 HSMA_TX_CN415
0 HSMA_TX_CP317
0 HSMA_TX_CN319
0 HSMA_TX_CP221
0 HSMA_TX_CN223
0 HSMA_TX_CP125
0 HSMA_TX_CN127
0 HSMA_TX_CP029
0 HSMA_TX_CN031
HSMA_SDA 6
33
JTAG_TCK 10,17,19 35
HSMA_JTAG_TDO 1037
HSMA_CLK_OUT0 4 39
HSMA_D0
HSMA_D2
HSMA_TX_D_P0
HSMA_TX_D_N0
D
HSMA_TX_D_P1
HSMA_TX_D_N1
HSMA_TX_D_P2
HSMA_TX_D_N2
HSMA_TX_D_P3
HSMA_TX_D_N3
HSMA_TX_D_P4
HSMA_TX_D_N4
HSMA_TX_D_P5
HSMA_TX_D_N5
HSMA_TX_D_P6
HSMA_TX_D_N6
C
HSMA_TX_D_P7
HSMA_TX_D_N7
HSMA_CLK_OUT_P1
HSMA_CLK_OUT_N1
HSMA_TX_D_P8
HSMA_TX_D_N8
HSMA_TX_D_P9
HSMA_TX_D_N9
HSMA_TX_D_P10
HSMA_TX_D_N10
HSMA_TX_D_P11
HSMA_TX_D_N11
B
HSMA_TX_D_P12
HSMA_TX_D_N12
HSMA_TX_D_P13
HSMA_TX_D_N13
HSMA_TX_D_P14
HSMA_TX_D_N14
HSMA_TX_D_P15
HSMA_TX_D_N15
HSMA_TX_D_P16
HSMA_TX_D_N16
12V
A
HSMA_CLK_OUT_P2
HSMA_CLK_OUT_N2
3.3V
C238
C246
10uF
10uF
3.3V
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
3.3V
47
49
3.3V
53
55
3.3V
59
61
3.3V
65
67
3.3V
71
73
3.3V
77
79
3.3V
83
85
3.3V
89
91
3.3V
95
97
3.3V
101
103
3.3V
107
109
3.3V
113
115
3.3V
119
121
3.3V
125
127
3.3V
131
133
3.3V
137
139
3.3V
143
145
3.3V
149
151
3.3V
155
157
3.3V
ASP-122953-01
28
2 48
4 68
6 88
8 10
8
10 12
8
12 14
8
14 16
8
16 18
8
18 20
8
20 22
8
22 24
8
24 26
8
26 28
8
28 30
8
30 32
8
32 34 6
34
10,17,19
36
36 3810
38 40 9
40
BANK 1
42
44
12V
48
50
12V
54
56
12V
60
62
12V
66
68
12V
72
74
12V
78
80
12V
84
86
12V
90
92
12V
96
98
12V
BANK 2
A
BANK 3
102
104
12V
108
110
12V
114
116
12V
120
122
12V
126
128
12V
132
134
12V
138
140
12V
144
146
12V
150
152
12V
156
158
PSNTn
GND_1_1
GND_1_2
GND_1_3
GND_1_4
GND_2_1
GND_2_2
GND_2_3
GND_2_4
GND_3_1
GND_3_2
GND_3_3
GND_3_4
E
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
HSMA_RX_P7
HSMA_RX_N7
HSMA_RX_P6
HSMA_RX_N6
HSMA_RX_P5
HSMA_RX_N5
HSMA_RX_P4
HSMA_RX_N4
HSMA_RX_P3
HSMA_RX_N3
HSMA_RX_P2
HSMA_RX_N2
HSMA_RX_P1
HSMA_RX_N1
HSMA_RX_P0
HSMA_RX_N0
HSMA_SCL
JTAG_TMS
HSMA_JTAG_TDI
HSMA_CLK_IN0
3
HSMC Port A & Port B
HSMB_TX_P5
HSMB_TX_N5
HSMB_TX_P4
HSMB_TX_N4
HSMB_TX_P3
HSMB_TX_N3
HSMB_TX_P2
HSMB_TX_N2
HSMB_TX_P1
HSMB_TX_N1
HSMB_TX_P0
HSMB_TX_N0
8
8
8
8
8
8
8
8
8
8
8
8
R273
R274
R275
R276
R277
R278
R279
R280
R281
R282
R283
R284
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
HSMA_D1
HSMA_D3
HSMB_D0
HSMB_D2
HSMA_RX_D_P0
HSMA_RX_D_N0
HSMB_TX_D_P0
HSMB_TX_D_N0
HSMA_RX_D_P1
HSMA_RX_D_N1
HSMB_TX_D_P1
HSMB_TX_D_N1
HSMA_RX_D_P2
HSMA_RX_D_N2
HSMB_TX_D_P2
HSMB_TX_D_N2
HSMA_RX_D_P3
HSMA_RX_D_N3
HSMB_TX_D_P3
HSMB_TX_D_N3
HSMA_RX_D_P4
HSMA_RX_D_N4
HSMB_TX_D_P4
HSMB_TX_D_N4
HSMA_RX_D_P5
HSMA_RX_D_N5
HSMB_TX_D_P5
HSMB_TX_D_N5
HSMA_RX_D_P6
HSMA_RX_D_N6
HSMB_TX_D_P6
HSMB_TX_D_N6
HSMA_RX_D_P7
HSMA_RX_D_N7
HSMB_TX_D_P7
HSMB_TX_D_N7
HSMA_CLK_IN_P1
HSMA_CLK_IN_N1
HSMB_CLK_OUT_P1
HSMB_CLK_OUT_N1
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
HSMA_RX_D_P8
HSMA_RX_D_N8
HSMB_TX_D_P8
HSMB_TX_D_N8
HSMA_RX_D_P9
HSMA_RX_D_N9
HSMB_TX_D_P9
HSMB_TX_D_N9
HSMA_RX_D_P10
HSMA_RX_D_N10
HSMB_TX_D_P10
HSMB_TX_D_N10
HSMA_RX_D_P11
HSMA_RX_D_N11
HSMB_TX_D_P11
HSMB_TX_D_N11
HSMA_RX_D_P12
HSMA_RX_D_N12
HSMB_TX_D_P12
HSMB_TX_D_N12
HSMA_RX_D_P13
HSMA_RX_D_N13
HSMB_TX_D_P13
HSMB_TX_D_N13
HSMA_RX_D_P14
HSMA_RX_D_N14
HSMB_TX_D_P14
HSMB_TX_D_N14
HSMA_RX_D_P15
HSMA_RX_D_N15
HSMB_TX_D_P15
HSMB_TX_D_N15
HSMA_RX_D_P16
HSMA_RX_D_N16
HSMB_TX_D_P16
HSMB_TX_D_N16
HSMA_CLK_IN_P2
HSMA_CLK_IN_N2
HSMA_PRSNTn
HSMB_CLK_OUT_P2
HSMB_CLK_OUT_N2
12V
3.3V
2
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
3.3V
47
49
3.3V
53
55
3.3V
59
61
3.3V
65
67
3.3V
71
73
3.3V
77
79
3.3V
83
85
3.3V
89
91
3.3V
95
97
3.3V
101
103
3.3V
107
109
3.3V
113
115
3.3V
119
121
3.3V
125
127
3.3V
131
133
3.3V
137
139
3.3V
143
145
3.3V
149
151
3.3V
155
157
3.3V
ASP-122953-01
2
2 4
4 6
6 8
8 10
8
10 12
8
12 14
8
14 16
8
16 18
8
18 20
8
20 22
8
22 24
8
24 26
8
26 28
8
28 30
8
30 32
8
32 344
34
10,17,19
36
36 38
10
38 40 9
40
BANK 1
42
44
12V
48
50
12V
54
56
12V
60
62
12V
66
68
12V
72
74
12V
78
80
12V
84
86
12V
90
92
12V
96
98
12V
BANK 2
B
102
104
12V
108
110
12V
114
116
12V
120
122
12V
126
128
12V
132
134
12V
138
140
12V
144
146
12V
150
152
12V
156
158
PSNTn
BANK 3
HSMB_RX_P5
HSMB_RX_N5
HSMB_RX_P4
HSMB_RX_N4
HSMB_RX_P3
HSMB_RX_N3
HSMB_RX_P2
HSMB_RX_N2
HSMB_RX_P1
HSMB_RX_N1
HSMB_RX_P0
HSMB_RX_N0
HSMB_SCL
JTAG_TMS
HSMB_JTAG_TDI
HSMB_CLK_IN0
5
4
3
6 HSMA_D[3:0]
6,9 HSMA_TX_D_P[16:0]
6,9 HSMA_TX_D_N[16:0]
6 HSMA_RX_D_P[16:0]
6 HSMA_RX_D_N[16:0]
6 HSMA_CLK_OUT_P[2:1]
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
HSMB_RX_D_P8
HSMB_RX_D_N8
6 HSMA_CLK_OUT_N[2:1]
HSMB_RX_D_P0
HSMB_RX_D_N0
HSMB_RX_D_P1
HSMB_RX_D_N1
HSMB_RX_D_P2
HSMB_RX_D_N2
HSMB_RX_D_P3
HSMB_RX_D_N3
HSMB_RX_D_P4
HSMB_RX_D_N4
HSMB_RX_D_P5
HSMB_RX_D_N5
HSMB_RX_D_P6
HSMB_RX_D_N6
HSMB_RX_D_P7
HSMB_RX_D_N7
HSMB_CLK_IN_P1
HSMB_CLK_IN_N1
9 HSMA_CLK_IN_P[2:1]
D
9 HSMA_CLK_IN_N[2:1]
6,17,18 HSMA_PRSNTn
HSMC PORT B
6 HSMB_D[3:0]
6,9 HSMB_TX_D_P[16:0]
6,9 HSMB_TX_D_N[16:0]
6 HSMB_RX_D_P[16:0]
6 HSMB_RX_D_N[16:0]
C
6 HSMB_CLK_OUT_P[2:1]
6 HSMB_CLK_OUT_N[2:1]
9 HSMB_CLK_IN_P[2:1]
9 HSMB_CLK_IN_N[2:1]
6,17,18 HSMB_PRSNTn
HSMB_RX_D_P9
HSMB_RX_D_N9
HSMB_RX_D_P10
HSMB_RX_D_N10
HSMB_RX_D_P11
HSMB_RX_D_N11
B
HSMB_RX_D_P12
HSMB_RX_D_N12
HSMB_RX_D_P13
HSMB_RX_D_N13
12V
HSMB_RX_D_P14
HSMB_RX_D_N14
HSMB_RX_D_P15
HSMB_RX_D_N15
HSMB_RX_D_P16
HSMB_RX_D_N16
3.3V
C157
C164
10uF
10uF
12V
HSMB_CLK_IN_P2
HSMB_CLK_IN_N2
HSMB_PRSNTn
A
Altera Corporation, 9330 Scranton Rd, San Diego, CA 92121
Title
Copyright (c) 2009 Altera Corporation. All Rights Reserved.
Stratix IV GX FPGA Development Kit Board
B
6
HSMC PORT A
HSMB_D1
HSMB_D3
Date:
7
E
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
Size
8
1
J2
1
3
5
7
0 HSMB_TX_CP5 9
0 HSMB_TX_CN5 11
0 HSMB_TX_CP4 13
0 HSMB_TX_CN4 15
0 HSMB_TX_CP3 17
0 HSMB_TX_CN3 19
0 HSMB_TX_CP2 21
0 HSMB_TX_CN2 23
0 HSMB_TX_CP1 25
0 HSMB_TX_CN1 27
0 HSMB_TX_CP0 29
0 HSMB_TX_CN0 31
HSMB_SDA 4
33
JTAG_TCK 10,17,19 35
HSMB_JTAG_TDO 1037
HSMB_CLK_OUT0 4 39
161
162
163
164
165
166
167
168
169
170
171
172
HSMA_TX_P7
HSMA_TX_N7
HSMA_TX_P6
HSMA_TX_N6
HSMA_TX_P5
HSMA_TX_N5
HSMA_TX_P4
HSMA_TX_N4
HSMA_TX_P3
HSMA_TX_N3
HSMA_TX_P2
HSMA_TX_N2
HSMA_TX_P1
HSMA_TX_N1
HSMA_TX_P0
HSMA_TX_N0
4
GND_1_1
GND_1_2
GND_1_3
GND_1_4
GND_2_1
GND_2_2
GND_2_3
GND_2_4
GND_3_1
GND_3_2
GND_3_3
GND_3_4
7
161
162
163
164
165
166
167
168
169
170
171
172
8
Document Number
Rev
150-0310901-B1 (6XX-41284R )
Friday, February 27, 2009
2
Sheet
12
B
of
1
29
6
5
4
10/100/1000 Ethernet
E
2.5V
ENET_RESETn
4.7K 4
4.7K 4
4.7K 4
4.7K 4
R65
R68
R66
R72
C623
0.01uF
C585
0.01uF
C673
0.01uF
R164
R165
R162
R163
R161
R167
R168
R169
2.5V
J6
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
2.5V
VCC
MDI_P0
MDI_N0
MDI_P1
MDI_N1
MDI_P2
MDI_N2
MDI_P3
MDI_N3
TD0_P
TD0_N
TD1_P
TD1_N
TD2_P
TD2_N
GND_TAB
GND_TAB
D
R190
10.0K
1
3
6
4
5
7
8
10
EN
VCC
GND
OUT
MDI_P0
MDI_N0
MDI_P1
MDI_N1
MDI_P2
MDI_N2
MDI_P3
MDI_N3
29
31
33
34
39
41
42
43
ENET_MDIO
ENET_MDC
ENET_INTn
24
25
23
37
38
HFJ11-1G02E
30
56
ENET_RSET
2.5V
X5
2
GND
1
2
4
3
22
55
54
53
ENET_XTAL_25MHZ
25.00MHz
C836
13
51
B
97
72
66
52
VDDOH
VDDOH
VDDOH
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
VDDO
VDDO
VDDO
VDDO
32
36
35
40
45
78
VDDOX
VDDOX
U21B
5
21
88
96
R73
4.99K
26
48
2.5V
NC1
NC2
R77
4.7K
MDI0_P
MDI0_N
MDI1_P
MDI1_N
MDI2_P
MDI2_N
MDI3_P
MDI3_N
MDIO
MDC
INT_N
HSDAC_P
HSDAC_N
125CLK
XTAL1
XTAL2
VSSC
TRST_N
TCK
TDI
TDO
TMS
E
11
12
14
16
17
18
19
20
TXD0
TXD1
TXD2
TXD3
TXD4
TXD5
TXD6
TXD7
2
94
3
RXCLK
RX_DV
RX_ER
95
92
93
91
90
89
87
86
RXD0
RXD1
RXD2
RXD3
RXD4
RXD5
RXD6
RXD7
D
84
83
CRS
COL
RSET
SEL_FREQ
1
6
10
15
57
62
67
71
85
79
80
82
81
77
75
S_CLK_P
S_CLK_N
S_IN_P
S_IN_N
S_OUT_P
S_OUT_N
68
69
70
73
74
76
LED_TX
LED_RX
LED_DUPLEX
LED_LINK1000
LED_LINK100
LED_LINK10
ENET_LED_TX
SGMII Mode (default)
4
4
4
4
ENET_TX_P
ENET_TX_N
ENET_RX_P
ENET_RX_N
ENET_LED_TX
ENET_LED_RX
C
ENET_LED_LINK1000
ENET_LED_LINK100
ENET_LED_LINK10
R58
R56
ENET_LED_RX
88E1111
ENET_LED_LINK1000 R47
Place near 88E1111 PHY
ENET_LED_LINK100
R51
2.5V
D35
Green_LED
220
D34
Green_LED
220
B
D32
Green_LED
VSS
2.5V
1
88E1111
ENET_DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
CONFIG0
CONFIG1
CONFIG2
CONFIG3
CONFIG4
CONFIG5
CONFIG6
2
8
4
9
7
GTX_CLK
TX_CLK
TX_EN
TX_ER
JTAG
47
49
44
50
46
0.01uF
C
COMA
RESET_N
TEST
12
11
2.5V
TD3_P
TD3_N
ENET_LED_LINK1000
ENET_LED_LINK10
ENET_LED_RX
9
65
64
63
61
60
59
58
U21A
MGMT
0.01uF
ENET_MDIO
ENET_MDC
ENET_INTn
ENET_RESETn
27
28
MDI INTERFACE
C538
3
GMII/MII/TBI INTERFACE
7
SGMII INTERFACE
8
220
D33
Green_LED
220
ENET_DVDD
C878
C879
C837
C757
C758
C795
C834
C793
C835
C792
C794
C931
C833
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
A
A
Altera Corporation, 9330 Scranton Rd, San Diego, CA 92121
Title
Copyright (c) 2009 Altera Corporation. All Rights Reserved.
Stratix IV GX FPGA Development Kit Board
Size
B
Date:
8
7
6
5
4
3
Document Number
Rev
150-0310901-B1 (6XX-41284R )
Friday, May 01, 2009
2
Sheet
13
B
of
1
29
8
7
QDR2TOP0_A[19:0]
7,9
QDR2TOP0_Q[17:0]
7
QDR2TOP0_D[17:0]
7
E
QDR2TOP0_D0
QDR2TOP0_D1
QDR2TOP0_D2
QDR2TOP0_D3
QDR2TOP0_D4
QDR2TOP0_D5
QDR2TOP0_D6
QDR2TOP0_D7
QDR2TOP0_D8
QDR2TOP0_D9
QDR2TOP0_D10
QDR2TOP0_D11
QDR2TOP0_D12
QDR2TOP0_D13
QDR2TOP0_D14
QDR2TOP0_D15
QDR2TOP0_D16
QDR2TOP0_D17
D
P10
N11
M11
K10
J11
G11
E10
D11
C11
B3
C3
D2
F3
G2
J3
L3
M3
N2
N10
M9
L9
J9
G10
F9
D10
C9
B9
C1
D1
E2
G1
J1
K2
M1
N1
P2
U22A
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
QDR2TOP0_BWSn0 7 B7
QDR2TOP0_BWSn1 7 A5
A7
B5
C
QDR2TOP0_WPSn 7
QDR2TOP0_RPSn 7
A4
A8
QDR2TOP0_K_P 7
QDR2TOP0_K_N 7
B6
A6
QDR2TOP0_QVLD 7
QDR2TOP0_ODT 9
P6
R6
QDR2TOP0_DOFFn
1.8V
WPS
RPS
K_P
K_N
QVLD
ODT
9 H1
DOFF
301
TMS
TDI
TDO
TCK
H11
VREF1
VREF2
ZQ
P11
M10
L11
K11
J10
F11
E11
C10
B11
B2
D3
E3
F2
G3
K3
L2
N3
P3
P9
N9
L10
K9
F10
E9
D9
B10
B1
C2
E1
F1
J2
K1
L1
M2
P1
C6
A2
R9
R8
B4
B8
C5
C7
N5
N6
N7
P4
P5
P7
P8
R3
R4
R5
R7
A9
A3
A10
5
F5
F7
G5
G7
H5
H7
J5
J7
K5
K7
1.5V
E4
E8
F4
F8
L8
G4
G8
H3
H4
H8
H9
J4
J8
K4
K8
L4
G9
U22B
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
7,9
QDR2TOP1_Q[17:0]
7
QDR2TOP1_D[17:0]
QDR2TOP1_D0
QDR2TOP1_D1
QDR2TOP1_D2
QDR2TOP1_D3
QDR2TOP1_D4
QDR2TOP1_D5
QDR2TOP1_D6
QDR2TOP1_D7
QDR2TOP1_D8
QDR2TOP1_D9
QDR2TOP1_D10
QDR2TOP1_D11
QDR2TOP1_D12
QDR2TOP1_D13
QDR2TOP1_D14
QDR2TOP1_D15
QDR2TOP1_D16
QDR2TOP1_D17
H2
H10
C729
C764
C766
C883
C730
0.1uF
0.01uF
2.2nF
3.3nF
1.0nF
P10
N11
M11
K10
J11
G11
E10
D11
C11
B3
C3
D2
F3
G2
J3
L3
M3
N2
N10
M9
L9
J9
G10
F9
D10
C9
B9
C1
D1
E2
G1
J1
K2
M1
N1
P2
U7A
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
VREF_B7B8
C336
R130
0.1uF
0.1uF
10K
A4
A8
QDR2TOP1_K_P 7
QDR2TOP1_K_N 7
B6
A6
QDR2TOP1_QVLD 7
QDR2TOP1_ODT 9
P6
R6
QDR2TOP1_DOFFn
1.8V
10K
C486
QDR2TOP1_WPSn 7
QDR2TOP1_RPSn 7
10.0K
R152
301
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
WPS
RPS
K_P
K_N
QVLD
ODT
CQ_P
CQ_N
9 H1
DOFF
R10
R11
R1
R2
R129
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14
Q15
Q16
Q17
NC19
NC20
NC21
NC22
NC23
NC24
NC25
NC26
NC27
NC28
NC29
NC30
NC31
NC32
NC33
NC34
NC35
NC36
NC/144M
BWS0
BWS1
NC/288M
NC
QDR2TOP1_CQ_P 7 A11
QDR2TOP1_CQ_N 7 A1
R196
TMS
TDI
TDO
TCK
H11
VREF1
VREF2
ZQ
QDRII
1.8V
1.8V
C356
C398
C404
C362
C359
C358
C357
C405
C760
0.1uF
0.1uF
0.1uF
0.1uF
0.01uF
0.01uF
0.01uF
0.01uF
1.0uF
C400
C401
C403
C402
C399
C361
C360
C429
2.2nF
3.3nF
4.7nF
4.7nF
4.7nF
22nF
22nF
2.2uF
C844
C850
C808
C814
C852
C809
C810
C811
C1080
0.1uF
0.1uF
0.1uF
0.1uF
0.01uF
0.01uF
0.01uF
0.01uF
1.0uF
C851
C849
C846
C847
C848
C812
C813
C884
2.2nF
3.3nF
4.7nF
4.7nF
4.7nF
22nF
22nF
2.2uF
P11
M10
L11
K11
J10
F11
E11
C10
B11
B2
D3
E3
F2
G3
K3
L2
N3
P3
P9
N9
L10
K9
F10
E9
D9
B10
B1
C2
E1
F1
J2
K1
L1
M2
P1
C6
A2
R9
R8
B4
B8
C5
C7
N5
N6
N7
P4
P5
P7
P8
R3
R4
R5
R7
A9
A3
A10
H2
H10
7
6
5
4
1.8V
QDR2TOP1_Q0
QDR2TOP1_Q1
QDR2TOP1_Q2
QDR2TOP1_Q3
QDR2TOP1_Q4
QDR2TOP1_Q5
QDR2TOP1_Q6
QDR2TOP1_Q7
QDR2TOP1_Q8
QDR2TOP1_Q9
QDR2TOP1_Q10
QDR2TOP1_Q11
QDR2TOP1_Q12
QDR2TOP1_Q13
QDR2TOP1_Q14
QDR2TOP1_Q15
QDR2TOP1_Q16
QDR2TOP1_Q17
F5
F7
G5
G7
H5
H7
J5
J7
K5
K7
1.5V
E4
E8
F4
F8
L8
G4
G8
H3
H4
H8
H9
J4
J8
K4
K8
L4
G9
U7B
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
C4
C8
D4
D5
D6
D7
D8
E5
E6
E7
F6
G6
H6
J6
K6
L5
L6
L7
M4
M5
M6
M7
M8
N4
N8
D
CY7C2563KV18
1.5V
C436
C432
C882
C435
C763
0.1uF
0.01uF
2.2nF
3.3nF
1.0nF
QDR2TOP1_A0
QDR2TOP1_A1
QDR2TOP1_A2
QDR2TOP1_A3
QDR2TOP1_A4
QDR2TOP1_A5
QDR2TOP1_A6
QDR2TOP1_A7
QDR2TOP1_A8
QDR2TOP1_A9
QDR2TOP1_A10
QDR2TOP1_A11
QDR2TOP1_A12
QDR2TOP1_A13
QDR2TOP1_A14
QDR2TOP1_A15
QDR2TOP1_A16
QDR2TOP1_A17
QDR2TOP1_A18
QDR2TOP1_A19
B
C885
C553
0.1uF
0.1uF
A
Altera Corporation, 9330 Scranton Rd, San Diego, CA 92121
Title
Copyright (c) 2009 Altera Corporation. All Rights Reserved.
Stratix IV GX FPGA Development Kit Board
Size
B
3
C
VREF_B7B8
Date:
8
1
E
QDR2TOP1_BWSn0 7 B7
QDR2TOP1_BWSn1 7 A5
A7
B5
S4VCCIO_B7B8
2
7
1.5V
QDRII
A
C4
C8
D4
D5
D6
D7
D8
E5
E6
E7
F6
G6
H6
J6
K6
L5
L6
L7
M4
M5
M6
M7
M8
N4
N8
QDR2TOP1_A[19:0]
CY7C2563KV18
QDR2TOP0_A0
QDR2TOP0_A1
QDR2TOP0_A2
QDR2TOP0_A3
QDR2TOP0_A4
QDR2TOP0_A5
QDR2TOP0_A6
QDR2TOP0_A7
QDR2TOP0_A8
QDR2TOP0_A9
QDR2TOP0_A10
QDR2TOP0_A11
QDR2TOP0_A12
QDR2TOP0_A13
QDR2TOP0_A14
QDR2TOP0_A15
QDR2TOP0_A16
QDR2TOP0_A17
QDR2TOP0_A18
QDR2TOP0_A19
3
Dual 2MB QDRII+ SRAM Ports 0 & 1
1.8V
QDR2TOP0_Q0
QDR2TOP0_Q1
QDR2TOP0_Q2
QDR2TOP0_Q3
QDR2TOP0_Q4
QDR2TOP0_Q5
QDR2TOP0_Q6
QDR2TOP0_Q7
QDR2TOP0_Q8
QDR2TOP0_Q9
QDR2TOP0_Q10
QDR2TOP0_Q11
QDR2TOP0_Q12
QDR2TOP0_Q13
QDR2TOP0_Q14
QDR2TOP0_Q15
QDR2TOP0_Q16
QDR2TOP0_Q17
4
JTAG
R197
CQ_P
CQ_N
R10
R11
R1
R2
R181
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
JTAG
10.0K
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14
Q15
Q16
Q17
NC19
NC20
NC21
NC22
NC23
NC24
NC25
NC26
NC27
NC28
NC29
NC30
NC31
NC32
NC33
NC34
NC35
NC36
NC/144M
BWS0
BWS1
NC/288M
NC
QDR2TOP0_CQ_P 7 A11
QDR2TOP0_CQ_N 7 A1
B
6
Document Number
Rev
150-0310901-B1 (6XX-41284R )
Friday, November 06, 2009
2
Sheet
14
B
of
1
29
8
7
DDR3BOT_CK_P
100, 1%
E
6
5
5
DDR3BOT_DM[7:0]
5
0.75V_VTT
1
2
3
4
DDR3BOT_DQS_P[7:0]
5
DDR3BOT_DQS_N[7:0]
5
DDR3BOT_DQ[63:0]
DDR3BOT_A[14:0]
3
512MB DDR3 Bottom Port
DDR3BOT_CK_N
R202
DDR3BOT_BA[2:0]
4
0.75V_VTT
CN3
8
7
6
5
1
2
3
4
0.75V_VTT
CN2
0.1uF
8
7
6
5
1
2
3
4
0.1uF
CN1
DDR3BOT_A0
DDR3BOT_A1
DDR3BOT_A2
DDR3BOT_A3
DDR3BOT_A4
DDR3BOT_A5
DDR3BOT_A6
DDR3BOT_A7
8
7
6
5
0.1uF
2
0.75V_VTT
7
5
6
6
7
8
5
1
RN4G
RN5E
RN5F
RN4F
RN5G
RN4H
RN3E
RN3A
10 56
12 56
11 56
11 56
10 56
9 56
12 56
16 56
1
0.75V_VTT
DDR3BOT_A8
DDR3BOT_A9
DDR3BOT_RSTn
DDR3BOT_A11
DDR3BOT_A12
DDR3BOT_A13
DDR3BOT_A14
DDR3BOT_CKE
RN3H
RN3B
RN3D
RN3C
RN5C
RN3F
RN3G
RN5A
8
2
4
3
3
6
7
1
9 56
15 56
13 56
14 56
14 56
11 56
10 56
16 56
5
0.75V_VTT
DDR3BOT_CSn
DDR3BOT_WEn
DDR3BOT_RASn
DDR3BOT_BA0
DDR3BOT_BA1
DDR3BOT_BA2
DDR3BOT_CASn
DDR3BOT_ODT
DDR3BOT_A10
RN4B
RN4C
RN5B
RN4D
RN5D
RN4E
RN4A
RN5H
R214
2
3
2
4
4
5
1
8
15 56
14 56
15 56
13 56
13 56
12 56
16 56
9 56
56.2
E
5
Note: ADDR/CMD signals daisy chain
U5-->U12-->U18-->U24
U24
DDR3BOT_A0
DDR3BOT_A1
DDR3BOT_A2
DDR3BOT_A3
DDR3BOT_A4
DDR3BOT_A5
DDR3BOT_A6
DDR3BOT_A7
DDR3BOT_A8
DDR3BOT_A9
DDR3BOT_A10
DDR3BOT_A11
DDR3BOT_A12
D
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
DDR3BOT_CKE K9
9
DDR3BOT_CK_P J7
5
DDR3BOT_CK_N K75
DDR3BOT_DM6 E7
DDR3BOT_DM7 D3
DDR3BOT_CSn 9L2
DDR3BOT_WEn L3
9
DDR3BOT_RASn J3
9
DDR3BOT_CASn K3
9
C
DDR3BOT_BA0 M2
DDR3BOT_BA1 N8
DDR3BOT_BA2 M3
DDR3BOT_RSTn T2
9
DDR3BOT_ODT K1
5
DDR3BOT_ZQ04 L8
VREF_B3B4
H1
M8
R201
B2
D9
G7
K2
K8
N1
N9
R1
R9
240
B
1.5V
A1
A8
C1
C9
D2
E9
F1
H2
H9
U18
DDR3 Device
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BCn
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CKE
CK_P
CK_N
DQS0p
DQS0n
DQS1p
DQS1n
DM0
DM1
CS
WE
RAS
CAS
NC_J1
NC_J9
NC_L1
NC_L9
BA0
BA1
BA2
RESETn
ODT
ZQ
NC/A13
NC/A14
NC/A15
VREFDQ
VREFCA
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
DDR3BOT_DQ48
DDR3BOT_DQ49
DDR3BOT_DQ50
DDR3BOT_DQ51
DDR3BOT_DQ52
DDR3BOT_DQ53
DDR3BOT_DQ54
DDR3BOT_DQ55
DDR3BOT_DQ56
DDR3BOT_DQ57
DDR3BOT_DQ58
DDR3BOT_DQ59
DDR3BOT_DQ60
DDR3BOT_DQ61
DDR3BOT_DQ62
DDR3BOT_DQ63
F3
G3
C7
B7
DDR3BOT_DQS_P6
DDR3BOT_DQS_N6
DDR3BOT_DQS_P7
DDR3BOT_DQS_N7
DDR3BOT_A0
DDR3BOT_A1
DDR3BOT_A2
DDR3BOT_A3
DDR3BOT_A4
DDR3BOT_A5
DDR3BOT_A6
DDR3BOT_A7
DDR3BOT_A8
DDR3BOT_A9
DDR3BOT_A10
DDR3BOT_A11
DDR3BOT_A12
DDR3BOT_CKE K9
9
DDR3BOT_CK_P J7
5
DDR3BOT_CK_N K75
DDR3BOT_DM4 E7
DDR3BOT_DM5 D3
DDR3BOT_CSn 9L2
DDR3BOT_WEn L3
9
DDR3BOT_RASn J3
9
DDR3BOT_CASn K3
9
J1
J9
L1
L9
T3
T7
M7
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
DDR3BOT_BA0 M2
DDR3BOT_BA1 N8
DDR3BOT_BA2 M3
DDR3BOT_RSTn T2
9
DDR3BOT_ODT K1
5
DDR3BOT_ZQ03 L8
VREF_B3B4
H1
M8
R172
DDR3BOT_A13
DDR3BOT_A14
B1
B9
D1
D8
E2
E8
F9
G1
G9
B2
D9
G7
K2
K8
N1
N9
R1
R9
240
J2
J8
A9
M1
M9
B3
P1
P9
E1
T1
T9
G8
1.5V
A1
A8
C1
C9
D2
E9
F1
H2
H9
DDR3 Device
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BCn
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CKE
CK_P
CK_N
DQS0p
DQS0n
DQS1p
DQS1n
DM0
DM1
CS
WE
RAS
CAS
BA0
BA1
BA2
RESETn
ODT
ZQ
NC_J1
NC_J9
NC_L1
NC_L9
NC/A13
NC/A14
NC/A15
VREFDQ
VREFCA
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
U12
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
DDR3BOT_DQ32
DDR3BOT_DQ33
DDR3BOT_DQ34
DDR3BOT_DQ35
DDR3BOT_DQ36
DDR3BOT_DQ37
DDR3BOT_DQ38
DDR3BOT_DQ39
DDR3BOT_DQ40
DDR3BOT_DQ41
DDR3BOT_DQ42
DDR3BOT_DQ43
DDR3BOT_DQ44
DDR3BOT_DQ45
DDR3BOT_DQ46
DDR3BOT_DQ47
F3
G3
C7
B7
DDR3BOT_DQS_P4
DDR3BOT_DQS_N4
DDR3BOT_DQS_P5
DDR3BOT_DQS_N5
DDR3BOT_A0
DDR3BOT_A1
DDR3BOT_A2
DDR3BOT_A3
DDR3BOT_A4
DDR3BOT_A5
DDR3BOT_A6
DDR3BOT_A7
DDR3BOT_A8
DDR3BOT_A9
DDR3BOT_A10
DDR3BOT_A11
DDR3BOT_A12
DDR3BOT_CKE K9
9
DDR3BOT_CK_P J7
5
DDR3BOT_CK_N K75
DDR3BOT_DM2 E7
DDR3BOT_DM3 D3
DDR3BOT_CSn 9L2
DDR3BOT_WEn L3
9
DDR3BOT_RASn J3
9
DDR3BOT_CASn K3
9
J1
J9
L1
L9
T3
T7
M7
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
DDR3BOT_BA0 M2
DDR3BOT_BA1 N8
DDR3BOT_BA2 M3
DDR3BOT_RSTn T2
9
DDR3BOT_ODT K1
5
DDR3BOT_ZQ02 L8
VREF_B3B4
H1
M8
R159
DDR3BOT_A13
DDR3BOT_A14
B1
B9
D1
D8
E2
E8
F9
G1
G9
B2
D9
G7
K2
K8
N1
N9
R1
R9
240
J2
J8
A9
M1
M9
B3
P1
P9
E1
T1
T9
G8
1.5V
A1
A8
C1
C9
D2
E9
F1
H2
H9
DDR3 Device
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BCn
CKE
CK_P
CK_N
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS0p
DQS0n
DQS1p
DQS1n
DM0
DM1
CS
WE
RAS
CAS
BA0
BA1
BA2
RESETn
ODT
ZQ
NC_J1
NC_J9
NC_L1
NC_L9
NC/A13
NC/A14
NC/A15
VREFDQ
VREFCA
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
U5
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
DDR3BOT_DQ16
DDR3BOT_DQ17
DDR3BOT_DQ18
DDR3BOT_DQ19
DDR3BOT_DQ20
DDR3BOT_DQ21
DDR3BOT_DQ22
DDR3BOT_DQ23
DDR3BOT_DQ24
DDR3BOT_DQ25
DDR3BOT_DQ26
DDR3BOT_DQ27
DDR3BOT_DQ28
DDR3BOT_DQ29
DDR3BOT_DQ30
DDR3BOT_DQ31
F3
G3
C7
B7
DDR3BOT_DQS_P2
DDR3BOT_DQS_N2
DDR3BOT_DQS_P3
DDR3BOT_DQS_N3
DDR3BOT_A0
DDR3BOT_A1
DDR3BOT_A2
DDR3BOT_A3
DDR3BOT_A4
DDR3BOT_A5
DDR3BOT_A6
DDR3BOT_A7
DDR3BOT_A8
DDR3BOT_A9
DDR3BOT_A10
DDR3BOT_A11
DDR3BOT_A12
DDR3BOT_CKE K9
9
DDR3BOT_CK_P J7
5
DDR3BOT_CK_N K75
DDR3BOT_DM0 E7
DDR3BOT_DM1 D3
DDR3BOT_CSn 9L2
DDR3BOT_WEn L3
9
DDR3BOT_RASn J3
9
DDR3BOT_CASn K3
9
J1
J9
L1
L9
T3
T7
M7
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
DDR3BOT_BA0 M2
DDR3BOT_BA1 N8
DDR3BOT_BA2 M3
DDR3BOT_RSTn T2
9
DDR3BOT_ODT K1
5
DDR3BOT_ZQ01 L8
VREF_B3B4
H1
M8
R137
DDR3BOT_A13
DDR3BOT_A14
B1
B9
D1
D8
E2
E8
F9
G1
G9
B2
D9
G7
K2
K8
N1
N9
R1
R9
240
J2
J8
A9
M1
M9
B3
P1
P9
E1
T1
T9
G8
1.5V
A1
A8
C1
C9
D2
E9
F1
H2
H9
DDR3 Device
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BCn
CKE
CK_P
CK_N
DM0
DM1
CS
WE
RAS
CAS
BA0
BA1
BA2
RESETn
ODT
ZQ
VREFDQ
VREFCA
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS0p
DQS0n
DQS1p
DQS1n
NC_J1
NC_J9
NC_L1
NC_L9
NC/A13
NC/A14
NC/A15
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
DDR3BOT_DQ0
DDR3BOT_DQ1
DDR3BOT_DQ2
DDR3BOT_DQ3
DDR3BOT_DQ4
DDR3BOT_DQ5
DDR3BOT_DQ6
DDR3BOT_DQ7
DDR3BOT_DQ8
DDR3BOT_DQ9
DDR3BOT_DQ10
DDR3BOT_DQ11
DDR3BOT_DQ12
DDR3BOT_DQ13
DDR3BOT_DQ14
DDR3BOT_DQ15
F3
G3
C7
B7
DDR3BOT_DQS_P0
DDR3BOT_DQS_N0
DDR3BOT_DQS_P1
DDR3BOT_DQS_N1
D
J1
J9
L1
L9
C
T3
T7
M7
DDR3BOT_A13
DDR3BOT_A14
B1
B9
D1
D8
E2
E8
F9
G1
G9
B
J2
J8
A9
M1
M9
B3
P1
P9
E1
T1
T9
G8
1.5V
MT41J64M16LA
A
MT41J64M16LA
MT41J64M16LA
MT41J64M16LA
C715
C790
C789 C788 C827
C753
C713
C345
C344
C350
C468
C420
C464
C389
C349
C466
C716
C465
C903
C584
C829
C346
C537
C501
C469
C923
C925
C926
2.2nF
2.2nF
2.2nF 2.2nF 2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
3.3nF
3.3nF
4.7nF
4.7nF
4.7nF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
Title
C831
C717
C787
C619
C582
C622
C620
C621
C671
C583
C502
C348
C922
C924
C874
C875
C899
C900
C901
C902
0.01uF
0.01uF
0.01uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.47uF
0.47uF
0.47uF
0.47uF
0.47uF
0.47uF
0.47uF
0.47uF
7
6
5
4
Copyright (c) 2009 Altera Corporation. All Rights Reserved.
Stratix IV GX FPGA Development Kit Board
Size
B
Date:
8
A
Altera Corporation, 9330 Scranton Rd, San Diego, CA 92121
1.5V
3
Document Number
Rev
150-0310901-B1 (6XX-41284R )
Friday, November 06, 2009
2
Sheet
15
B
of
1
29
8
7
6
5
SRAM & FLASH
FSM BUS
4
3
2
1
FSM_D[31:0] 4,17
FSM_A[25:0] 4,17
2.5V
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
U30
2.5V
R6
P6
A2
A10
B2
B10
N6
P3
P4
P8
P9
P10
P11
R3
R4
R8
R9
R10
R11
B1
A1
B11
C10
P2
R2
FSM_A2
FSM_A3
FSM_A4
FSM_A5
FSM_A6
FSM_A7
FSM_A8
FSM_A9
FSM_A10
FSM_A11
FSM_A12
FSM_A13
FSM_A14
FSM_A15
FSM_A16
FSM_A17
FSM_A18
FSM_A19
FSM_A20
FSM_A21
FSM_A22
FSM_A23
FSM_A24
FSM_A25
D
C
SRAM_CLK 4
B6
SRAM_OEn 4
SRAM_CEn 4
SRAM_CE2
SRAM_CE3n
SRAM_MODE 17
B8
A3
B3
A6
R1
SRAM_BWn0
SRAM_BWn1
SRAM_BWn2
SRAM_BWn3
SRAM_BWEn 4
B5
A5
A4
B4
A7
SRAM_GWn 4
B7
SRAM_ADSCn 4 A8
SRAM_ADSPn 4 B9
A9
SRAM_ADVn 4
SRAM_ZZ 4,17 H11
B
R7
P5
P7
R5
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
NC_144M
NC_288M
NC_576M
NC_1G
NC_A
NC_B
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
CLK
OE_n
CE1_n
CE2
CE3_n
MODE
BWA_n
BWB_n
BWC_n
BWD_n
BWE_n
DQPA
DQPB
DQPC
DQPD
GW_n
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
ADSC_n
ADSP_n
ADV_n
ZZ
TCK
TDI
TDO
TMS
U32
J10
J11
K10
K11
L10
L11
M10
M11
D10
D11
E10
E11
F10
F11
G10
G11
D1
D2
E1
E2
F1
F2
G1
G2
J1
J2
K1
K2
L1
L2
M1
M2
N11
C11
C1
N1
FSM_D0
FSM_D1
FSM_D2
FSM_D3
FSM_D4
FSM_D5
FSM_D6
FSM_D7
FSM_D8
FSM_D9
FSM_D10
FSM_D11
FSM_D12
FSM_D13
FSM_D14
FSM_D15
FSM_D16
FSM_D17
FSM_D18
FSM_D19
FSM_D20
FSM_D21
FSM_D22
FSM_D23
FSM_D24
FSM_D25
FSM_D26
FSM_D27
FSM_D28
FSM_D29
FSM_D30
FSM_D31
4
4
4
4
FSM_A1
FSM_A2
FSM_A3
FSM_A4
FSM_A5
FSM_A6
FSM_A7
FSM_A8
FSM_A9
FSM_A10
FSM_A11
FSM_A12
FSM_A13
FSM_A14
FSM_A15
FSM_A16
FSM_A17
FSM_A18
FSM_A19
FSM_A20
FSM_A21
FSM_A22
FSM_A23
FSM_A24
FSM_A25
A1
B1
C1
D1
D2
A2
C2
A3
B3
C3
D3
C4
A5
B5
C5
D7
D8
A7
B7
C7
C8
A8
G1
H8
B6
FLASH_CLK 4,17 E6
FLASH_RESETn 4,17
D4
FLASH_CEn 4,17 B4
FLASH_OEn 4,17 F8
FLASH_WEn 4,17 G8
FLASH_ADVn 4,17 F6
C6
FLASH_WPn
SRAM_DQP0
SRAM_DQP1
SRAM_DQP2
SRAM_DQP3
A11
C2
H1
P1
H3
H9
H10
N2
N5
N10
PC28FxxxP30B85
FLASH
1.8V
A4
VPP
A1
A2
VCC
A3
VCC
A4
A5
VCCQ
A6
VCCQ
A7
VCCQ
A8
A9
D0
A10
D1
A11
D2
A12
D3
A13
D4
A14
D5
A15
D6
A16
D7
A17
A18
D8
A19
D9
A20
D10
A21
D11
A22
D12
NC(64M)/A23
D13
NC(64M,128M)/A24 D14
NC/A25(512M)
D15
CLK
A6
H3
D5
D6
G4
F2
E2
G3
E4
E5
G5
G6
H7
FSM_D0
FSM_D1
FSM_D2
FSM_D3
FSM_D4
FSM_D5
FSM_D6
FSM_D7
E1
E3
F3
F4
F5
H5
G7
E7
FSM_D8
FSM_D9
FSM_D10
FSM_D11
FSM_D12
FSM_D13
FSM_D14
FSM_D15
D
F7 4,17 FLASH_RDYBSYn
WAIT
RESET#
CE#
OE#
WE#
ADV#
WP#
2.5V
C
B2
H2
H4
H6
GND
GND
GND
GND
H1
G2
F1
E8
B8
RFU0
RFU1
RFU2
RFU3
RFU4
PC48F4400P0ZBQ0
1.8V
2.5V
R253
R237
R236
R252
10K
10K
10K
10K
FLASH_WPn
FLASH_WEn
FLASH_RDYBSYn
FLASH_RESETn
B
2.5V
C1097
C1067
C1086
C1085
C1098
C1053
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
H2
N7
L5
K7
K6
K5
J7
J6
J5
H7
H6
H5
G7
G6
G5
F7
C8
F6
L6
F5
E7
E6
E5
D7
D6
D5
C7
C6
C5
C4
M5
L7
N8
N4
M7
M6
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
2.5V
FLASH 512Mb (32M X 16)
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
4
J3
J9
K3
K9
L3
L9
M3
M9
N3
N9
C3
C9
D3
D9
E3
E9
F3
F9
G3
G9
E
SRAM_BWn[3:0]
D4
D8
E4
E8
F4
F8
G4
G8
H4
H8
J4
J8
K4
K8
L4
L8
M4
M8
E
IS61VPS51236A
2.5V
2.5V
R241
R250
A
10K
10K
SRAM_CE2
SRAM_CE3n
C1020
C1021
C1051
C1083
C1096
C1065
C1050
C1052
C1066
C1064
0.1uF
0.1uF
0.1uF
0.1uF
4.7nF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
A
Altera Corporation, 9330 Scranton Rd, San Diego, CA 92121
Title
Copyright (c) 2009 Altera Corporation. All Rights Reserved.
Stratix IV GX FPGA Development Kit Board
Size
B
Date:
8
7
6
5
4
3
Document Number
Rev
150-0310901-B1 (6XX-41284R )
Wednesday, February 25, 2009
2
Sheet
16
B
of
1
29
8
7
U31A
E
FPGA_CONFIG_D0
FPGA_CONFIG_D1
FPGA_CONFIG_D2
FPGA_CONFIG_D3
FPGA_CONFIG_D4
FPGA_CONFIG_D5
FPGA_CONFIG_D6
FPGA_CONFIG_D7
D3
C2
E3
C3
E4
D2
E5
D1
MAX2_OEn
MAX2_CSn
MAX2_WEn
MAX2_CLK
MAX2_BEn0
MAX2_BEn1
MAX2_BEn2
MAX2_BEn3
F3
E2
F4
E1
F5
F2
F6
F1
MAX_ERROR
MAX_LOAD
G3
G2
G4
G1
G5
H2
D
H1
OVERTEMP
MAX II
BANK1
IOB1_1
IOB1_2
IOB1_3
IOB1_4
IOB1_5
IOB1_6
IOB1_7
IOB1_8
IOB1_9
IOB1_10
IOB1_11
IOB1_12
IOB1_13
IOB1_14
IOB1_15
IOB1_16
H3
J1
H4
J2
J4
K1
J3
K2
IOB1_25
IOB1_26
IOB1_27
IOB1_28
IOB1_29
IOB1_30
IOB1_31
IOB1_32
L1
K5
L2
K4
M1
K3
M2
L5
M3
L4
N1
L3
N2
M4
N3
IOB1_41
IOB1_42
IOB1_43
IOB1_44
IOB1_45
IOB1_46
IOB1_47
IOB1_48
IOB1_24
CLKIN_50
FPGA_nSTATUS
FPGA_CONF_DONE
FPGA_DCLK
PGM0
PGM1
PGM2
PGM3
RESET_CONFIGn
TSENSE_ALERTn
SENSE_SCK
SENSE_SDI
SENSE_SDO
SENSE_CS0n
SENSE_CS1n
SENSE_ADC_F0
FSM_A0
FSM_A1
FSM_A2
FSM_A3
FSM_A4
FSM_A5
FSM_A6
FSM_A7
C13
B16
C12
A15
D12
B14
C11
B13
FSM_A8
FSM_A9
FSM_A10
FSM_A11
FSM_A12
FSM_A13
FSM_A14
FSM_A15
D11
A13
E11
B12
C10
A12
D10
B11
FSM_A16
FSM_A17
E10
A11
FSM_A18
FSM_A19
FSM_A20
FSM_A21
FSM_A22
B10
C9
A10
D9
B9
C
P14
N13
P15
M14
N14
M13
N15
L14
SRAM_ZZ
N16
L13
M15
L12
M16
L11
L15
K14
L16
K13
K15
K12
K16
B
J15
J14
J12
H12
CLK_CONFIG
IOB3_103
IOB3_104
IOB3_105
IOB3_106
IOB3_107
IOB3_108
IOB3_109
IOB3_110
3
IOB2_82
IOB2_83
IOB2_85
IOB2_86
IOB2_87
IOB2_88
IOB2_89
IOB2_66
IOB2_67
IOB2_90
IOB2_91
IOB2_92
IOB2_93
IOB2_94
IOB2_95
IOB2_96
IOB2_97
IOB2_69
IOB2_70
IOB2_71
IOB2_72
IOB2_73
E9
A9
A8
B8
E8
A7
D8
B7
FSM_D0
FSM_D1
FSM_D2
FSM_D3
FSM_D4
FSM_D5
FSM_D6
FSM_D7
C8
A6
FSM_D8
FSM_D9
B6
E7
A5
D7
B5
FSM_D10
FSM_D11
FSM_D12
FSM_D13
FSM_D14
C7
A4
E6
B4
D6
C4
C6
B3
FSM_D15
FLASH_WEn
FLASH_CEn
FLASH_OEn
FLASH_RDYBSYn
FLASH_RESETn
FLASH_CLK
FLASH_ADVn
C5
A2
D5
B1
D4
CLK100_SDA
FSM_A25
FSM_A24
FSM_A23
U31D
MAX II
BANK3
J16
J13
H16
H13
H15
H14
G16
G12
IOB3_127
IOB3_128
IOB3_129
IOB3_130
IOB3_131
IOB3_132
IOB3_133
IOB3_134
IOB3_111
IOB3_112
IOB3_113
IOB3_114
IOB3_115
IOB3_116
IOB3_117
IOB3_118
IOB3_135
IOB3_119
IOB3_120
IOB3_121
IOB3_122
IOB3_123
IOB3_125
IOB3_126
IOB3_143
IOB3_144
IOB3_145
IOB3_146
IOB3_147
IOB3_148
IOB3_149
IOB3_150
IOB3/GCLK2
IOB3/GCLK3
IOB3_151
IOB3_152
IOB3_153
IOB3_154
IOB3_155
HSMA_PRSNTn
HSMB_PRSNTn
CLK125_EN
CLK148_EN
CLK155_EN
CLK156_EN
CLK100_EN
CLK50_EN
SRAM_MODE
SENSE_SMB_CLK
OVERTEMPn
FPGA_nCONFIG
SENSE_SMB_DATA
G15
F16
G13
F15
G14
E16
F11
IOB3_137
IOB3_138
IOB3_139
IOB3_140
IOB3_141
IOB3_142
SDI_TX_EN
SDI_RX_BYPASS
SDI_RX_EN
LCD_PWRMON
FAN_FORCE_ON
CLK_SEL
CLK_ENABLE
MAX_DIP
USB_DISABLEn
E15
F12
D16
F13
D15
F14
D14
E12
MAX_CONF_DONEn
USB_LED
C15
E13
C14
E14
D13
CLK100_SCL
P4
R1
P5
T2
N5
R3
P6
R4
N6
T4
M6
R5
P7
T5
N7
R6
M7
T6
PHASE_0
R7
P8
T7
N8
R8
PHASE_90
PHASE_135
PHASE_270
CPU_RESETn
M9
M8
IOB4_156
IOB4_157
IOB4_158
IOB4_159
IOB4_160
IOB4_161
IOB4_162
IOB4_163
IOB4_180
IOB4_181
IOB4_182
IOB4_183
IOB4_184
IOB4_185
IOB4_187
IOB4_164
IOB4_165
IOB4_166
IOB4_167
IOB4_168
IOB4_169
IOB4_170
IOB4_171
IOB4_188
IOB4_189
IOB4_190
IOB4_191
IOB4_192
IOB4_193
IOB4_194
IOB4_195
IOB4_172
IOB4_173
IOB4_196
IOB4_197
IOB4_198
IOB4_199
IOB4_200
IOB4_201
IOB4_202
IOB4_203
IOB4_204
IOB4/DEV_CLRn IOB4_205
IOB4/DEV_OE
IOB4_206
N9
T8
T9
R9
P9
T10
SHARED BUS
4,16 FSM_A[25:0]
PHASE_0
PHASE_90
PHASE_135
PHASE_270
4,25
4,25
4,25
4,25
4,25
4,25
SENSE_ADC_F0
SENSE_SDO
SENSE_SDI
SENSE_SCK
SENSE_CS0n
SENSE_CS1n
25
25
25
9,25
4,25
TSENSE_ALERTn
OVERTEMPn
OVERTEMP
SENSE_SMB_CLK
SENSE_SMB_DATA
4,16
4,16
INTERFACE4,16
4,16
4,16
4,16
4,16
H7
H9
J8
J10
G6
F7
K11
L10
M10
T11
N10
R11
P10
T12
M11
R12
FSM_D22
FSM_D23
FSM_D24
FSM_D25
FSM_D26
FSM_D27
FSM_D28
FSM_D29
N11
T13
P11
R13
M12
R14
N12
T15
FSM_D30
FSM_D31
A1
A16
B2
B15
G7
G8
G9
G10
K7
K8
K9
K10
R2
R15
T1
T16
R10
Configuration Clock
1
From EPM2210
Place near MAX II
2
X9
EN
VCC
GND
OUT
125MHz
2.5V
C1042
C1087
C1014
C1093
C1074
C1041
C1076
C1094
C974
C972
C933
C934
C1090
C1075
C1061
C1092
C1040
C1088
C1095
C1079
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
2.5V
GNDINT
GNDINT
GNDINT
GNDINT
GNDINT
GNDINT
GNDINT
GNDINT
FPGA CONFIGURATION
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO4
VCCIO4
VCCIO4
VCCIO4
18 PGM[3:0]
10
10
10
10
6
5
FPGA_nSTATUS
FPGA_CONF_DONE
FPGA_DCLK
FPGA_nCONFIG
MAXII CONTROL INTERFACE
4 MAX2_BEn[3:0]
4
4
4
4
H8
H10
J7
J9
K6
L7
G11
F10
MAX2_OEn
MAX2_CSn
MAX2_WEn
MAX2_CLK
C
PUSH BUTTON INTERFACE
18 RESET_CONFIGn
10,18 CPU_RESETn
9 CLKIN_50
2.5V
LED INTERFACE
C1
H6
J6
P1
19 USB_LED
18 MAX_ERROR
18 MAX_LOAD
A3
A14
F8
F9
18 MAX_CONF_DONEn
6,12,18 HSMA_PRSNTn
6,12,18 HSMB_PRSNTn
B
C16
H11
J11
P16
DIP SWITCH INTERFACE
18
10,18,19
18
18
9,18
18
L8
L9
T3
T14
MAX_DIP
USB_DISABLEn
LCD_PWRMON
FAN_FORCE_ON
CLK_SEL
CLK_ENABLE
EPM2210_F256FBGA
4
3
CLK_CONFIG
C1072
C1073
2.2uF
0.1uF
A
Altera Corporation, 9330 Scranton Rd, San Diego, CA 92121
Title
Copyright (c) 2009 Altera Corporation. All Rights Reserved.
Stratix IV GX FPGA Development Kit Board
Size
B
7
D
10 FPGA_CONFIG_D[7:0]
Date:
8
SRAM INTERFACE
1.8V
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
FLASH_WEn
FLASH_CEn
FLASH_OEn
FLASH_RDYBSYn
FLASH_RESETn
FLASH_CLK
FLASH_ADVn
16 SRAM_MODE
4,16 SRAM_ZZ
SDI INTERFACE
MAX II
Power
E
FLASH INTERFACE
CURRENT & TEMP SENSE INTERFACES
FSM_D16
FSM_D17
FSM_D18
FSM_D19
FSM_D20
FSM_D21
P12
R16
P13
1
4,16 FSM_D[31:0]
REGULATOR PHASE CLOCK
21
23
22
22
U31E
EPM2210_F256FBGA
1.8V
CLK125_EN
CLK148_EN
CLK155_EN
CLK156_EN
CLK100_EN
CLK50_EN
CLK100_SDA
CLK100_SCL
20 SDI_TX_EN
20 SDI_RX_BYPASS
20 SDI_RX_EN
MAX II
BANK4
IOB4_175
IOB4_176
IOB4_177
IOB4_178
IOB4_179
2
CLOCK INTERFACE
9
9
9
9
9
9
9
9
EPM2210_F256FBGA
EPM2210_F256FBGA
A
IOB2_58
IOB2_59
IOB2_60
IOB2_61
IOB2_62
IOB2_63
IOB2_64
IOB2_65
IOB2_74
IOB2_75
IOB2_76
IOB2_77
IOB2_78
IOB2_79
IOB2_80
IOB2_81
IOB2_98
IOB2_99
IOB2_100
IOB2_101
IOB2_102
EPM2210_F256FBGA
U31C
IOB2_50
IOB2_51
IOB2_52
IOB2_53
IOB2_54
IOB2_55
IOB2_56
IOB2_57
MAX II
BANK2
P3
10,12,19
JTAG_TCK
TCK L6 10
JTAG_FPGA_TDO
TDI M510 JTAG_EPM2210_TDO
TDO
10,12,19
JTAG_TMS
N4
TMS
IOB1/GCLK0
IOB1/GCLK1
4
EPM2210 System Controller
P2
IOB1_49
H5
J5
5
U31B
IOB1_34
IOB1_35
IOB1_36
IOB1_37
IOB1_38
IOB1_39
IOB1_40
IOB1_17
IOB1_18
IOB1_19
IOB1_20
IOB1_21
IOB1_22
6
4
3
Document Number
Rev
150-0310901-B1 (6XX-41284R )
Friday, February 27, 2009
2
Sheet
17
B
of
1
29
8
7
6
3.3V
D27
MAX_ERROR
E
D26
MAX_LOAD
Red_LED
RES_MAX_ERROR
R42
D5
Green_LED
D4
HSMA_RX_LED
Green_LED
D3
HSMA_TX_LED
D
Green_LED
D15
HSMB_RX_LED
Green_LED
D14
HSMB_TX_LED
R40
RES_CONF_DONEn
R5
56.2
RESn_HSMA_RX_LED R4
HSMB_PRSNTn
R2
56.2
R1
56.2
USER_LED2
USER_LED3
56.2
USER_LED4
RESn_HSMA_TX_LED R3
56.2
USER_LED5
RESn_HSMB_RX_LED R20
56.2
USER_LED6
RESn_HSMB_TX_LED R14
56.2
USER_LED7
3.3V
D1
D2
USER_LED8
GREEN LED
USER_LED9
GREEN LED
2.5V
PCIE_LED_X1
D37
C
PCIE_LED_X4
D38
PCIE_LED_X8
D39
PCIE_LED_G2
D25
YELLOW LED
R209
56.2
YELLOW LED
R208
56.2
YELLOW LED
R207
56.2
YELLOW LED
R36
56.2
3
D23
2.5V
Green_LED
RESn_LED0
R31
2
B2
56.2
1
B3
2x16 LED DISPLAY INTERFACE
4,10 LCD_DATA[7:0]
56.2
Green_LED
HSMA_PRSNTn
USER_LED0
USER_LED1
Green_LED
RES_MAX_LOAD
4
User IO & Connector
100, 1%
2.5V
MAX_CONF_DONEn
5
USER_LED10
USER_LED11
USER_LED12
USER_LED13
USER_LED14
USER_LED15
D22
D21
D20
Green_LED
Green_LED
Green_LED
D19
Green_LED
D18
Green_LED
D17
Green_LED
D16
Green_LED
D13
Green_LED
D12
Green_LED
D11
Green_LED
D9
Green_LED
D8
Green_LED
D7
Green_LED
D6
Green_LED
D40
Green_LED
R30
56.2
RESn_LED2
R29
56.2
RESn_LED3
RESn_LED4
R28
R27
2x16 LCD
56.2
LCD_WEn
LCD_DATA0
LCD_DATA2
LCD_DATA4
LCD_DATA6
56.2
RESn_LED5
R26
56.2
RESn_LED6
R25
56.2
RESn_LED7
R24
56.2
RESn_LED8
R12
56.2
RESn_LED9
R11
56.2
RESn_LED10
R10
56.2
RESn_LED11
R9
56.2
RESn_LED13
R7
56.2
RESn_LED14 R6
56.2
J16
1
3
5
7
9
11
13
2
4
6
8
10
12
14
2
4
6
8
10
12
14
PUSH BUTTON INTERFACE
LCD_D_Cn
LCD_CSn
LCD_DATA1
LCD_DATA3
LCD_DATA5
LCD_DATA7
4,9 USER_PB[2:0]
LED INTERFACE
4,9,10 USER_LED[15:0]
6
6
6
4
1
1
1
S1
S2
S5
S4
S3
E
17 RESET_CONFIGn
10,17 CPU_RESETn
17
17
17
17
1
R8
1
3
5
7
9
11
13
HDR2X7
56.2
RESn_LED12
4 LCD_CSn
4 LCD_D_Cn
4 LCD_WEn
2x7 HDR
2 x 16 Display Connector
5.0V
1
Green_LED
D10
RESn_LED1
OVERTEMPn
MAX_ERROR
MAX_LOAD
MAX_CONF_DONEn
D
HSMA_RX_LED
HSMA_TX_LED
HSMB_RX_LED
HSMB_TX_LED
6,12,17 HSMA_PRSNTn
2.5V
6,12,17 HSMB_PRSNTn
2
RESET_CONFIGn
R23
10.0K
2
CPU_RESETn
R15
10.0K
2
USER_PB0
R18
10.0K
2
USER_PB1
R13
10.0K
2
USER_PB2
R17
10.0K
4
4
4
4
PCIE_LED_X1
PCIE_LED_X4
PCIE_LED_X8
PCIE_LED_G2
DIP SWITCH INTERFACE
4,9 USER_DIPSW[7:0]
17
10,17,19
17
17
9,17
17
24
24
C
MAX_DIP
USB_DISABLEn
LCD_PWRMON
FAN_FORCE_ON
CLK_SEL
CLK_ENABLE
S4VCCH_SEL
S4VCCA_SEL
ROTARY SWITCH
RESn_LED15
R16
17 PGM[3:0]
56.2
B
B
OVERTEMPn
16
15
14
13
12
11
10
9
SW3
2.5V
1
2
3
4
5
6
7
8
USER_DIPSW0
USER_DIPSW1
USER_DIPSW2
USER_DIPSW3
USER_DIPSW4
USER_DIPSW5
USER_DIPSW6
USER_DIPSW7
RN1A
RN1B
RN1C
RN1D
RN1E
RN1F
RN1G
RN1H
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
10K
10K
10K
10K
10K
10K
10K
10K
R118
R117
56.2
2.5V
1
2
3
4
5
6
7
8
MAX_DIP
USB_DISABLEn
LCD_PWRMON
FAN_FORCE_ON
CLK_SEL
CLK_ENABLE
S4VCCH_SEL
S4VCCA_SEL
RN2A
RN2B
RN2C
RN2D
RN2E
RN2F
RN2G
RN2H
1
2
3
4
5
6
7
8
R34
10.0K PGM1
R43
10.0K PGM3
2
C2
8
16 10K
15 10K
14 10K
13 10K
12 10K
11 10K
10 10K
9 10K
P2
C2
P8
P4
C1
P1
4
C1
1
PGM2
R35
10.0K
PGM0
R44
10.0K
947705-012
Rotary Switch Cap
A
Altera Corporation, 9330 Scranton Rd, San Diego, CA 92121
Title
ON = 0
OFF = 1
Copyright (c) 2009 Altera Corporation. All Rights Reserved.
Stratix IV GX FPGA Development Kit Board
Size
B
Date:
8
SW2
B4
BOARD SETTINGS DIPSWITCH
USER DIPSWITCH
2.5V
94HCB16WT
TDA08H0SB1
TDA08H0SB1
A
16
15
14
13
12
11
2.37M 10
9
32.4K
SW4
RESn_LED_FANR86
2.5V
7
6
5
4
3
Document Number
Rev
150-0310901-B1 (6XX-41284R )
Friday, November 06, 2009
2
Sheet
18
B
of
1
29
8
7
6
5
4
3
Embedded USB Blaster
2
1
MAXII USB INTERFACE
5V_USB
USB
L4
J7
USB CON
BLM21PG331SN1
C87
10uF
1
2
3
4
6
5V_USB
5V_USB
R127
27
28
USB_XTAL1
USB_XTAL2
R115
18pF
5
1.5K
10.0K
4
USB_RESETn
USB_EECS
USB_EESK
EEDATA
2
USB_XTAL1
31
XTIN
XTOUT
EECS
EESK
EEDATA
USB_XTAL2
13
D0
D1
D2
D3
D4
D5
D6
D7
RD#
WR
RESET#
TEST
VCC-IO
3
26
VCC1
VCC2
30
RSTOUT#
TXE#
RXF#
9
17
1
Y1
6.000MHz
18pF
32
1
2
USBDM
USBDP
SI/WU
PWREN#
AGND
8
7
27
27
25
24
23
22
21
20
19
18
USB_D0
USB_D1
USB_D2
USB_D3
USB_D4
USB_D5
USB_D6
USB_D7
16
15
USB_RDn
USB_WR
14
12
USB_TXEn
USB_RXFn
11
10
USB_SI_WU
USB_PWR_ENn
2.5V_USB
1
2
3
4
DECOUPLING CAPS
C313
0.1uF
10uF
C289
0.1uF
CS
SK
DIN
DOUT
VCC
NC1
NC2
GND
K8
L8
R133
1.00k
USB_EEDATA
R138
IOB1_9
IOB1_10
IOB1_11
IOB1_12
IOB1_13
IOB1_14
IOB1_15
IOB1_16
IOB1_17
IOB1_18
IOB1_19
IOB1_20
IOB1_21
IOB1_22
IOB1_23
IOB1_24
IOB1_25
IOB1_26
IOB1_27
IOB1_28
IOB1_29
IOB1_30
IOB1_31
IOB1_32
IOB1/CLK0
IOB1/CLK1
IOB1/DEV_CLRn
IOB1/DEV_OE
U3B
8
7
6
5
TCK
TDI
TDO
TMS
J7
K10
K3
K4
K5
K6
K7
K9
L1
L10
L11
L2
L3
L4
L5
L6
JTAG_TCK
JTAG_TMS
JTAG_BLASTER_TDI
JTAG_BLASTER_TDO
E
3 MAX_EN
10,17,18 USB_DISABLEn
17 USB_LED
USB_LED
JTAG_BLASTER_TDO
5V_USB
C312
L7
L9
JTAG_TCK
K1
J2
K2
J1
USB_MAX_TCK
USB_MAX_TDI
USB_MAX_TDO
USB_MAX_TMS
1uF
8
7
6
5
2.5V_USB
U39
IN
OUT
NC7 SENSE
NC6
NC3
SHDNn GND
EPAD
1
2
3
4
9
C311
R114
19.1K
LT3010
C323
0.01uF
D
1uF
R123
20.0K
EPM240M100
USB_TXEn
USB_D1
USB_D0
USB_WR
USB_RDn
USB_D7
USB_D6
USB_D5
A1
A10
A11
A2
A3
A4
A5
A6
USB_D4
USB_D3
USB_D2
A7
A8
A9
B10
B11
B2
B3
B4
AT93C46DN-SH-B
R145
2.2K
B
U42
F2
E1
USB_RESETn
5V_USB
C273
F3
G1
G2
H1
H2
H3
J5
J6
CLKIN_24MHZ
C
5V_USB
USB_EECS
USB_EESK
EEDATA
USB_SI_WU
USB_DISABLEn
USB_PWR_ENn
IOB1_1
IOB1_2
IOB1_3
IOB1_4
IOB1_5
IOB1_6
IOB1_7
IOB1_8
MAX II
BANK1
IOB1_33
IOB1_34
FT245BL
29
R75
R71
3V3OUT
AVCC
6
4
5
NC1
A
NC2
B
GNDGND
5V_USB
C22
U40
6
SN65220DBV
C13
C290
0.1uF
GND1
GND2
1
3
2
D
B1
C1
C2
D1
D2
D3
E2
F1
C390
0.1uF
C325
33nF
U23
2.5V_USB
USB_RXFn
MAX_EN
R109
470
5
E
U3A
10,12,17
10,12,17
10
10
IOB2_35
IOB2_36
IOB2_37
IOB2_38
IOB2_39
IOB2_40
IOB2_41
IOB2_42
MAX II
BANK2
IOB2_43
IOB2_44
IOB2_45
IOB2_46
IOB2_47
IOB2_48
IOB2_49
IOB2_50
IOB2_59
IOB2_60
IOB2_61
IOB2_62
IOB2_63
IOB2_64
IOB2_65
IOB2_66
IOB2/CLK2
IOB2/CLK3
IOB2_67
IOB2_68
IOB2_69
IOB2_70
IOB2_71
IOB2_72
IOB2_73
IOB2_74
10.0K
F10
G11
IOB2_51
IOB2_52
IOB2_53
IOB2_54
IOB2_55
IOB2_56
IOB2_57
IOB2_58
B5
B6
B7
B8
B9
C10
C11
C5
C
C6
C7
D10
D11
D9
E10
E11
F11
F9
G10
H10
H11
H9
J10
J11
K11
U3C
D5
D7
E4
E8
G4
G8
H5
H7
JTAG_TMS
JTAG_BLASTER_TDI
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
MAX II
Power
2.5V_USB
VCCINT
VCCINT
VCCIO1
VCCIO1
VCCIO1
VCCIO2
VCCIO2
VCCIO2
E9
G3
E3
J4
J8
C4
C8
G9
B
EPM240M100
EPM240M100
2.5V_USB
2.5V_USB
2.5V_USB
1
2
C324
0.01uF
X4
EN
VCC
GND
OUT
24MHz
2.5V_USB
R148
4
3
2.5V_USB
CLKIN_24MHZ
C329
0.01uF
R160
C347
4.7uF
1.00K USB_MAX_TCK
USB_MAX_TDO
1.00K USB_MAX_TMS
USB_MAX_TDI
1
3
5
7
9
J18
1
3
5
7
9
2
4
6
8
10
2
4
6
8
10
0
R156
0
R173
PLACE NEAR MAX II
C53
C35
C52
C30
C31
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
DNI
A
A
Altera Corporation, 9330 Scranton Rd, San Diego, CA 92121
Title
Copyright (c) 2009 Altera Corporation. All Rights Reserved.
Stratix IV GX FPGA Development Kit Board
Size
B
Date:
8
7
6
5
4
3
Document Number
Rev
150-0310901-B1 (6XX-41284R )
Friday, May 01, 2009
2
Sheet
19
B
of
1
29
8
7
6
5
4
3
SDI Cable Driver, Equalizer, and SMB
2
1
75 Ohm Impedance
E
3.3V_SDI
L7
1
750
R46
1.00K
3.3V_SDI
SDI_TX_P 8
SDI_TX_N 8
C391
C351
4.7uF
U4
4.7uF
SDI_TX_SD_HDn 10
From EPM2210
1
2
SDI_TXCAP_P
SDI_TXCAP_N
SDI_TX_EN 17
R139
R140
49.9
49.9
3.3V
0.01uF
NC0
DISABLE
MUTE
NC3
NC4
NC5
NC6
VEE
NC7
CENTERPAD
L3
120 Ohm FB
22uF
75 Ohm Impedance
12
11
C393
4.7uF
SDI_TXBNC_P
1
J5
SMB
75
SDI_TXDRV_P
SDI_TXDRV_N
R134
75
D
3
17
R141
L6
1
75
5.6nH
C352
4.7uF
SDI_TXBNC_N
2
R128
75
C51
C34
C33
C56
0.1uF
0.1uF
220nF
220nF
C
L5
1
1
R146
75
3.3V_SDI
C36
J3
SMB
SDO
SDO
9
LMH0302SQ
C392
C
VCC
SD/HD
RSET
5
6
7
8
13
14
15
16
SDI_TX_MUTEn
D
SDI
SDI
10
4
SDI_TX_RSET
Cable
Driver
R147
3.3V_SDI
E
2
2
3
4
5
R149
5.6nH
3.9nH
2
C315
SDI_IN_P1
75
R110
75
5
4
3
2
R111
3.3V_SDI
R126
B
37.4
From EPM2210
SDI_RX_BYPASS
1uF
C326
2
3
SDI_EQIN_P1
SDI_EQIN_N1
1uF
7
3.3V_SDI
R125
10K
17
SDI
SDI
VCC1
VCC2
BYPASS
C42
SDO
SDO
CD
5
6
1uF
R39
14
8
R124
0
0
SDI_RX_EN 17
Read-Only (Auto-Mute)
U2
AEC+
AECMUTE
MUTEref
VEE1
VEE2
VEE3
VEE4
DAP
13
16
11
10
15
SDO_P
SDO_N
C29
SDI_RX_CDn
1
4
9
12
17
C28
1uF
1uF 8
SDI_RX_P
8
SDI_RX_N
D30
3.3V_SDI
R45
B
75
Green_LED
LMH0344
A
A
Altera Corporation, 9330 Scranton Rd, San Diego, CA 92121
Title
Copyright (c) 2009 Altera Corporation. All Rights Reserved.
Stratix IV GX FPGA Development Kit Board
Size
B
Date:
8
7
6
5
4
3
Document Number
Rev
150-0310901-B1 (6XX-41284R )
Friday, November 06, 2009
2
Sheet
20
B
of
1
29
8
CPO
VIN
3
4
C
9
13
7
C319
47uf
10uF
10uF
10uF
10uF
0.1uF
0.1uF
0.1uF
0.1uF
3.3V_TGATE
U34
IRF7455PbF
C39
R116
27
C293
0.1uF
R113
0
R19
C275
0.001uF
0.007
R98
3.3V_SWOUT
26
24
3.3V_BOOST
25
3.3V_SW
22
3.3V_BGATE
3.3V_SENSE_P 30
3.3V_SENSE_N 31
3.3V_VOSENSE 1
5
3.3V_ITH
28
3.3V_SHDNn
4
27
R103
0
C161 C159 C254
C12
C253
C163
C160
C162
C252
10uF
10uF
22uF
22uF
100uf
100uf
100uf
61.9K
C261
1.0nF
R94
20K
R93
30.0K
C260
100pF
C276
B
D29
CMDSH2_3
INTVCC
L1
1
U33
IRF7455PbF
10uF
C292
0.1uF
TG1
BOOST1
SW1
BG1
SENSE1_P
SENSE1_N
Vosense1
Ith1
RUN_SS1
FCB
PGOOD
2
OUT
VDD
GND
EP_GND
5 6 7 8
8
7
6
5
8
9
2
3
10
4
11
12
5
6
NC
D
3
2
5
U20
FDMC8878
1
2
3
D41
MBRS130L
R112
0
14
17
15
18
12
11
9
8
13
7
2
12V_BOOST
12V_SW
12V_BGATE
12V_SENSE_P
12V_SENSE_N
12V_VOSENSE
12V_ITH
12V_SHDNn
C291
0.1uF
C274
0.001uF
U19
1
6
4
7
R21
+12V @ 6A
OUT
VDD
GND
EP_GND
GATE
IN
NC
3
2
C
5
LTC4357
0.007
12V_SWOUT
R102 280K
C259
C258
100pF
3.3nF
+ C675 + C626 + C539 + C353 + C472 + C394 + C158
22uF
R92
15.0K
C38
0.01uF
PHASE_0 17
1
GATE
IN
4
C37
1000pF
7
12V_PCIE
LTC4357
3 2 1
10.0K R41
0.1uF
3.3V_SHDNn
5.6uH
LTC3727
TG2
BOOST2
SW2
BG2
SENSE2_P
SENSE2_N
Vosense2
Ith2
RUN_SS2
3.3Vout
PLLFLTR
1
2
3
U15
1
6
4
7
4
C314
0.1uF
U16
FDMC8878
4
3 2 1
D28
CMDSH2_3
U35
C331
0.1uF
5 6 7 8
12V
0.003
4
12V_TGATE
2
VCC
U37
IRF7455PbF
DC_INPUT_FET
1 2 3
D42
MBRS130L
3.3V_MUXVCC
10uF
C320
4
+3.3V @ 5A
10uF
C317
2
STATUS
FAULT
5
6
1
1
R142
DNI
UV
OV
10
C316
12V_SW
LTC4352CDD
GND
EP
REV
C327
3.3V_SW
8 7 6 5
OUT
GATE
SOURCE
C318
8
7
6
5
2
2
FDMC8878
U43
1 2 3
C334
21
1
C328
1 2 3
8 7 6 5
D44
U38
IRF7455PbF
C32
EXTVcc
8 7 6 5
8
11
12
DC_INPUT_FET
4
3.3uH
R64
A1
12CWQ03FN
8 7 6 5
L2
4
12V_OUT
0.1uF
U47
FDMC8878
D
4
5
6
4
STATUS
FAULT
SOURCE
GATE
OUT
7
13
9
REV
EP
GND
BaseCC
1
E
A2
20
CPO
12
11
8
C759
14V - 20V
DC Input
D43
INTVcc
3
4
LTC4352CDD
2
VCC
3
23
10
1 2 3
UV
OV
VIN
1
1
J4
CONN JACK PWR
2
1
3
3.3V_PCIE
1
2
DC_INPUT
3.3V_MUXVCCP
D45
3
Power 1 - DC Input & 12V, 3.3V Output
3.3V
E
R180
DNI
4
Vin
R70
5
SGND
PGND
EGND
PLLIN
NC1
NC2
NC3
NC4
0.003
6
6
19
33
3
10
16
29
32
3.3V_OUT
7
22uF
22uF
22uF
22uF
22uF
C250 C251 C5
22uF
10uF
10uF
10uF
R97
20.0K
B
12V
12V_SHDNn
R22
1K
SW1
SW SLIDE-4P2T
POWER LED
D24
BLUE LED
A
A
Altera Corporation, 9330 Scranton Rd, San Diego, CA 92121
Title
Copyright (c) 2009 Altera Corporation. All Rights Reserved.
Stratix IV GX FPGA Development Kit Board
Size
B
Date:
8
7
6
5
4
3
Document Number
Rev
150-0310901-B1 (6XX-41284R )
Thursday, February 26, 2009
2
Sheet
21
B
of
1
29
5
4
3
Power 2 - 0.9V & 5V
0.9V_OUT
C81
10uF
C91
10uF
C86
0.1uF
D36
20V Zener
LTM4601
D
12V
+ C129
2
2
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
C89
0.1uF
C80
100uF
1
C1038
+
330uF
4V
Tantalum
C908
100uF
C85
100uF
12V
C805
330uF
4V
Tantalum
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
C932
100uF
C90
0.1uF
LTM4601
DNI
0.9V_RUN
C1035
0.047uF
INT_VCC_C
C1037
1.0nF
C1034
DNI
PHASE_135
TRACK_C
COMP_C
A10
A7
E12
A8
A9
A11
A12
C12
D12
U26D
RUN
INTVCC
DRVCC
PLLIN
TRACK/SS
COMP
MPGM
MARG0
MARG1
PGOOD
VFB
DIFFVOUT
VOUT_LCL
VOSNS+
FSET
VOSNS-
B
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
C1036
0.1uF
C1013
10uF
G12
F12
K12
L12
0.9V_FB
VOUT_LCL
J12
B12
M12
60.4K
R84
C880
100pF
S4VCC
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
SGND
C135
+ 100uF
16V
Tantalum
D46
20V Zener
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
A1
A2
A3
A4
A5
A6
B1
B2
B3
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
LTM4601
D
12V
C973 +
DNI
0.9V_FB
G12
F12
VOUT_LCL
K12
L12
INT_VCC_D
C101
F8
F9
G1
G2
G3
G4
G5
G6
G7
G8
G9
H1
H2
H3
H4
H5
H6
H7
H8
H9
H12
C1012
10uF
U51C
B4
B5
B6
C1
C2
C3
C4
C5
C6
C95
+ 100uF
16V
Tantalum
Slave
C100
220PF
12V
1000pF
U26B
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
LTM4601
LTM4601
D1
D2
D3
D4
D5
D6
E1
E2
E3
E4
E5
E6
E7
F1
F2
F3
F4
F5
F6
F7
U51A
S4VCC
Master
C
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
C804
+
330uF
4V
Tantalum
E
Bottom-Side Module
1
C136
C907
+ 100uF
+ 100uF
16V
16V
Tantalum Tantalum
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
+
2
1
1
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
2
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
1
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
B4
B5
B6
C1
C2
C3
C4
C5
C6
2
A1
A2
A3
A4
A5
A6
B1
B2
B3
U26C
1
Top-Side Module (default)
U26A
17 PHASE_135
17 PHASE_270
0.003
TP1
TP2
12V
1
S4VCC
R220
E
2
2
6
1
7
2
8
A4
A5
B4
B5
A1
C72
C70
0.1uf
DNI
U11A
VIN
VIN
VIN
VIN
RUNN/SS
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
BIAS
ADJ
F3
F4
F5
G3
G4
G5
H4
H5
LTM8201EV
B1
B2
C1
C2
D1
D2
D3
D4
D5
E1
LTM4601
A
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DIFFVOUT
VOUT_LCL
VOSNS+
FSET
VOSNS-
A10
A7
E12
RUN
INTVCC
DRVCC
A12
C12
D12
MPGM
MARG0
MARG1
10K
C840
A8
PHASE_270
A9
TRACK_C
A11
COMP_C
PLLIN
TRACK/SS
COMP
R191
0.9V_RUN
INT_VCC_D
C
1000pF
C802
DNI
LTM4601
R57
19.1K
U11B
PGOOD
VFB
5.0V
D1
D2
D3
D4
D5
D6
E1
E2
E3
E4
E5
E6
E7
F1
F2
F3
F4
F5
F6
F7
H3
A2
J12
B12
M12
3.3V
U51D
C64
C63
2.2uF
0.1uf
H2
H1
G2
G1
F2
F1
E5
E4
E3
E2
U51B
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
SGND
F8
F9
G1
G2
G3
G4
G5
G6
G7
G8
G9
H1
H2
H3
H4
H5
H6
H7
H8
H9
H12
B
LTM4601
A
Altera Corporation, 9330 Scranton Rd, San Diego, CA 92121
LTM8201EV
Title
Copyright (c) 2009 Altera Corporation. All Rights Reserved.
Stratix IV GX FPGA Development Kit Board
Size
B
Date:
8
7
6
5
4
3
Document Number
Rev
150-0310901-B1 (6XX-41284R )
Friday, November 06, 2009
2
Sheet
22
B
of
1
29
7
6
U17A
J1
J2
J3
J4
J5
J6
K1
K2
K3
K4
K5
K6
E
C67
C627 C586
0.1uF
10uF
10uF
L2
L5
1.8V_RUNSS
C71
0.01uF
1.8V_SW
D
H2
H3
H4
H5
H6
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
H1
H7
H8
H9
H10
C
VIN1_0
VIN1_1
VIN1_2
VIN1_3
VIN1_4
VIN1_5
VIN1_6
VIN1_7
VIN1_8
VIN1_9
VIN1_10
VIN1_11
PGOOD1
RUN/SS1
COMP1
SW1_0
SW1_1
SW1_2
SW1_3
SW1_4
VOUT1_0
VOUT1_1
VOUT1_2
VOUT1_3
VOUT1_4
VOUT1_5
VOUT1_6
VOUT1_7
VOUT1_8
VOUT1_9
VOUT1_10
VOUT1_11
VOUT1_12
VOUT1_13
VOUT1_14
VOUT1_15
TRACK1
FB1
GND1_0
GND1_1
GND1_2
GND1_3
GND1_4
GND1_5
GND1_6
GND1_7
GND1_8
GND1_9
GND1_10
GND1_11
GND1_12
GND1_13
GND1_14
GND1_15
GND1_16
GND1_17
GND1_18
GND1_19
GND1_20
GND1_21
GND1_22
GND1_23
GND1_24
GND1_25
GND1_26
GND1_27
GND1_28
GND1_29
GND1_30
GND1_31
GND1_32
GND1_33
L4
J9
J10
J11
J12
K9
K10
K11
K12
L9
L10
L11
L12
M9
M10
M11
M12
L3
L6
1.8V @ 4A
10uF
S4VCCIO_B3A
R200
C1
C2
C3
C4
C5
C6
D1
D2
D3
D4
D5
D6
10uF
0.003
B
2.5V
1.5V_SW
1.8V_FB
R62
4.02K
B2
B3
B4
B5
B6
SW2_0
SW2_1
SW2_2
SW2_3
SW2_4
TRACK2
FB2
GND2_0
GND2_1
GND2_2
GND2_3
GND2_4
GND2_5
GND2_6
GND2_7
GND2_8
GND2_9
GND2_10
GND2_11
GND2_12
GND2_13
GND2_14
GND2_15
GND2_16
GND2_17
GND2_18
GND2_19
GND2_20
GND2_21
GND2_22
GND2_23
GND2_24
GND2_25
GND2_26
GND2_27
GND2_28
GND2_29
GND2_30
GND2_31
GND2_32
GND2_33
C426
0.1uF
10uF
C506
+ C23
10uF
DNI
C906
+ 100uF
16V
Tantalum
1
C41
B4
B5
B6
C1
C2
C3
C4
C5
C6
C96
+ 100uF
16V
Tantalum
D31
20V Zener
2.5V
3.3V
LTM4601
PHASE_90 17
C425 0.01uF
R157
A
A10
A7
E12
A8
A9
A11
A12
C12
D12
U8C
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
A1
A2
A3
A4
A5
A6
B1
B2
B3
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
C9
C10
C11
C12
D9
D10
D11
D12
E9
E10
E11
E12
F9
F10
F11
F12
E3
E6
1.5V @ 4A
C726
100uF
1.5V
S4VCCIO_B3B4
R171
C725
100uF
E
0.003
S4VCCIO_B7B8
R174
0.003
1.8V
R67
4.99K
1.5V_TRACK
1.5V_FB
D
R59
5.76K
B11
B12
C7
C8
D7
D8
E1
E7
E8
F1
F2
F3
F4
F5
F6
F7
F8
R63
5.76K
C
LTM4601
R151
10.0K
U8D
RUN
INTVCC
DRVCC
PLLIN
TRACK/SS
COMP
MPGM
MARG0
MARG1
PGOOD
VFB
DIFFVOUT
VOUT_LCL
VOSNS+
FSET
VOSNS-
G12 24 PG_2.5V
F12
2.5V_FB
K12
L12
100pF
R150
C477
2.5V
2.5V
J12
B12
M12
19.1K
2.5V @ 12A
U8A
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
C478
100pF
C40
0.1uF
C395
100uF
C330
100uF
+
C69
470uF
10V
Tantalum
S4VCCIO_B1B2
R223
0.003
S4VCCIO_B5
R105
0.003
B
S4VCCIO_B6
R104
0.003
S4VCCIO_INT
R158
0.003
LTM4601
LTM4601
A
Altera Corporation, 9330 Scranton Rd, San Diego, CA 92121
Title
Copyright (c) 2009 Altera Corporation. All Rights Reserved.
Stratix IV GX FPGA Development Kit Board
Size
B
Date:
7
2.5V
2.5V_FB
392K
8
1.8V
12V
F8
F9
G1
G2
G3
G4
G5
G6
G7
G8
G9
H1
H2
H3
H4
H5
H6
H7
H8
H9
H12
2
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
SGND
VOUT2_0
VOUT2_1
VOUT2_2
VOUT2_3
VOUT2_4
VOUT2_5
VOUT2_6
VOUT2_7
VOUT2_8
VOUT2_9
VOUT2_10
VOUT2_11
VOUT2_12
VOUT2_13
VOUT2_14
VOUT2_15
E4
PG_1.5V
LTM4614
1
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGOOD2
RUN/SS2
COMP2
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
B1
B7
B8
B9
B10
2
U8B
VIN2_0
VIN2_1
VIN2_2
VIN2_3
VIN2_4
VIN2_5
VIN2_6
VIN2_7
VIN2_8
VIN2_9
VIN2_10
VIN2_11
E2
E5
C780
0.1uF
LTM4614
D1
D2
D3
D4
D5
D6
E1
E2
E3
E4
E5
E6
E7
F1
F2
F3
F4
F5
F6
F7
R61
10.0K
LTM4614 - CHANNEL 2
C628 C587
1
24
U17B
1.8V
C723
100uF
2
1.8V tracks 1.5V output during ramp-up
2.5V
C724
100uF
H11
H12
J7
J8
K7
K8
L1
L7
L8
M1
M2
M3
M4
M5
M6
M7
M8
3
Power 3 - 2.5V, 1.8V, 1.5V
R60
10.0K
LTM4614 - CHANNEL 1
4
1
2.5V
5
2
8
6
5
4
3
Document Number
Rev
150-0310901-B1 (6XX-41284R )
Wednesday, February 25, 2009
2
Sheet
23
B
of
1
29
6
Power 4 - Linear Regulators
5.0V
S4VCCPT = 1.5V/0.286A
C853
0.1uf
2.5V
1
E
U48
3
6
C887
10uF
BIAS
OUT
IN
ADJ
SHDN
5
R186
2
7
1.8V
S4VCCPT
C462
27.4K
R185
LTC3025-1
PG_2.5V 23
R187
0.003
S4VCCPT_OUT
4
GND
EP_GND
5
C680
C768
22uF
2.2uF
10uF
3.3V
5
10.0K
1.8V
S4VCCD_PLL = 0.9V/0.100A
0.1uf
1
U45
3
D
6
C549
10uF
BIAS
OUT
IN
ADJ
SHDN
4
S4VCCD_PLL_OUT
5
R154
2
7
GND
EP_GND
R155
0.003
10uF
S4VCCD_PLL
VCONT
S4VCC_GXB = 1.1V/1.428A
OUT
OUT
OUT
EP
SET
12.7K
1
2
3
9
4
R144
0.003
S4VCC_GXB_OUT
1.1V_SET
C535
C534
22uF
2.2uF
3.3V
C437
C438
7
8
6
5
22uF
2.2uF
2.2uF
IN
IN
NC
VCONT
OUT
OUT
OUT
EP
SET
LT3080-1/1.1A LDO
10
1
2
3
9
4
1.1V_SET
VREF_B3B4
R136
1
C
3
6
C68
10uF
5.0V
7
8
6
OUT
IN
ADJ
SHDN
GND
EP_GND
4
3.3V
5
R55
2
7
S4VCCA_GXB
12.4K
C54
C65
22uF
2.2uF
S4VCCA_SEL
S4VCCA_PLL = 2.5V/0.051A
0.1uf
1
B
U6
3
6
C58
10uF
BIAS
OUT
IN
ADJ
SHDN
GND
EP_GND
4
5
R48
2
7
52.3K
C748
C781
22uF
2.2uF
10.0K
5.0V
OUT
OUT
OUT
EP
SET
2.5V
0.1uf
HDMI = 1.8V/0.280A
1
3
A
C929
0.1uf
6
U49
BIAS
OUT
IN
SHDN
ADJ
GND
EP_GND
LTC3025-1
HDMI_PVDD
4
5
2
7
L10
R210
52.3K
L11
R211
15.0K
1
3
6
10uF
4
18
C898
C870
22uF
2.2uF
U50
BIAS
OUT
IN
ADJ
SHDN
GND
EP_GND
S4VCCH_GXB
Bias up? (15mV drop)
S4VCCH_SEL
Voltage
1.4V
1.5V
C
DIP Setting
CLOSED (Default)
Do not use
ENET_DVDD
4
5
R204
2
7
15.0K
R203
LTC3025-1
10.0K
C1054
C930
22uF
2.2uF
B
S4VCCA_PLL
C613
C490
22uF
2.2uF
12V
8
7
6
5
C1068
DNI
5.0V_MONITOR
U57
1
2
3
4
9
IN
OUT
NC7 SENSE
NC6
NC3
SHDNn GND
EPAD
R240
180K
C1055
C1027
0.01uF
1uF
R239
60.4K
HDMI_DVDD
120 Ohm FB
HDMI_AVDD
A
Altera Corporation, 9330 Scranton Rd, San Diego, CA 92121
120 Ohm FB
Title
Copyright (c) 2009 Altera Corporation. All Rights Reserved.
Stratix IV GX FPGA Development Kit Board
C928
6
R69
0.003
L9
BLM21PG331SN1
1uF
7
10uF
D
ENET_DVDD = 1.0V/0.253A
Size
B
Date:
8
1
2
3
9
150.0K
LT3010
C905
10uF
S4VCCH_GXB_OUT
LT3080-1/1.1A LDO
0.1uf
1.5V
S4VCCAUX
R49
LTC3025-1
VTTREF
C986 C987
S4VCCH_GXB = 1.5V/0.514A
VCONT
C969
18
R53
0.003
C927
10uF
3
5
VTT
VTTSNS
S3
S5
3.3V
DIP Setting
CLOSED (Default)
OPEN
2
1
0.75V VTT (3A Sink/Src)
IN
IN
NC
C993 PG_1.5V
S4VCCAUX_OUT
VLDOIN
VDDQSNS
R189
2.2uF
64.9K
Voltage
3.0V
2.5V
VIN
C824
R54
LTC3025-1
5
S4VCCAUX = 2.5V/0.250A
C59
3.3V
BIAS
R52
0.003
7
9
10K
10K
6
U46
10uF
S4VCCA_GXB_OUT
TPS51100DGQ
1uF
C782
U10
U52
C999
5.0V
5.0V
R232
R233
10.0K
S4VCCA_GXB = 3.0V/0.347A
E
0.75V_VTT
2.5V
0.1uf
S4VCC_GXB
5.0V
54.9K
PG_1.5V 23
C66
1
L8
S4VCCL_GXB
BLM21PG331SN1
LT3080-1/1.1A LDO
U41
C386
R153
LTC3025-1
IN
IN
NC
2
S4VCCIO_B3B4
2.2uF
3.3V
C514
7
8
6
3
C499
C341
1.5V
U44
4
PGND
GND
GND
7
4
8
11
8
5
4
3
Document Number
Rev
150-0310901-B1 (6XX-41284R )
Friday, November 06, 2009
2
Sheet
24
B
of
1
29
8
7
6
5
4
3
Power & Temp Monitor
5.0V_MONITOR
5.0V
A/D #0
S4VCCIO_B7B8
1.5V
S4VCC
0.9V_OUT
23
24
3.3V
3.3V_OUT
S4VCCIO_INT
2.5V
S4VCCH_GXB_OUT
S4VCCAUX_OUT
D
S4VCCH_GXB
S4VCCAUX
S4VCCD_PLL
S4VCCD_PLL_OUT
25
26
27
28
1
2
3
4
S4VCCPT
S4VCCPT_OUT
21
22
5
6
7
8
10
REF-
CH4
CH5
F0
CH6
CH7
SDO
SDI
SCK
CSn
CH8
CH9
CH10
CH11
11
REF=5.0V
12
19
17
20
18
16
R121
DNI
SENSE5_ADC_F0
CH14
CH15
NC1
NC2
COM
GND
Q1
10K
10K
10K
10K
Temperature Sense
3.3V
6
10
TEMPDIODE_P 10
TEMPDIODE_N 10
3
4
15
1
200
C997
0.1uF
5
13
16
U27
ADD1
ADD0
DXP
DXN
OVERTn
ALERTn
SMBCLK
SMBDATA
STBYn
VCC
GND1
GND2
GND3
REFF0
SDO
SDI
SCK
CSn
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
CH12
CH13
13
14
10.0K
15
2.5V
U28
VCC
IO VCC1
IO VCC2
IO VCC3
IO VCC4
NC2
/TS
VL
IO VL1
IO VL2
IO VL3
IO VL4
NC1
GND
1
2
3
4
5
6
7
4,17
4,17
4,17
4,17
NC1
NC2
CH14
CH15
GND
COM
21
22
23
24
25
26
27
28
1
2
3
4
5
6
7
8
S4VCCA_GXB
S4VCCA_GXB_OUT
S4VCCIO_B5
2.5V
S4VCCIO_B6
2.5V
S4VCCIO_B1B2
2.5V
S4VCCIO_B3A
1.8V
S4VCCIO_B3B4
S4VCC_GXB
1.5V
D
S4VCC_GXB_OUT
2.5V_DIV
3.3V_DIV
10.0K
10.0K
R32
R37
2.5V
3.3V
10
R33
10.0K
LTC2418
SENSE_ADC_F0
SENSE_SDO
SENSE_SDI
SENSE_SCK
R38
10.0K
C
R83
3.3V
R225
R224
R222
R226
FAN
17
20
18
SENSE5_CS1n 16
REF+
CH0
CH1
DNI
14
13
12
11
10
9
8
High Side
MAX3378
17 OVERTEMP
FDV305N
SENSE5_ADC_F0 19
VCC
R96
SENSE5_ADC_F0
SENSE5_SDO
SENSE5_SDI
SENSE5_SCK
R81
9
U1
CH10
CH11
5.0V
2.5V
Low Side
E
C267
0.1uF
12
R106
0
13
14
15
C268
10uF
R107
DNI
R120
0
SENSE5_SDO
SENSE5_SDI
SENSE5_SCK
SENSE5_CS0n
5.0V
A/D #1
R108
0
11
CH12
CH13
TSENSE_FAN_CNTL
B1
R221
REF+
9
5.0V
SENSE5_CS1n
SENSE5_CS0n
10K
1
2
C
3.3V
CH2
CH3
VCC
R119
0
12V
22_23_2021
B
CH0
CH1
C298
10uF
LTC2418
Fan Power Header
J10
U36
C322
0.1uF
R101
R99
R100
R95
Low Side
E
1
5.0V_MONITOR
10K
10K
10K
10K
High Side
2
2.5V
R82
10.0K
14
13
12
11
10
9
8
2.5V
U29
VCC
IO VCC1
IO VCC2
IO VCC3
IO VCC4
NC2
/TS
VL
IO VL1
IO VL2
IO VL3
IO VL4
NC1
GND
1
2
3
4
5
6
7
4,17 SENSE_CS1n
4,17 SENSE_CS0n
MAX3378
9 17 OVERTEMPn
11 17 TSENSE_ALERTn
149,17 SENSE_SMB_CLK
124,17 SENSE_SMB_DATA
B
2
7
8
ADDR = 01
NC1
NC2
NC3
MAX1619
12V_OUT
12V_OUT
R50
1
2
0
C61
0.1uF
A
8
4
3
5
12V
U9
SENSE+
VIN
SHDN
ADR0
ADR1
ADIN
SENSESCL
SDA
GND
EP_GND
10
ADDR = 10
6
7
9
11
Title
LTC4151
B
Date:
7
Copyright (c) 2009 Altera Corporation. All Rights Reserved.
Stratix IV GX FPGA Development Kit Board
Size
8
A
Altera Corporation, 9330 Scranton Rd, San Diego, CA 92121
6
5
4
3
Document Number
Rev
150-0310901-B1 (6XX-41284R )
Wednesday, February 25, 2009
2
Sheet
25
B
of
1
29
8
7
U13K
S4VCCAUX
E
S4VCCIO_INT
(2.5V)
D
AL12
AL28
G11
H29
U27
W27
AB26
Y26
AD24
AD22
AD20
AD14
AD16
AD18
AC13
AA13
U13
W13
R15
R17
R19
R25
R23
R21
S4VCCD_PLL
S4VCCA_PLL
C
AK20
AK19
Y28
AA28
Y11
AA11
K20
K19
AL20
AL19
Y29
AA29
Y10
AA10
J20
J19
S4VCCPT
S4VCCIO_INT
B
(2.5V)
Y13
H20
AM20
AA27
AA26
AA12
AK12
AK28
K11
6
Stratix IV GX
Power
Auxiliary Power
VCCAUX
VCCAUX
VCCAUX
VCCAUX
Core and Periphery
2.5V
IO Pre-Driver Power
VCCPD1A
VCCPD1C
VCCPD2A
VCCPD2C
VCCPD3A
VCCPD3B
VCCPD3C
VCCPD4A
VCCPD4B
VCCPD4C
VCCPD5A
VCCPD5C
VCCPD6A
VCCPD6C
VCCPD7A
VCCPD7B
VCCPD7C
VCCPD8A
VCCPD8B
VCCPD8C
2.5V
OR
3.0V
0.9V
PLL Digital Power
VCCD_PLL_B1
VCCD_PLL_B2
VCCD_PLL_L2
VCCD_PLL_L3
VCCD_PLL_R2
VCCD_PLL_R3
VCCD_PLL_T1
VCCD_PLL_T2
0.9V
PLL Analog Power
VCCA_PLL_B1
VCCA_PLL_B2
VCCA_PLL_L2
VCCA_PLL_L3
VCCA_PLL_R2
VCCA_PLL_R3
VCCA_PLL_T1
VCCA_PLL_T2
2.5V
Programmable Power
VCCPT
VCCPT
VCCPT
VCCPT
VCCPT
VCCPT
1.5V
Configuration Power
VCCPGM
VCCPGM
Battery Back-up Power
VCCBAT
2.5V
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Diff. CLK Input Power
2.5V
VCC_CLKIN3C
VCC_CLKIN4C
VCC_CLKIN7C
VCC_CLKIN8C
5
U13L
S4VCCIO_B1B2
(2.5V)
D32
E35
G32
G34
J31
P28
AA30
K33
N32
T29
U29
AG26
AJ28
AM32
AP31
AT35
AF28
S4VCCIO_B3A
VREF_B3B4
S4VCCIO_B3B4
AF31
AG33
AH31
AL33
AB29
AH25
AL26
AR29
AU30
AN28
AG23
AR26
AL24
AH21
AK22
AW24
AP22
AH15
AK15
AP12
AU13
AN12
AJ17
AW15
AM16
S4VCCIO_INT
AK21
AK18
K18
K21
3
Power 6 - Stratix IV GX Power
S4VCC
AA15
AA17
AA19
AA21
AA23
AA25
AA32
AA8
AB14
AB16
AB18
AB20
AB22
AB24
AB32
AB8
AC15
AC17
AC19
AC21
AC23
AC25
AE32
AE8
AF32
AF8
T14
T16
T18
T20
T22
T24
T26
U15
U17
U19
U21
U23
U25
U32
U8
V14
V16
V18
V20
V22
V24
V26
V32
V8
W15
W17
W19
W21
W23
W25
Y14
Y16
Y18
Y20
Y22
Y24
4
(2.5V)
AJ19
AU21
AW17
AL18
2
U13M
Stratix IV GX
I/O Power
VCCIO1A
VCCIO1A
VCCIO1A
VCCIO1A
VCCIO1A
VREF1A
VCCIO5A
VCCIO5A
VCCIO5A
VCCIO5A
VCCIO5A
VREF5A
VCCIO1C
VCCIO1C
VCCIO1C
VCCIO1C
VREF1C
VCCIO5C
VCCIO5C
VCCIO5C
VCCIO5C
VREF5C
VCCIO2A
VCCIO2A
VCCIO2A
VCCIO2A
VCCIO2A
VREF2A
VCCIO6A
VCCIO6A
VCCIO6A
VCCIO6A
VCCIO6A
VREF6A
VCCIO2C
VCCIO2C
VCCIO2C
VCCIO2C
VREF2C
VCCIO6C
VCCIO6C
VCCIO6C
VCCIO6C
VREF6C
VCCIO3A
VCCIO3A
VCCIO3A
VCCIO3A
VREF3A
VCCIO7A
VCCIO7A
VCCIO7A
VCCIO7A
VREF7A
VCCIO3B
VCCIO3B
VREF3B
VCCIO7B
VCCIO7B
VREF7B
VCCIO3C
VCCIO3C
VCCIO3C
VREF3C
VCCIO7C
VCCIO7C
VCCIO7C
VREF7C
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VREF4A
VCCIO8A
VCCIO8A
VCCIO8A
VCCIO8A
VREF8A
VCCIO4B
VCCIO4B
VREF4B
VCCIO8B
VCCIO8B
VREF8B
VCCIO4C
VCCIO4C
VCCIO4C
VREF4C
VCCIO8C
VCCIO8C
VCCIO8C
VREF8C
S4VCCIO_B5
AW9
AR7
AR10
AN8
AK10
AG11
AL7
AJ8
AH7
AE9
AD11
S4VCCIO_B6
B8
E5
E8
H8
M9
P11
H5
P10
T11
V13
U11
A12
D12
J14
M15
G12
S4VCCIO_B7B8
VREF_B7B8
A15
L17
H16
C21
E19
M18
E20
A30
D30
J28
M26
F29
E26
K25
H25
C23
F22
L22
J21
A2
A3
A33
A35
A36
A37
A38
A4
A5
A7
AA14
AA16
AA18
AA22
AA24
AA3
AA36
AA37
AA4
AB1
AB15
AB17
AB19
AB2
AB21
AB23
AB25
AB33
AB38
AB39
AB7
AC12
AC14
AC16
AC18
AC20
AC22
AC24
AC27
AC3
AC30
AC33
AC36
AC37
AC4
AC7
AC9
AD1
AD2
AD23
AD32
AD34
AD38
AD39
AD6
AD8
AE3
AE36
AE37
AE4
AF1
AF12
AF15
AF18
Stratix IV GX
Power
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
EP4SGX230KF40_F1517
Version = 0.4 Preliminary
1
U13O
U13N
AF2
AF21
AF24
AF27
AF30
AF33
AF38
AF39
AF7
AF9
AG3
AG36
AG37
AG4
AH1
AH2
AH38
AH39
AJ12
AJ15
AJ18
AJ21
AJ24
AJ27
AJ3
AJ30
AJ33
AJ36
AJ37
AJ4
AJ7
AJ9
AK1
AK2
AK38
AK39
AL11
AL3
AL36
AL37
AL4
AM1
AM12
AM15
AM18
AM2
AM21
AM24
AM27
AM30
AM33
AM38
AM39
AM7
AM9
AN3
AN36
AN37
AN4
AP1
AP2
AP38
AP39
AR12
AR15
AR18
AR21
AR24
AR27
AR3
AR30
AR33
AR36
AR37
AR4
AR6
AR9
AT1
AT2
AT38
AT39
AU3
AU36
AU37
AU4
AV1
AV12
AV15
AV18
AV2
AV21
AV24
AV27
AV3
AV30
AV33
AV37
AV38
AV39
AV6
AV9
AW3
AW37
B1
B12
B15
B18
B2
B21
B24
B27
B30
B33
B34
B35
B38
B39
B5
B6
B7
B9
C3
C36
C37
C4
D1
D2
D38
Stratix IV GX
Power
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
D39
E12
E15
E18
E21
E24
E27
E3
E30
E33
E36
E37
E4
E6
E9
F1
F2
F38
F39
G3
G36
G37
G4
H1
H12
H15
H18
H2
H21
H24
H27
H30
H33
H38
H39
H6
H9
J3
J36
J37
J4
K1
K2
K38
K39
L12
L15
L18
L21
L24
L27
L3
L30
L33
L36
L37
L4
L6
L9
M1
M2
M38
M39
N18
N24
N3
N36
N37
N4
P1
P12
P15
P2
P21
P27
P30
P33
P38
P39
P7
P9
R3
R36
R37
R4
T1
T15
T17
T19
T2
T21
T23
T25
T32
T34
T38
T39
T6
T8
U12
U14
U16
U18
U20
U22
U24
U26
U28
U3
AK11
L28
AU35
AV36
AU5
AV4
Stratix IV GX
Power
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
NC_7
NC_8
NC_9
NC_10
NC_11
E
U30
U36
U37
U4
U9
V1
V15
V17
V19
V2
V21
V23
V25
V33
V38
V39
V7
W10
W14
W16
W18
W20
W22
W24
W3
W36
W37
W4
Y1
Y12
Y15
Y17
Y19
Y2
Y21
Y23
Y25
Y27
Y30
Y32
Y34
Y38
Y39
Y6
Y8
D
C
AD17
R16
R26
AM28
F11
EP4SGX230KF40_F1517
Version = 0.4 Preliminary
B
EP4SGX230KF40_F1517
Version = 0.4 Preliminary
EP4SGX230KF40_F1517
Version = 0.4 Preliminary
EP4SGX230KF40_F1517
Version = 0.4 Preliminary
A
A
Altera Corporation, 9330 Scranton Rd, San Diego, CA 92121
Title
Copyright (c) 2009 Altera Corporation. All Rights Reserved.
Stratix IV GX FPGA Development Kit Board
Size
B
Date:
8
7
6
5
4
3
Document Number
Rev
150-0310901-B1 (6XX-41284R )
Wednesday, February 25, 2009
2
Sheet
26
B
of
1
29
8
7
6
5
D
3
2
1
Stratix IV GX VCC
S4VCC
E
4
C102
C655
C608
C523
C521
C518
C529
C646
C526
C644
C605
C691
C693
C696
C698
C604
C652
C650
C602
C607
C657
C694
C697
C653
C603
C645
C562
C649
C564
C656
330uF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
3.3nF
3.3nF
3.3nF
3.3nF
3.3nF
3.3nF
3.3nF
3.3nF
3.3nF
C695
C658
C647
C559
C560
C692
C294
C297
C308
C207
C946
C950
C952
C942
C838
C796
C964
C1000
C240
C843
C507
C479
C594
C310
C229
C307
C270
C249
C786
C397
3.3nF
3.3nF
3.3nF
3.3nF
3.3nF
3.3nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
C540
C589
C550
C482
C872
C871
C669
C832
C1026
C944
C948
C940
C208
C954
C996
C941
C938
C945
C947
C951
C953
C981
C1016
C1017
C728
C542
C508
C541
C762
C770
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
C683
C685
C321
C409
C825
C668
C750
C784
C920
C963
C1001
C877
C755
C388
C235
C236
C237
C248
C306
C239
C241
C296
C305
C295
C785
C876
C921
C670
C309
C269
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
C271
C272
C596
C355
C396
C480
C957
C959
C956
C958
C820
C821
C452
C822
C816
C739
C455
C451
C448
C601
C525
C528
C558
C561
C453
C606
C648
C446
C818
C737
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
C563
C565
C520
C450
C817
C651
C654
C819
C449
C447
C955
C939
C949
C943
C749
C280
C783
C904
C712
C754
C282
C303
C285
C301
C354
C806
C333
C407
C1044
C978
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
0.047uF 0.047uF 0.047uF 0.047uF 0.047uF 0.047uF 0.047uF 0.047uF 0.047uF 0.047uF 0.047uF 0.047uF 0.047uF 0.047uF 0.047uF 0.047uF 0.047uF 0.047uF 0.1uF
0.1uF
C590
C304
C302
C798
C839
C74
C99
C98
C93
C92
C26
C797
C799
C791
C718
C300
C284
C281
C230
C994
C983
C982
C985
C588
C97
C94
C1019
C1045
C984
C980
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.47uF
0.47uF
0.47uF
0.47uF
0.47uF
0.47uF
0.47uF
C826
C711
C247
C283
C299
C332
C277
C633
C419
C264
C752
C828
C731
C287
C513
C751
C998
C727
C27
C679
C278
C279
C286
C1063
C1049
C672
C873
C581
C500
0.47uF
0.47uF
0.47uF
0.47uF
0.47uF
10uF
10uF
10uF
10uF
10uF
10uF
100uF
100uF
100uF
100uF
100uF
100uF
1.0uF
1.0uF
1.0uF
1.0uF
1.0uF
1.0uF
1.0uF
1.0uF
1.0uF
1.0uF
1.0uF
1.0uF
E
D
C
C
Stratix IV GX VCC_GXB
S4VCC_GXB
VCCA_GXB
S4VCCA_GXB
C57
C364
C916
C366
C371
C918
C855
C379
C893
C919
C374
C862
C917
C859
C863
C894
C372
C376
C378
C856
C370
C377
C380
C373
C864
C857
C895
C381
C369
C867
C892
C891
C382
330uF
1.0nF
1.0nF
1.0nF
1.0nF
1.0nF
1.0nF
1.0nF
1.0nF
1.0nF
1.0nF
1.0nF
1.0nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
1.0nF
1.0nF
1.0nF
1.0nF
4.7nF
4.7nF
C365
C684
C734
C772
C815
C481
C484
C666
C615
C385
C497
C747
C771
C515
C636
C571
C408
C439
C498
C551
C595
C614
C384
C703
C343
C342
C536
C896
C889
C367
C383
C868
C375
3.3nF
3.3nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
22nF
22nF
22nF
22nF
0.047uF 0.047uF 0.1uF
0.47uF
0.47uF
0.47uF
1.0uF
1.0uF
100uF
2.2nF
2.2nF
2.2nF
2.2nF
0.01uF
0.01uF
Stratix IV GX VCCH_GXB
S4VCCH_GXB
Stratix IV GX S4VCCPT
S4VCCPT
S4VCCAUX
Stratix IV GX VCCAUX
C62
C84
C83
1.0uF
100uF
100uF
B
B
C78
C860
C861
C866
C413
C704
C414
C416
C578
C705
C708
C667
330uF
1.0nF
1.0nF
1.0nF
1.0nF
1.0nF
1.0nF
1.0nF
2.2nF
2.2nF
2.2nF
2.2nF
C572
C709
C577
C706
C574
C575
C710
C576
C617
C707
C616
2.2nF
4.7nF
4.7nF
0.01uF
0.01uF
0.01uF
22nF
22nF
0.1uF
0.47uF
0.47uF
Stratix IV GX VCCD_PLL
Stratix IV GX VCCA_PLL
S4VCCA_PLL
A
C573
C79
C492
C639
C742
C663
C682
C524
C743
C485
C746
C775
C496
C441
C443
C897
C368
2.2nF
330uF
1.0nF
1.0nF
1.0nF
1.0nF
2.2nF
2.2nF
2.2nF
1.0nF
1.0nF
1.0nF
2.2nF
2.2nF
4.7nF
0.1uF
22nF
C73
C618
C733
C635
C681
C732
C769
C634
C77
C76
C458
C778
C493
C890
C869
C533
100uF
1.0uF
4.7nF
4.7nF
0.01uF
0.01uF
22nF
0.1uF
1.0uF
100uF
0.01uF
0.01uF
22nF
0.1uF
100uF
1.0uF
Stratix IV GX VCCL_GXB
S4VCCD_PLL
S4VCCL_GXB
Stratix IV GX VREF_B3B4
VREF_B3B4
C640
C662
C776
C597
C641
C661
C777
C491
C406
C363
C858
C865
C412
C415
C487
C568
C467
C714
C664
C700
3.3nF
0.01uF
0.1uF
100uF
2.2nF
4.7nF
0.01uF
0.1uF
1.0uF
100uF
0.1uF
0.1uF
0.01uF
0.01uF
100uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
A
Altera Corporation, 9330 Scranton Rd, San Diego, CA 92121
Title
Copyright (c) 2009 Altera Corporation. All Rights Reserved.
Stratix IV GX FPGA Development Kit Board
Size
B
Date:
8
7
6
5
4
3
Document Number
Rev
150-0310901-B1 (6XX-41284R )
Wednesday, February 25, 2009
2
Sheet
27
B
of
1
29
8
7
6
5
1.5V
1.5V
E
C431
C434
C433
C430
C841
C845
C767
C881
C765
C337
C335
C592
C75
1.0nF
1.0nF
1.0nF
1.0nF
1.0nF
1.0nF
1.0nF
1.0nF
1.0nF
2.2nF
2.2uF
2.2uF
22uF
Decoupling 2
4
3
2
1
E
S4VCCIO_B7B8
C512
C637
C510
C511
C554
C555
C517
C552
C516
C774
C736
C642
C773
C483
C735
C638
C686
1.0nF
1.0nF
1.0nF
1.0nF
2.2nF
2.2nF
2.2nF
2.2nF
4.7nF
4.7nF
4.7nF
4.7nF
22nF
22nF
0.01uF
0.01uF
0.047uF 0.1uF
C688
C599
C593
C591
0.47uF
1.0uF
100uF
S4VCCIO_B3B4
D
C665
C570
C702
C532 C701
C569
C611
C660
1.0nF
1.0nF
2.2nF
2.2nF 4.7nF
0.01uF
22nF
0.047uF 0.47uF
C567
C756
C830
1.0uF
100uF
D
1.8V
1.8V
C
C911
C842
C803
C719
C579
C470
C991
C1100
C387
C1018
C971
C1091
C807
1.0nF
1.0nF
1.0nF
1.0nF
1.0nF
1.0nF
1.0nF
1.0nF
1.0nF
1.0nF
1.0nF
1.0nF
1.0nF
C910
C1099
C427
C761
C720
C580
C471
C1025
C1101
C463
C913
C970
C1089
C428
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
C
2.5V
2.5V
B
S4VCCIO_INT
C961
C288
C421
C960
C977
C779
C55
C530
C531
C519
C612
C598
C689
C643
C699
C600
C557
C556
C738
C494
1.0nF
1.0nF
1.0nF
1.0nF
1.0nF
2.2nF
22uF
1.0nF
1.0nF
1.0nF
1.0nF
1.0nF
1.0nF
1.0nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
C745
C609
C659
C527
C690
C610
C522
C566
C740
C741
C543
C509
4.7nF
4.7nF
4.7nF
0.01uF
0.01uF
0.01uF
22nF
0.047uF 0.1uF
0.47uF
1.0uF
100uF
S4VCCIO_B1B2
A
S4VCCIO_B5
C823
C854
C888
2.2nF
4.7nF
0.01uF
C744
C962
0.1uF
100uF
B
S4VCCIO_B6
C456
C460
C495
C459
C418
C488
C489
C445
C411
C442
1.0nF
1.0nF
2.2nF
3.3nF
4.7nF
1.0nF
1.0nF
2.2nF
3.3nF
4.7nF
C457
C454
C417
C461
C444
C440
C410
C338
0.01uF
22nF
0.1uF
100uF
0.01uF
22nF
0.1uF
100uF
A
Altera Corporation, 9330 Scranton Rd, San Diego, CA 92121
Title
Copyright (c) 2009 Altera Corporation. All Rights Reserved.
Stratix IV GX FPGA Development Kit Board
Size
B
Date:
8
7
6
5
4
3
Document Number
Rev
150-0310901-B1 (6XX-41284R )
Wednesday, February 25, 2009
2
Sheet
28
B
of
1
29
8
7
6
5
Decoupling 3
3
2
1
12V
12V
E
D
4
E
C123
C117
C119
C120
C121
C122
C124
C125
C1056
C1069
C126
C139
C140
C141
C142
C143
C144
C1005
C1007
C1003
C1071
C1070
C1057
C674
C1002
C1010
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.1uF
0.1uF
0.1uF
C1011
C1032
C1033
C476
C505
C222
C224
C226
C228
C209
C155
C156
C210
C801
C800
C1059
C1004
C1006
C152
C151
C203
C138
C204
C137
C205
C206
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
2.2nF
2.2nF
2.2nF
2.2nF
C625
C1058
C424
C423
C504
C503
C474
C473
C422
C110
C107
C108
C109
C221
C223
C225
C227
C146
C147
C145
C148
C149
C150
C624
C721
C722
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
3.3nF
3.3nF
3.3nF
C1009
C1029
C1028
C1008
C1031
C1030
C475
0.47uF
0.47uF
0.47uF
0.47uF
0.47uF
0.047uF 0.047uF
D
3.3V
3.3V
C115
C214
C182
C165
C166
C167
C168
C170
C202
C201
C199
C195
C197
C193
C194
C200
C196
C198
C134
C133
C116
C218
C219
C220
C217
C215
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
C
C
C233
C172
C176
C190
C131
C111
C212
C112
C113
C114
C213
C234
C188
C232
C189
C153
C154
C216
C175
C173
C169
C171
C174
C211
C177
C178
0.1uF
0.1uF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
C183
C180
C127
C179
C191
C185
C187
C181
C231
C128
C184
C186
C192
C118
C130
C132
C82
C60
4.7nF
4.7nF
3.3nF
3.3nF
3.3nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2uF
0.047uF 0.047uF 0.047uF 0.47uF
0.47uF
0.47uF
330uF
100uf
B
B
SCREW1
SCREW3
STANDOFF1
SPACER1
SCREW2
SCREW4
STANDOFF2
SPACER2
SCREW5
STANDOFF3
PCB1
STANDOFF4
A
A
Altera Corporation, 9330 Scranton Rd, San Diego, CA 92121
Title
Copyright (c) 2009 Altera Corporation. All Rights Reserved.
Stratix IV GX FPGA Development Kit Board
Size
B
Date:
8
7
6
5
4
3
Document Number
Rev
150-0310901-B1 (6XX-41284R )
Wednesday, February 25, 2009
2
Sheet
29
B
of
1
29
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