INTEGRATED CIRCUITS SSTV16857 14-bit SSTL_2 registered driver with differential clock inputs Product data Supersedes data of 2002 Jun 05 2002 Sep 27 Philips Semiconductors Product data 14-bit SSTL_2 registered driver with differential clock inputs SSTV16857 FEATURES PIN CONFIGURATION • Stub-series terminated logic for 2.5 V VDDQ (SSTL_2) • Optimized for DDR (Double Data Rate) SDRAM applications • Inputs compatible with JESD8–9 SSTL_2 specifications. • Flow-through architecture optimizes PCB layout • ESD classification testing is done to JEDEC Standard JESD22. Protection exceeds 2000 V to HBM per method A114. • Latch-up testing is done to JEDEC Standard JESD78, which exceeds 100 mA. • Same form, fit, and function as SSTL16877 • Full DDR 200/266 solution @ 2.5 V when used with PCKV857 • See SSTV16856 for driver/buffer version with mode select. • Available in TSSOP-48, TVSOP-48 and 56 ball VFBGA packages DESCRIPTION The SSTV16857 is a 14-bit SSTL_2 registered driver with differential clock inputs, designed to operate between 2.3 V and 2.7 V. VDDQ must not exceed VCC. Inputs are SSTL_2 type with VREF normally at 0.5*VDDQ. The outputs support class I which can be used for standard stub-series applications or capacitive loads. Master reset (RESET) asynchronously resets all registers to zero. The SSTV16857 is intended to be incorporated into standard DIMM (Dual In-Line Memory Module) designs defined by JEDEC, such as DDR (Double Data Rate) SDRAM or SDRAM II Memory Modules. Different from traditional SDRAM, DDR SDRAM transfers data on both clock edges (rising and falling), thus doubling the peak bus bandwidth. A DDR DRAM rated at 133 MHz will have a burst rate of 266 MHz. The modules require between 23 and 27 registered control and address lines, so two 14-bit wide devices will be used on each module. The SSTV16857 is intended to be used for SSTL_2 input and output signals. The device data inputs consist of differential receivers. One differential input is tied to the input pin while the other is tied to a reference input pad, which is shared by all inputs. Q1 1 48 D1 Q2 2 47 D2 GND 3 46 GND VDDQ 4 45 VCC Q3 5 44 D3 Q4 6 43 D4 Q5 7 42 D5 GND 8 41 D6 VDDQ 9 40 D7 Q6 10 39 CLK– Q7 11 38 CLK+ VDDQ 12 37 VCC GND 13 36 GND Q8 14 35 VREF Q9 15 34 RESET VDDQ 16 33 D8 GND 17 32 D9 Q10 18 31 D10 Q11 19 30 D11 Q12 20 29 D12 VDDQ 21 28 VCC GND 22 27 GND Q13 23 26 D13 Q14 24 25 D14 SW00685 The clock input is fully differential to be compatible with DRAM devices that are installed on the DIMM. However, since the control inputs to the SDRAM change at only half the data rate, the device must only change state on the positive transition of the CLK signal. In order to be able to provide defined outputs from the device even before a stable clock has been supplied, the device must support an asynchronous input pin (reset), which when held to the LOW state will assume that all registers are reset to the LOW state and all outputs drive a LOW signal as well. QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr =tf v2.5 ns TYPICAL UNIT Propagation delay; CLK to Qn PARAMETER CL = 30 pF; VDDQ = 2.5 V 2.4 ns Input capacitance VCC = 2.5 V 2.9 pF SYMBOL tPHL/tPLH CI CONDITIONS ORDERING INFORMATION TEMPERATURE RANGE ORDER CODE DWG NUMBER 48-Pin Plastic TSSOP PACKAGES 0 to +70 °C SSTV16857DGG SOT362-1 48-Pin Plastic TSSOP (TVSOP) 0 to +70 °C SSTV16857DGV SOT480-1 56-Ball Plastic VFBGA 0 to +70 °C SSTV16857EV SOT702-1 2002 Sep 27 2 Philips Semiconductors Product data 14-bit SSTL_2 registered driver with differential clock inputs SSTV16857 PIN DESCRIPTION PIN NUMBER LOGIC DIAGRAM SYMBOL NAME AND FUNCTION RESET 34 48, 47, 44, 43, 42, 41, 40, 33, 32, 31, 30, 29, 26, 25 LVCMOS asynchronous master reset (Active LOW) RESET D1 – D14 VREF D1 REGISTER Q1 D2 REGISTER Q2 D3 REGISTER Q3 D4 REGISTER Q4 D5 REGISTER Q5 D6 REGISTER Q6 D7 REGISTER Q7 D8 REGISTER Q8 D9 REGISTER Q9 D10 REGISTER Q10 D11 REGISTER Q11 D12 REGISTER Q12 D13 REGISTER Q13 D14 REGISTER Q14 SSTL_2 data inputs 1, 2, 5, 6, 7, 10, 11, 14, 15, 18, 19, 20, 23, 24 Q1 – Q14 35 VREF SSTL_2 input reference level 3, 8, 13, 17, 22, 27, 36, 46 GND Ground (0 V) 28, 37, 45 VCC Positive supply voltage 4, 9, 12, 16, 21 VDDQ Output supply voltage 38 39 CLK+ CLK– Differential clock inputs SSTL_2 data outputs FUNCTION TABLE OUTPUT INPUTS RESET CLK CLK D Q L X X X L H ↓ ↑ H H H ↓ ↑ L L H L or H L or H X Q0 H = High voltage level L = High voltage level ↓ = High-to-Low transition ↑ = Low-to-High transition X = Don’t care CLK+ CLK– 2002 Sep 27 3 SW00763 Philips Semiconductors Product data 14-bit SSTL_2 registered driver with differential clock inputs SSTV16857 BALL CONFIGURATION 1 2 3 4 5 6 A Q1 NC NC NC NC D1 B GND Q2 VCC VCC D2 GND C Q4 Q3 Q5 D5 D3 D4 D VCC GND Q6 CLK– D6 D7 E VCC Q7 CLK+ VCC F GND Q8 VREF GND G VCC GND Q9 RESET D9 D8 H Q11 Q12 Q10 D10 D12 D11 J GND Q13 VCC VCC D13 GND K Q14 NC NC NC NC D14 SW00952 ABSOLUTE MAXIMUM RATINGS1 SYMBOL PARAMETER VCC DC supply voltage IIK DC input diode current VI DC input voltage3 IOK DC output diode current VOUT DC output voltage3 IOUT O CONDITION VI < 0 VO < 0 LIMITS UNIT MIN MAX –0.5 +4.6 V — –50 mA –0.5 VDDQ + 0.5 V — –50 mA V –0.5 VDDQ + 0.5 DC output current VO = 0 to VDDQ — ±50 Continuous current4 VCC, VDDQ, or GND — ±100 mA Tstg Storage temperature range2 –65 +150 °C NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 4. The continuous current at VCC, VDDQ, or GND should not exceed ±100 mA. 2002 Sep 27 4 Philips Semiconductors Product data 14-bit SSTL_2 registered driver with differential clock inputs SSTV16857 RECOMMENDED OPERATING CONDITIONS1 PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT VCC Supply voltage 2.3 2.5 2.7 V VDDQ Output supply voltage 2.3 2.5 2.7 V VREF Reference voltage (VREF = 0.5 x VDDQ) 1.15 1.25 1.35 VTT Termination voltage VREF – 40 mV VREF VREF + 40 mV V VI Input voltage 0 — VCC V VIH AC HIGH-level input voltage All inputs VREF + 350 mV — — V VIL AC LOW-level input voltage All inputs — — VREF – 350 mV V VIH DC HIGH-level input voltage All inputs VREF + 180 mV — VDDQ + 0.5 V V All inputs V VIL DC LOW-level input voltage VSS – 0.5 V — VREF – 180 mV V IOH HIGH-level output current — — –20 mA IOL LOW-level output current — — 20 mA 0 — 70 °C Tamb Operating free-air temperature range NOTE: 1. Unused control inputs must be held HIGH or LOW to prevent them from floating. DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V). LIMITS SYMBOL VIK PARAMETER I/O supply voltage VOH HIGH level output voltage VOL O LOW level output voltage TEST CONDITIONS Temp = 0 to +70 °C UNIT MIN TYP2 MAX — — –1.2 VCC – 0.2 — — 1 95 1.95 — — VCC = 2.3 V to 2.7 V; IOL = 100 µA — — 0.2 VCC = 2.3 V; IOL = 16 mA — — 0.35 — 1.53 V mV VCC = 2.3 V; II = –18 mA VCC = 2.3 V to 2.7 V; IOH = –100 µA VCC = 2 2.3 3 V; IOH = –16 16 mA VCMR CLK, CLK Common mode range for reliable performance 0.97 VPP CLK, CLK Minimum peak-to-peak input to ensure logic state 360 — — — 0.01 ±5 — 0.01 ±5 — 0.05 ±5 — 0.05 ±5 Data inputs inputs, RESET II ICC CLK CLK CLK, VCC = 2.7 V; VI = 1.7 V or 0.8 V VCC = 2.7 V; VI = 2.7 V or 0 V VCC = 2.7 V; VI = 1.7 V or 0.8 V VCC = 2.7 V; VI = 2.7 V or 0 V 15 V or 1 35 V VREF = 1 1.15 1.35 VREF = 1 1.15 15 V or 1 1.35 35 V V µA µA VREF VCC = 2.7 V VREF = 1.15 V or 1.35 V — 0.05 ±5 µA Quiescent supply current CLK and CLK in opposite state1 VCC = 2.7 V; VI = 1.7 V or 0.8 V RESET = GND — 0.5 10 µA VCC = 2.7 V; VI = 2.7 V or 0 V RESET = VCC — 10 25 mA NOTES: 1. When CLK and CLK are HIGH, typical ICC = 25 mA. 2. All typical values are at VCC = 2.5 V and Tamb = 25 °C (unless otherwise specified). 2002 Sep 27 V 5 Philips Semiconductors Product data 14-bit SSTL_2 registered driver with differential clock inputs SSTV16857 TIMING REQUIREMENTS Over recommended operating conditions; Tamb = 0 to +70 °C (unless otherwise noted) (see Figure 1) LIMITS SYMBOL fclock PARAMETER VCC = 2.5 V ±0.2 V TEST CONDITIONS MIN MAX UNIT Clock frequency — 200 MHz tw Pulse duration, CLK, CLK HIGH or LOW 1.0 — ns Data before CLK↑, CLK↓ 0.2 — tsu Setup time RESET HIGH before CLK↑, CLK↓ 0.8 — th Hold time 0.75 — ns ns SWITCHING CHARACTERISTICS Over recommended operating conditions; Tamb = 0 to +70 °C; VDDQ = 2.3 – 2.7 V and VDDQ does not exceed VCC. Class I, VREF = VTT = VDDQ × 0.5 and CL = 10 pF (unless otherwise noted) (see Figure 1) LIMITS FROM (INPUT) SYMBOL TO (OUTPUT) VCC = 2.5 V ±0.2 V MIN fmax tPLH/tPHL tPHL Maximum clock frequency MAX 200 — MHz CLK and CLK Q 1.0 2.8 ns RESET Q 2.0 4.0 ns SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM 184/200-pin DDR SDRAM DIMM FRONT SIDE SSTV16857 SSTV16857 PCKV857 The PLL clock distribution device and SSTV registered drivers reduce signal loads on the memory controller and prevent timing delays and waveform distortions that would cause unreliable operation SW00686 2002 Sep 27 UNIT 6 Philips Semiconductors Product data 14-bit SSTL_2 registered driver with differential clock inputs SSTV16857 PARAMETER MEASUREMENT INFORMATION AC WAVEFORMS VIH CLK VREF tW VIH VREF INPUT VREF VIL tPLH VREF tPHL VIL VOH VREF OUTPUT SW00339 VREF Waveform 3. Pulse duration VOL SW00836 Waveform 1. Propagation delay times VIH TIMING INPUT VREF VIH VIL RESET VREF tsu th VIL VIH tPHL DATA INPUT VOH OUTPUT VREF VREF VREF VIL VOL SW00837 SW00340 Waveform 2. Propagation delay RESET to output. Waveform 4. Setup and hold times TEST CIRCUIT VTT 50 Ω TEST POINT CL = 30 pF NOTES: CL includes probe and jig capacitance All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 1.25 ns/V, tf 1.25 ns/V. The outputs are measured one at a time with one transition per measurement. VTT = VREF = VDDQ x 0.5 SW00838 Figure 1. Load circuitry 2002 Sep 27 7 Philips Semiconductors Product data 14-bit SSTL_2 registered driver with differential clock inputs SSTV16857 TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm 2002 Sep 27 8 SOT362-1 Philips Semiconductors Product data 14-bit SSTL_2 registered driver with differential clock inputs SSTV16857 TSSOP48: plastic thin shrink small outline package; 48 leads; body width 4.4 mm; lead pitch 0.4 mm SOT480-1 E D A X c y H v E A M Z 25 48 Q A (A 3) 2 A A 1 pin 1 index θ L p L detail X 1 24 w b e 0 M p 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) A UNIT max. mm 1.10 A1 A2 0.15 0.95 0.05 0.85 A3 0.25 D (1) E (2) bp c 0.23 0.20 9.80 4.50 0.13 0.09 9.60 4.30 e 0.40 HE 6.60 6.20 L 1.00 Lp Q 0.70 0.40 0.50 0.30 v w y 0.20 0.07 0.08 Z (1) 0.40 8 0.10 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC EUROPEAN EIAJ PROJECTION ISSUE DATE 97–03–20 SOT480–1 2002 Sep 27 MO–153 99–12–27 9 θ o o Philips Semiconductors Product data 14-bit SSTL_2 registered driver with differential clock inputs SSTV16857 VFBGA56: plastic very thin fine-pitch ball grid array package; 56 balls; body 4.5 x 7 x 0.65 mm 2002 Sep 27 10 SOT702-1 Philips Semiconductors Product data 14-bit SSTL_2 registered driver with differential clock inputs REVISION HISTORY Rev Date SSTV16857 Description _6 2002 Sep 27 Product data (9397 750 10412); sixth version supersedes Product data fifth version, 2002 Jun 05. Engineering Change Notice: 853 2224 28989 (2002 Sep 26). Modifications: Package type changed from SSTV16857EC to SSTV16857EV. _5 2002 Jun 05 Product data (9397 750 09942); fifth version. 2002 Sep 27 11 Philips Semiconductors Product data 14-bit SSTL_2 registered driver with differential clock inputs SSTV16857 Data sheet status Data sheet status [1] Product status [2] Definitions Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Koninklijke Philips Electronics N.V. 2002 All rights reserved. Printed in U.S.A. Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 Date of release: 09-02 For sales offices addresses send e-mail to: [email protected]. Document order number: 2002 Sep 27 12 9397 750 10412