PHILIPS PCK2001

INTEGRATED CIRCUITS
PCK2001
14.318-150 MHz I2C 1:18 Clock Buffer
Product specification
Supersedes data of 1998 Oct 27
1999 Jul 06
Philips Semiconductors
Product specification
14.318–150 MHz I2C 1:18 Clock Buffer
PCK2001
• Individual clock output enable/disable via I2C
FEATURES
• HIGH speed, LOW noise non-inverting 1–18 buffer
• Typically used to support four SDRAM DIMMs
• Multiple VDD, VSS pins for noise reduction
• 3.3V operation
• Separate 3-State pin for testing
• ESD protection exceeds 2000V per Standard 801.2
• Optimized for 66MHz, 100MHz and 133MHz operation
• 175 ps skew outputs
• Available in 48-pin SSOP package
• See PCK2001M for mobile (reduced pincount) 28-pin 1-10 buffer
DESCRIPTION
The PCK2001 is a 1–18 fanout buffer used for 133/100 MHz CPU,
66/33 MHz PCI, 14.318 MHz REF, or 133/100/66 MHz SDRAM
clock distribution. 18 outputs are typically used to support up to 4
SDRAM DIMMS commonly found in desktop, workstation or server
applications.
All clock outputs meet Intel’s drive, rise/fall time, accuracy, and skew
requirements. An I2C interface is included to allow each output to be
enabled/disabled individually. An output disabled via the I2C
interface will be held in the LOW state. In addition, there is an OE
input which 3-States all outputs.
version
QUICK REFERENCE DATA
SYMBOL
tPLH
tPHL
PARAMETER
CONDITIONS
TYPICAL
UNIT
2.5
2.5
ns
VCC = 3.3V, CL = 30pF
1.0
ns
VCC = 3.3V, CL = 20pF
700
ps
VCC = 3.465V
50
µA
Propagation delay
BUF_IN to BUF_OUTn
VCC = 3.3V, CL = 30pF
tr
Rise time
tf
Fall time
Total supply current
ICC
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
DRAWING NUMBER
48-Pin Plastic SSOP
0°C to +70°C
PCK2001 DL
SOT370-1
PIN CONFIGURATION
PIN DESCRIPTION
VDD0 1
48 RESERVED
RESERVED 2
47 RESERVED
RESERVED 3
46 VDD9
BUF_OUT0 4
BUF_OUT1 5
45 BUF_OUT15
44 BUF_OUT14
VSS0 6
43 VSS9
VDD1 7
42 VDD8
BUF_OUT2 8
41 BUF_OUT13
BUF_OUT3 9
VSS1 10
40 BUF_OUT12
39 VSS8
VDD2 12
BUF_OUT4 13
BUF_OUT5 14
VSS2 15
VDD3 16
BUF_OUT6 17
BUF_OUT7 18
38 OE
PCK2001
BUF_IN 11
37 VDD7
35 BUF_OUT10
33 VDD6
32 BUF_OUT9
31 BUF_OUT8
VDD4 20
29 VDD5
VDDI2C 23
SDA 24
28 BUF_OUT17
27 VSS5
26 VSSI2C
25 SCL
SW00248
I2C is a trademark of Philips Semiconductors Corporation.
1999 Jul 06
SYMBOL
FUNCTION
4, 5, 8, 9
Output
BUF_OUT (0–3)
Buffered clock outputs
13, 14, 17,
18
Output
BUF_OUT (4–7)
Buffered clock outputs
31, 32, 35,
36
Output
BUF_OUT
(8–11)
Buffered clock outputs
40, 41, 44,
45
Output
BUF_OUT
(12–15)
Buffered clock outputs
21, 28
Output
BUF_OUT
(16–17)
Buffered clock outputs
11
Input
BUF_IN
38
Input
OE
24
I/O
SDA
I2C serial data
25
Input
SCL
I2C serial clock
3, 7, 12, 16,
20, 29, 33,
37, 42, 46
Input
VDD (0–9)
3.3V Power supply
6, 10, 15,
19, 22,
27, 30, 34,
39, 43
Input
VSS (0–9)
Ground
23
Input
VDDI2C
3.3V I2C Power
supply
26
Input
VSSI2C
I2C Ground
34 VSS7
30 VSS6
VSS4 22
I/O
TYPE
36 BUF_OUT11
VSS3 19
BUF_OUT16 21
PIN
NUMBER
2
Buffered clock input
Active high output
enable
853-2072 21924
Philips Semiconductors
Product specification
14.318–150 MHz I2C 1:18 Clock Buffer
PCK2001
FUNCTION TABLE
OE
BUF_IN
I2CEN
BUF_OUTn
Z
L
X
X
H
L
X
L
H
H
H
H
H
H
L
L
ABSOLUTE MAXIMUM RATINGS1, 2
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to VSS (VSS = 0V)
SYMBOL
PARAMETER
VDD
DC 3.3V supply voltage
IIK
DC input diode current
VI < 0
VI
DC input voltage
Note 2
IOK
DC output diode current
VO > VDD or VO < 0
VO
DC output voltage
Note 2
IO
DC output source or sink current
VO >= 0 to VDD
TSTG
Storage temperature range
PTOT
Power dissipation per package
plastic medium-shrink SO (SSOP)
LIMITS
CONDITION
UNIT
MIN
MAX
–0.5
+4.6
V
–50
mA
–0.5
–0.5
–65
For temperature range: 0 to +70°C
above +55°C derate linearly with 11.3mW/K
5.5
V
±50
mA
VCC + 0.5
V
±50
mA
+150
°C
850
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
VDD
CONDITIONS
LIMITS
UNIT
MIN
MAX
DC 3.3V supply voltage
3.135
3.465
V
CL
Capacitive load
20
30
pF
VI
DC input voltage range
0
VDD
V
VO
DC output voltage range
0
VDD
V
Tamb
Operating ambient temperature range in free air
0
+70
°C
1999 Jul 06
3
Philips Semiconductors
Product specification
14.318–150 MHz I2C 1:18 Clock Buffer
PCK2001
DC CHARACTERISTICS
SYMBOL
PARAMETER
VDD
VIH
LIMITS
TEST CONDITIONS
(V)
HIGH level input voltage
3.135 to 3.465
Tamb = 0°C to +70°C
OTHER
UNIT
MIN
MAX
2.0
VDD + 0.3
V
VIL
LOW level input voltage
3.135 to 3.465
VSS – 0.3
0.8
V
VOH
3.3V output HIGH voltage
3.135 to 3.465
IOH = –1mA
2.4
–
V
VOL
3.3V output LOW voltage
3.135 to 3.465
IOL= 1mA
–
0.4
V
IOH
O
Output HIGH current
3.135 to 3.465
VOUT = 2.0V
–54
–
3.135 to 3.465
VOUT = 3.135V
–
–46
IOL
O
Output LOW current
3.135 to 3.465
VOUT = 1.0V
54
–
3.135 to 3.465
VOUT = 0.4V
–
53
±II
Input leakage current
3.465
–
5
µA
±IOZ
3-State output OFF-State
current
3.465
VOUT = VDDor GND
IO = 0
–
10
µA
ICC
Quiescent supply current
3.465
VI = VDD or GND
IO = 0
–
100
µA
∆ICC
Additional quiescent supply
current given per control pin
3.135 to 3.465
VI = VDD– 0.6V
IO = 0
–
500
µA
1999 Jul 06
4
mA
mA
Philips Semiconductors
Product specification
14.318–150 MHz I2C 1:18 Clock Buffer
PCK2001
SDRAM CLOCK OUTPUT BUFFER PULL-UP CHARACTERISTICS
PULL-UP
I
(mA)
VOLTAGE
(V)
MIN
TYP
MAX
0
–72
–116
–198
1
–72
–116
–198
1.40
–68
–110
–188
1.50
–67
–107
–184
1.65
–64
–103
–177
1.80
–60
–98
–170
2.00
–54
–90
–157
2.40
–39
–69
–126
2.60
–30
–56
–107
3.135
0
–15
–46
0
–23
3.30
3.465
0
SDRAM PULL-UP
0
0.25
0.5 0.75
1
1.25
1.5 1.75
2
2.25 2.5 2.75
3
3.25
3.5
0
–20
–40
–60
MIN
–80
TYP
MAX
IOH (mA)
–100
–120
–140
–160
–180
–200
VOUT (V)
SW00249
1999 Jul 06
5
Philips Semiconductors
Product specification
14.318–150 MHz I2C 1:18 Clock Buffer
PCK2001
SDRAM CLOCK OUTPUT BUFFER PULL-DOWN CHARACTERISTICS
PULL-UP
I
(mA)
VOLTAGE
(V)
MIN
TYP
MAX
0
0
0
0
0.4
23
34
53
0.65
35
52
83
0.85
43
65
104
1.00
49
74
118
1.4
61
93
152
1.5
64
98
159
1.65
67
103
168
1.8
70
108
177
1.95
72
112
184
3.135
72
112
204
112
204
3.6
SDRAM PULL-DOWN
225
200
175
150
IOL (mA)
MIN
125
TYP
100
MAX
75
50
25
0
0
0.4
0.8
1.2
1.6
2
2.4
2.8
3.2
3.6
VOUT (V)
SW00250
1999 Jul 06
6
Philips Semiconductors
Product specification
14.318–150 MHz I2C 1:18 Clock Buffer
PCK2001
AC CHARACTERISTICS
SYMBOL
PARAMETER
TSDKP
SDRAM CLK period
TSDKH
SDRAM CLK HIGH time
LIMITS
Tamb = 0°C to +70°C
TEST CONDITIONS
66MHz
UNIT
NOTES
MIN
TYP9
MAX
1, 6
15.0
15.2
15.5
2, 6, 8
5.6
7.8
8.4
ns
TSDKL
SDRAM CLK LOW time
3, 6, 8
5.3
7.4
8.0
TSDKP
SDRAM CLK period
1, 6
10.0
10.01
10.5
TSDKH
SDRAM CLK HIGH time
2, 6, 8
3.3
5.1
5.7
TSDKL
SDRAM CLK LOW time
3, 6, 8
3.1
4.9
5.5
TSDKP
SDRAM clock period
1, 6
7.4
7.5
7.7
TSDKH
SDRAM CLK HIGH time
2, 6, 8
2.6
3.2
3.8
TSDKL
SDRAM CLK LOW time
3, 6, 8
2.1
2.8
3.5
TSDRISE
SDRAM rise time
4, 6, 10
1.5
2.0
4.0
V/ns
TSDFALL
SDRAM fall time
4, 6, 11
1.5
2.9
4.0
V/ns
TPLH
SDRAM buffer LH propagation delay
6, 7
1.0
2.5
3.5
ns
TPHL
SDRAM buffer HL propagation delay
6, 7
1.0
2.5
3.5
ns
TPZL, TPZH
SDRAM buffer enable time
6, 7
1.0
2.6
5.0
ns
TPLZ, TPHZ
SDRAM buffer disable time
6, 7
1.0
2.7
5.0
ns
5, 6, 7
45
DUTY CYCLE
Output Duty Cycle
TSDSKW
SDRAM Bus CLK skew
TDDSKW
Device to device skew
100MHz
133MHz
Measured at 1.5V
1, 6
ns
ns
52
55
%
150
250
ps
250
ps
NOTES:
1. Clock period and skew are measured on the rising edge at 1.5V.
2. TSDKH is measured at 2.4V as shown in Figure 4.
3. TSDKL is measured at 0.4V as shown in Figure 4.
4. TSDRISE and TSDFALL are measured as a transition through the threshold region VOL = 0.4V and VOH = 2.4V (1mA) JEDEC specification.
5. Duty cycle should be tested with a 50/50% input.
6. Over MIN (20pF) to MAX (30pF) discrete load, process, voltage, and temperature.
7. Input edge rate for these tests must be faster than 1 V/ns.
8. Calculated at minimum edge rate (1.5ns) to guarantee 45/55% duty cycle at 1.5V. Pulsewidth is required to be wider at the faster edge to
ensure duty cycle specification is met.
9. All typical values are at VCC = 3.3V and Tamb = 25°C.
10. Typical is measured with MAX (30pf) discrete load.
11. Typical is measured with MIN (20pf) discrete load.
1999 Jul 06
7
Philips Semiconductors
Product specification
14.318–150 MHz I2C 1:18 Clock Buffer
PCK2001
I2C CONSIDERATIONS
I2C has been chosen as the serial bus interface to control the PCK2001. I2C was chosen to support the JEDEC proposal JC-42.5 168 Pin
Unbuffered SDRAM DIMM. All vendors are required to determine the legal issues associated with the manufacture of I2C devices.
1) Address assignment: The clock driver in this specification uses the single, 7-bit address shown below. All devices can use the address if only
one master clock driver is used in a design. The address can be re-used for the CKBF device if no other conflicting I2C clock driver is used in
the system.
The following address was confirmed by Philips on 09/04/96.
A6
A5
A4
A3
A2
A1
A0
R/W#
1
1
0
1
0
0
1
0
NOTE: The R/W# bit is used by the I2C controller as a data direction bit. A ‘zero’ indicates a transmission (WRITE) to the clock device. A ‘one’
indicates a request for data (READ) from the clock driver. Since the definition of the clock buffer only allows the controller to WRITE data; the
R/W# bit of the address will always be seen as ‘zero’. Optimal address decoding of this bit is left to the vendor.
2) Options: It is our understanding that metal mask options and other pinouts of this type of clock driver will be allowed to use the same address
as the original CKBF device. I2C addresses are defined in terms of function (master clock driver) rather than form (pinout, and option).
3) Slave/Receiver: The clock driver is assumed to require only slave/receiver functionality. Slave/transmitter functionality is optional.
4) Data Transfer Rate: 100 kbits/s (standard mode) is the base functionality required. Fast mode (400 kbits/s) functionality is optional.
5) Logic Levels: I2C logic levels are based on a percentage of VDD for the controller and other devices on the bus. Assume all devices are
based on a 3.3 Volt supply.
6) Data Byte Format: Byte format is 8 Bits as described in the following appendices.
7) Data Protocol: To simplify the clock I2C interface, the clock driver serial protocol was specified to use only block writes from the controller.
The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been
transferred. Indexed bytes are not allowed. However, the SMBus controller has a more specific format than the generic I2C protocol.
The clock driver must meet this protocol which is more rigorous than previously stated I2C protocol. Treat the description from the viewpoint of
controller. The controller ‘‘writes” to the clock driver and if possible would ‘‘read” from the clock driver (the clock driver is a slave/receiver only
and is incapable of this transaction.)
‘‘The block write begins with a slave address and a write condition. After the command code the host (controller) issues a byte count which
describes how many more bytes will follow in the message. If the host had 20 bytes to send, the first byte would be the number 20 (14h),
followed by the 20 bytes of data. The byte count may not be 0. A block write command is allowed to transfer a maximum of 32 data bytes.”
1 bit
7 bits
1
1
8 bits
1
Start bit
Slave Address
R/W
Ack
Command Code
Ack
Ack
Data Byte 1
Ack
Data Byte 2
Ack
1 bit
8 bits
1
8 bits
1
...
Byte Count = N
Data Byte 2
Ack
Stop
8 bits
1
1
SW00279
NOTE: The acknowledgement bit is returned by the slave/receiver (the clock driver).
1999 Jul 06
8
Philips Semiconductors
Product specification
14.318–150 MHz I2C 1:18 Clock Buffer
PCK2001
Consider the command code and the byte count bytes required as the first two bytes of any transfer. The command code is software
programmable via the controller, but will be specified as 0000 0000 in the clock specification. The byte count byte is the number of additional
bytes required to transfer, not counting the command code and byte count bytes. Additionally, the byte count byte is required to be a minimum of
1 byte and a maximum of 32 bytes to satisfy the above requirement.
For example:
Byte count byte
Notes:
MSB
LSB
0000
0000
Not allowed. Must have at least one byte.
0000
0001
Data for functional and frequency select register (currently byte 0 in spec)
0000
0010
Reads first two bytes of data. (byte 0 then byte 1)
0000
0011
Reads first three bytes (byte 0, 1, 2 in order)
0000
0100
Reads first four bytes (byte 0, 1, 2, 3 in order)
0000
0101
Reads first five bytes (byte 0, 1, 2, 3, 4 in order)
0000
0110
Reads first six bytes (byte 0, 1, 2, 3, 4, 5 in order)
0000
0111
Reads first seven bytes (byte 0, 1, 2, 3, 4, 5, 6 in order)
0010
0000
Max byte count supported = 32
A transfer is considered valid after the acknowledge bit corresponding to the byte count is read by the controller. The serial controller interface
can be simplified by discarding the information in both the command code and the byte count bytes and simply reading all the bytes that are
sent to the clock driver after being addressed by the controller. It is expected that the controller will not provide more bytes than the clock driver
can handle. A clock vendor may choose to discard any number of bytes that exceed the defined byte count.
8) Clock stretching: The clock device must not hold/stretch the SCLOCK or SDATA lines low for more than 10 mS. Clock stretching is
discouraged and should only be used as a last resort. Stretching the clock/data lines for longer than this time puts the device in an error/time-out
mode and may not be supported in all platforms. It is assumed that all data transfers can be completed as specified without the use of
clock/data stretching.
9) General Call: It is assumed that the clock driver will not have to respond to the ‘‘general call.”
10) Electrical Characteristics: All electrical characteristics must meet the standard mode specifications found in section 15 of the I2C
specification.
a) Pull-Up Resistors: Any internal resistors pull-ups on the SDATA and SCLOCK inputs must be stated in the individual datasheet. The use of
internal pull-ups on these pins of below 100K is discouraged. Assume that the board designer will use a single external pull-up resistor for each
line and that these values are in the 5 - 6K Ohm range. Assume one I2C device per DIMM (serial presence detect), one I2C controller, one clock
driver plus one/two more I2C devices on the platform for capacitive loading purposes.
(b) Input Glitch Filters: Only fast mode I2C devices require input glitch filters to suppress bus noise. The clock driver is specified as a standard
mode device and is not required to support this feature.
11) PWR DWN#: If a clock driver is placed in PWR DWN# mode, the SDATA and SCLK inputs must be Tri-Stated and the device must retain all
programming information. Idd current due to the I2C circuitry must be characterized and in the data sheet.
For specific I2C information consult the Philips I2C Peripherals Data Handbook IC12 (1997)
1999 Jul 06
9
Philips Semiconductors
Product specification
14.318–150 MHz I2C 1:18 Clock Buffer
PCK2001
SERIAL CONFIGURATION MAP
The serial bits will be read by the clock buffer in the following order:
Byte 0 – Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 – Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 2 – Bits 7, 6, 5, 4, 3, 2, 1, 0
All unused register bits (Reserved and N/A) should be desined as “Dont Care”. It is expected that the controller will force all of these bits to a “0”
level.
All register bits labeled “Initialize to 0” must be written to zero during intialization. Failure to do so may result in a higher than normal operating
current. The controller will read back the last written value.
Byte 0: Output active/inactive register
1 = enable; 0 = disable
BIT
PIN#
NAME
DESCRIPTION
7
18
BUF_OUT7
Active/Inactive
6
17
BUF_OUT6
Active/Inactive
5
14
BUF_OUT5
Active/Inactive
4
13
BUF_OUT4
Active/Inactive
3
9
BUF_OUT3
Active/Inactive
2
8
BUF_OUT2
Active/Inactive
1
5
BUF_OUT1
Active/Inactive
0
4
BUF_OUT0
Active/Inactive
NOTE:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are
not expected to be configured during the normal modes of operation.
Byte 1: Output active/inactive register
1 = enable; 0 = disable
BIT
PIN#
NAME
DESCRIPTION
7
45
BUF_OUT15
Active/Inactive
6
44
BUF_OUT14
Active/Inactive
5
41
BUF_OUT13
Active/Inactive
4
40
BUF_OUT12
Active/Inactive
3
36
BUF_OUT11
Active/Inactive
2
35
BUF_OUT10
Active/Inactive
1
32
BUF_OUT9
Active/Inactive
0
31
BUF_OUT8
Active/Inactive
NOTE:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are
not expected to be configured during the normal modes of operation.
Byte 2: Optional register for possible future requirments
BIT
PIN#
NAME
DESCRIPTION
7
28
BUF_OUT17
Active/Inactive
6
21
BUF_OUT16
Active/Inactive
5
—
(reserved)
(reserved)
4
—
(reserved)
(reserved)
3
—
(reserved)
(reserved)
2
—
(reserved)
(reserved)
1
—
(reserved)
(reserved)
0
—
(reserved)
(reserved)
NOTE:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are
not expected to be configured during the normal modes of operation.
1999 Jul 06
10
Philips Semiconductors
Product specification
14.318–150 MHz I2C 1:18 Clock Buffer
PCK2001
AC WAVEFORMS
VM = 1.5V
VX = VOL + 0.3V
VY = VOH –0.3V
VOL and VOH are the typical output voltage drop that occur with the
output load.
tkp
tkh
1.5
0.4
VDD
BUF_IN
INPUT
VM
DUTY CYCLE
2.4
tkl
VM
tr
tPLH
tf
tPHL
SW00479
Figure 4. SDRAM Output clock
VM
VM
BUF_OUT
TEST CIRCUIT
SW00246
Figure 1. Load circuitry for switching times.
S1
VDD
2<VDD
Open
VSS
VI
VDD
VM
nOE INPUT
500Ω
VI
VO
PULSE
GENERATOR
GND
D.U.T.
RT
tPLZ
CL
500Ω
tPZL
VDD
OUTPUT
LOW-to-OFF
OFF-to-LOW
VM
VX
VOL
tPHZ
tPZH
TEST
S1
tPLH/tPHL
Open
tPLZ/tPZL
2<VDD
tPHZ/tPZH
VSS
VOH
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
VY
SW00251
VM
VSS
outputs
enabled
Figure 5. Load circuitry for switching times
outputs
enabled
outputs
disabled
SW00245
Figure 2. 3-State enable and disable times
TSDKP
TSDKH
DUTY CYCLE
2.4
1.5
0.4
TSDKL
TSDRISE
TSDFALL
SW00247
Figure 3. Buffer Output clock
1999 Jul 06
11
Philips Semiconductors
Product specification
14.318–150 MHz I2C 1:18 Clock Buffer
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm
1999 Jul 06
12
PCK2001
SOT370-1
Philips Semiconductors
Product specification
14.318–150 MHz I2C 1:18 Clock Buffer
PCK2001
Data sheet status
Data sheet
status
Product
status
Definition [1]
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
 Copyright Philips Electronics North America Corporation 1999
All rights reserved. Printed in U.S.A.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 07-99
Document order number:
1999 Jul 06
13
9397-750-06208