SAA7893HL Super audio media player Rev. 02 — 26 February 2003 Product data 1. General description Thanks to the superior sound quality and multichannel capability of Super Audio CD (SACD) technology, multimedia devices such as DVD players and home cinema systems are incorporating SACD functionality. Philips' Super Audio Media Player (SA-MP) provides a flexible, state-of-the-art solution for SACD playback on DVD architectures. Built around the SAA7893HL SACD processor, SA-MP system solution delivers complete SACD functionality, avoiding the need for continual redesign and re-integration of SACD into various applications. The system is completed with a single 64 Mbit SDRAM and has extensive software processing options, resulting in low total system cost (see Figure 1). With integrated support for multiple loaders, the SAA7893 supports a variety of DVD platforms. High level and standard software interfaces – optimized for easy design-in – further enhance adaptability, enabling designers to build SACD players on many different hardware and software platforms. This ensures that the SA-MP can be left unchanged even if the SACD playback hardware is altered, again minimizing development effort. DVD HOST IC DVD SW STACK ANNEX J+ PLAYBACK API SACD TEXT AND DATA API SPEAKER SETUP API SW PSP DECODER SACD DEMUX DST DECODER BE SWITCH DSD POSTPROCESSOR PCM CONVERTER DSD CONVERTER DAC SWITCH HW HW D/A SAA7893HL SA-MP DVD host Fig 1. General block diagram. 64 Mbit SDRAM MGU724 DVD host DAC out SAA7893HL Philips Semiconductors Super audio media player 1.1 Hardware The SA-MP hardware consists of the SAA7893HL device. A typical HW block diagram of a DVD system incorporating the SAA7893HL is shown in Figure 2. The SAA7893HL takes sector data from the front-end. The front-end is controlled by the DVD host via the SA-MP software stack. The SAA7893HL uses one 64 Mbit SDRAM for audio data buffering and storage of SACD TOCs. The front-end timing can be fully asynchronous from all clocks. The 6-channel DAC outputs of the DVD host are routed via the SAA7893HL which provides a DAC switch function between SACD mode and DVD mode. The audio outputs of the SAA7893HL operate on the system audio clock. The DVD back-end communicates with the SAA7893HL via a host bus. The system clock and the system audio clock are allowed to be asynchronous. NVRAM SDRAM control video DVD BACK-END FRONTdata END host bus 27 MHz audio clock ROM PLL audio EFM SAA7893HL audio SDRAM MGU726 Fig 2. Hardware block diagram. 1.2 Software The SA-MP software is delivered in the form of a library in the development environment of the DVD host. The SA-MP software has been developed in ANSI-C using conventional software technology to allow easy integration into any development environment. A typical software block diagram of a DVD system incorporating SA-MP is shown in Figure 3. At the device driver and HW-level, SA-MP interfaces with the SAA7893HL and a front-end driver. At the infrastructure level, SA-MP interfaces with an Operating System Abstraction layer (OSA). At the application level, SA-MP provides a high-level playback and post-processing interface which is easy to integrate into typical applications. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 2 of 66 SAA7893HL Philips Semiconductors Super audio media player APPLICATION LAYER - "SACD PLAYER BEHAVIOUR" Annex J+ MEDIA PLAYERS SA-MP POSTPROCESSING LOADER etc. UI SUBSYSTEM "LOOK-AND-FEEL" DEVICE DRIVERS UI DEVICE DRIVERS HW I/O PERIPHERALS DEVICE DRIVERS INFRASTRUCTURE (OSA) MGU725 SAA7893HL HW Fig 3. Software block diagram. 2. Features 2.1 Components ■ SAA7893HL second generation SACD processor IC ■ SA-MP Annex J+ level software stack. 2.2 HW interfaces ■ Front-end, supports 3 types: ◆ UDE ◆ FEC ◆ I2S-bus ■ Flexible PSP detection from EFM signal with AGC, without EFM clock (digital PLL) ■ (DVD-)host bus, supports 3 types: ◆ Separate address/data bus (SAD16) with 16-bit data bus (3 different modes) ◆ Multiplexed address/data bus (MAD16) with 16-bit data bus (2 different modes) ◆ Separate address/data bus (SAD08) with 8-bit data bus (1 mode) ■ 16-bit 100 MHz SDRAM interface supports one 64 Mbit device ■ 6-channel I2S-PCM audio input 44.1, 48, 88.2, 96, 176.4 or 192 kHz at 16-bit or 24-bit ■ 6-channel DSD or I2S-PCM (2fs or 4fs) output with programmable pinning configuration ■ 2-channel DSD or I2S-PCM (2fs or 4fs) output with programmable pinning configuration ■ Audio clock reference 256fs, 384fs, 512fs or 768fs ■ System clock 27 to 35 MHz. 2.3 SW interfaces ■ Annex J+ level playback interface © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 3 of 66 SAA7893HL Philips Semiconductors Super audio media player ■ High-level audio post-processing control ■ SACD data interface ■ System configuration 2.4 System ■ Full SACD Menu TOC and Area TOC storage in VBR ■ Front-end clock asynchronous to other clocks 2.5 System configuration ■ D/A converters: ◆ DSD and PCM selectable pin sharing configuration ◆ DSD clock polarity ■ Audio and system clock asynchronous ■ Front-end type 2.6 SACD playback ■ SACD playback: ◆ Multi-channel ◆ 2-channel ■ PSP processing ■ Decrypting and demultiplexing ■ VBR management ■ DST decoding ■ Fade processing ■ Annex J+ level software interface: ◆ Stop ◆ Pause ◆ Play ◆ Fast forward ◆ Fast reverse ◆ Next/previous track ◆ Program and play playlist ◆ Repeat (Track, All or AB) ◆ Shuffle ◆ Introscan ◆ Time search 2.7 Audio postprocessing ■ DSD Bass Management with support of: ◆ Dolby® configuration 0 (LLL1) ◆ Dolby® configuration 1 (SSS1) ◆ Dolby® configuration 2 (LSS0) ■ Programmable bass filter frequency and slope: © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 4 of 66 SAA7893HL Philips Semiconductors Super audio media player ■ ■ ■ ■ ■ ◆ 60, 80, 100, 120 Hz ◆ 12, 18, 24 dB/Oct (other frequencies or slopes are possible on customer request) DSD down mixing: ◆ 2/2 ◆ 3/0 ◆ 2/0 ◆ separate 2/0 DSD attenuation function 0 to −90 dB, programmable per channel DSD delay function total 65 ms (approximately 20 meters), programmable per channel 6-channel PCM input: ◆ 44.1, 88.2, 176.4, 48, 96 or 192 kHz at 16-bit or 24-bit ◆ PCM to DSD upsampling with 3 programmable Sigma-Delta and anti-aliasing filter modes ◆ Attenuation and delay as with DSD DSD to PCM conversion 88.2, 176.4 kHz at 24-bit. 2.8 SACD data and text ■ ■ ■ ■ ■ ■ Album info Disc info Album or disc text Area text Track data Track text. 2.9 General ■ ■ ■ ■ ■ ■ E-JTAG for board test and debug 3.3 V pad supply voltage 1.8 V core supply voltage 1.8 V analog supply voltage LQFP128 package 0.18 µm CMOS process. 3. Applications ■ Consumer DVD players ■ Home cinema ■ Car audio systems. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 5 of 66 SAA7893HL Philips Semiconductors Super audio media player 4. Ordering information Table 1: Ordering information Type number Package SAA7893HL Name Description Version LQFP128 plastic low profile quad flat package; 128 leads; body 14 × 20 × 1.4 mm2 SOT425-1 5. Block diagram Figure 4 shows the block diagram of the SAA7893HL with all defined functions. to host host_sel HF AGC FRONTEND INTERFACE ADC HOST INTERFACE MEMORY MANAGER PSP-KEY DECODER key data-bus control REGISTER HOST INTERFACE SAA7893HL PI-bus DECRYPTION/ SECTOR PROCESSOR 8-CHANNEL DSD2PCM CONVERSION DEMUX SACD AUDIO INTERFACE PI-BUS CONTROL 2, 5 or 6-channel LOSSLESS DECODER SPEAKER SETUP VOLUME CONTROL DELAY SWITCH MATRIX to DSD/PCM DAC SDRAM INTERFACE MBL615 to 64 Mbit SDRAM sys_clk 27-35 MHz aud_clk 256/384/512/768*fs external PCM Fig 4. Block diagram. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 6 of 66 SAA7893HL Philips Semiconductors Super audio media player 6. Pinning information 103 D_DQ[1] 104 D_DQ[14] 105 D_DQ[0] 106 VCC_IO5 107 D_DQ[15] 108 DSD_PCM_0 109 DSD_PCM_1 110 DSD_PCM_2 111 DSD_PCM_3 112 GND_IO6 113 DSD_PCM_4 114 DSD_PCM_5 115 DSD_PCM_6 116 DSD_PCM_7 117 DSD_PCM_8 118 VCC_IO6 119 DSD_PCM_10 120 DSD_PCM_9 121 DSD_PCM_11 122 RESETn 123 H_A_sel 124 H_A[6] 125 H_A[5] 126 H_A[4] 127 H_A[3] 128 H_A[2] 6.1 Pinning H_A[1] 1 102 D_DQ[13] H_DQ[15] 2 101 D_DQ[2] H_DQ[14] 3 100 D_DQ[12] GND_IO1 4 99 GND_IO5 H_DQ[13] 5 98 D_DQ[3] H_DQ[12] 6 97 D_DQ[11] H_DQ[11] 7 96 D_DQ[4] H_DQ[10] 8 95 D_DQ[10] H_DQ[9] 9 94 D_DQ[9] VCC_IO1 10 93 D_DQ[6] H_DQ[8] 11 92 VCC_IO4 H_DQ[7] 12 91 D_DQ[8] H_DQ[6] 13 90 D_DQ[7] H_DQ[5] 14 89 D_LDQM H_DQ[4] 15 88 D_UDQM H_DQ[3] 16 87 D_DQ[5] 86 D_clk GND_IO2 17 85 VCC_Core2 H_procclock 18 VCC_Core1 19 84 GND_Core2 SAA7893HL GND_Core1 20 83 GND_IO4 sys_clk 21 82 D_CASn H_DQ[2] 22 81 D_RASn H_DQ[1] 23 80 D_Wen H_CSn 24 79 D_ADDR[11] H_DQ[0] 25 78 D_ADDR[12] H_RWn 26 77 D_ADDR[9] H_WAIT 27 76 VCC_IO3 H_IRQn 28 75 D_ADDR[13] aud_clk 29 74 D_ADDR[8] PCM_dclk_in 30 73 D_ADDR[10] PCM_wclk_in 31 72 D_ADDR[7] VDDA 32 VSSA 33 71 D_ADDR[0] biasin 34 69 GND_IO3 70 D_ADDR[6] D_ADDR[3] 64 H_sel[1] 63 H_sel[0] 62 TCK 61 TDI 60 TDO 59 VCC_IO2 58 TMS 57 TRST 56 Be_dat(7) 55 Be_dat(6) 54 Be_dat(5) 53 Be_dat(4) 52 Be_dat(3) 51 Be_dat(2) 50 Be_dat(1) 49 Data_req 48 UDE_req 47 B_BCLK/SDCLK 46 B_DATA/Be_dat(0) 45 B_WCLK/SENB 44 B_SYNC/Sync 43 65 D_ADDR[4] B_FLAG/SERR 42 66 D_ADDR[2] GND_IO7 38 PCM_LsRs_in 41 67 D_ADDR[5] VCC_IO7 37 PCM_LeRi_in 40 68 D_ADDR[1] Adcrefl 36 PCM_CeLf_in 39 Agcinp 35 MCE016 Fig 5. Pin configuration. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 7 of 66 SAA7893HL Philips Semiconductors Super audio media player 6.2 Pin description Table 2: Pin description Symbol Pin Type[1] Description H_A[1] 1 IN address bus H_DQ[15] 2 I/O10 data bus H_DQ[14] 3 I/O10 data bus GND_IO1 4 GND_IO GND I/O pads H_DQ[13] 5 I/O10 data bus H_DQ[12] 6 I/O10 data bus H_DQ[11] 7 I/O10 data bus H_DQ[10] 8 I/O10 data bus H_DQ[9] 9 I/O10 data bus VCC_IO1 10 VCC_IO VCC I/O pads H_DQ[8] 11 I/O10 data bus H_DQ[7] 12 I/O10 data bus H_DQ[6] 13 I/O10 data bus H_DQ[5] 14 I/O10 data bus H_DQ[4] 15 I/O10 data bus H_DQ[3] 16 I/O10 data bus GND_IO2 17 GND_IO GND I/O pads H_procclock 18 IN host processor EMI interface clock VCC_Core1 19 VCC_core core supply voltage GND_Core1 20 GND_core core ground sys_clk 21 IN system clock H_DQ[2] 22 I/O10 data bus H_DQ[1] 23 I/O10 data bus H_CSn 24 IN host chip select; active LOW H_DQ[0] 25 I/O10 data bus H_RWn 26 IN read = 1; write = 0 H_WAIT 27 O10 wait signal H_IRQn 28 O10 interrupt request; active LOW aud_clk 29 IN DSD audio clock PCM_dclk_in 30 IN PCM data clock PCM_wclk_in 31 IN PCM word clock VDDA 32 VDDCO VDD of ADC VSSA 33 VSSCO VSS of AGC and ADC; connected to substrate biasin 34 APIO bias current input Agcinp 35 APIO AGC positive input signal; HF in Adcrefl 36 APIO ADC decoupling VCC_IO7 37 VCC_IO VCC I/O pads GND_IO7 38 GND_IO GND I/O pads PCM_CeLf_in 39 IN PCM data center or LFE © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 8 of 66 SAA7893HL Philips Semiconductors Super audio media player Table 2: Pin description…continued Symbol Pin Type[1] Description PCM_LeRi_in 40 IN PCM data left or right PCM_LsRs_in 41 IN PCM data left or right surround B_FLAG/SERR 42 IN I2S-bus flag (EDC flag) B_SYNC/Sync 43 IN sector sync or absolute time sync B_WCLK/SENB 44 IN I2S-bus word clock or UDE data sense from host B_DATA/Be_dat(0) 45 IN I2S-bus data or LSB data of parallel interface B_BCLK/SDCLK 46 IN I2S-bus bit clock UDE_req 47 IN host request data from front-end; routed via the SAA7893HL Data_req 48 O10 data request for UDE Be_dat(1) 49 IN front-end parallel data interface Be_dat(2) 50 IN front-end parallel data interface Be_dat(3) 51 IN front-end parallel data interface Be_dat(4) 52 IN front-end parallel data interface Be_dat(5) 53 IN front-end parallel data interface Be_dat(6) 54 IN front-end parallel data interface Be_dat(7) 55 IN front-end parallel data interface TRST 56 IN1 boundary scan reset TMS 57 IN1 boundary scan mode select VCC_IO2 58 VCC_IO VCC I/O pads TDO 59 O10 output TDI 60 IN1 boundary scan data input TCK 61 IN boundary scan clock H_sel[0] 62 IN host select signals: SAD16, MAD16 and SAD08 H_sel[1] 63 IN host select signals: SAD16, MAD16 and SAD08 D_ADDR[3] 64 O10 SDRAM address bus D_ADDR[4] 65 O10 SDRAM address bus D_ADDR[2] 66 O10 SDRAM address bus D_ADDR[5] 67 O10 SDRAM address bus D_ADDR[1] 68 O10 SDRAM address bus GND_IO3 69 GND_IO GND I/O pads D_ADDR[6] 70 O10 SDRAM address bus D_ADDR[0] 71 O10 SDRAM address bus D_ADDR[7] 72 O10 SDRAM address bus D_ADDR[10] 73 O10 SDRAM address bus D_ADDR[8] 74 O10 SDRAM address bus D_ADDR[13] 75 O10 SDRAM address bus VCC_IO3 76 VCC_IO VCC I/O pads D_ADDR[9] 77 O10 SDRAM address bus © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 9 of 66 SAA7893HL Philips Semiconductors Super audio media player Table 2: Pin description…continued Symbol Pin Type[1] Description D_ADDR[12] 78 O10 SDRAM address bus D_ADDR[11] 79 O10 SDRAM address bus D_Wen 80 O10 read or write D_RASn 81 O10 row address select; active LOW D_CASn 82 O10 column address select; active LOW GND_IO4 83 GND_IO GND I/O pads GND_Core2 84 GND_core core ground VCC_Core2 85 VCC_core core supply voltage D_clk 86 O10 clock signal needed for SDRAM D_DQ[5] 87 I/O10 data bus D_UDQM 88 O10 DQ mask enable (upper) D_LDQM 89 O10 DQ mask enable (lower) D_DQ[7] 90 I/O10 data bus D_DQ[8] 91 I/O10 data bus VCC_IO4 92 VCC_IO VCC I/O pads D_DQ[6] 93 I/O10 data bus D_DQ[9] 94 I/O10 data bus D_DQ[10] 95 I/O10 data bus D_DQ[4] 96 I/O10 data bus D_DQ[11] 97 I/O10 data bus D_DQ[3] 98 I/O10 data bus GND_IO5 99 GND_IO GND I/O pads D_DQ[12] 100 I/O10 data bus D_DQ[2] 101 I/O10 data bus D_DQ[13] 102 I/O10 data bus D_DQ[1] 103 I/O10 data bus D_DQ[14] 104 I/O10 data bus D_DQ[0] 105 I/O10 data bus VCC_IO5 106 VCC_IO VCC I/O pads D_DQ[15] 107 I/O10 data bus DSD_PCM_0 108 O10 6-channel data output DSD_PCM_1 109 O10 6-channel data output DSD_PCM_2 110 O10 6-channel data output DSD_PCM_3 111 O10 6-channel data output GND_IO6 112 GND_IO GND I/O pads DSD_PCM_4 113 O10 6-channel data output DSD_PCM_5 114 O10 6-channel data output DSD_PCM_6 115 O10 6-channel clock/control DSD_PCM_7 116 O10 6-channel clock/control DSD_PCM_8 117 O10 2-channel clock/control VCC_IO6 118 VCC_IO VCC I/O pads © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 10 of 66 SAA7893HL Philips Semiconductors Super audio media player Table 2: Pin description…continued Symbol Pin Type[1] Description DSD_PCM_10 119 O10 2-channel data output DSD_PCM_9 120 O10 2-channel clock or control DSD_PCM_11 121 O10 2-channel data output RESETn 122 IN asynchronous reset; active LOW H_A_sel 123 IN address select H_A[6] 124 IN address bus H_A[5] 125 IN address bus H_A[4] 126 IN address bus H_A[3] 127 IN address bus H_A[2] 128 IN address bus [1] Explanation of input and output ports: IN: digital input port; all dedicated inputs are TTL tolerant. IN1: digital input port with internal pull-up resistor. I/O10: bidirectional port with 10 ns slew rate. O10: 3-state (in test mode) output port with 10 ns slew rate. APIO: analog input port. VDDCO: analog VDD port (1.8 V). VSSCO: analog VSS port. GND_IO: ground for I/O pads. VCC_IO: VCC for I/O pads (3.3 V). GND_core: ground for core. VCC_core: VCC for core (1.8 V). 7. Interfaces 7.1 Host interface Different types of host busses are supported: • Separate address/data bus with 16-bit data bus (3 different modes) • Multiplexed address/data bus with 16-bit data bus (2 different modes) • Separate address/data bus with 8-bit data bus (1 mode). The host interface type is set via the dedicated pins H_sel and sys_clk. The SAA7893HL has a dedicated interrupt output pin. 7.2 Front-end interface 7.2.1 Data input interface The SAA7893HL supports three different front-end interfaces which are selectable via the host interface: • I2S-bus interface: the front-end interface is in essence an I2S-bus interface and therefore, it has to conform to the I2S-bus specification. • FEC interface © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 11 of 66 SAA7893HL Philips Semiconductors Super audio media player • Parallel interface (UDE data interface part): a parallel front-end interface with a handshake protocol. 7.2.2 Analog HF input The analog HF input, coming from the optical pickup unit, is also fed to the SAA7893HL to extract the copy protection information PSP. 7.3 Audio interface 7.3.1 Audio input The audio input is a 6-channel PCM-I2S input. 7.3.2 DAC interface The audio output is a 6-channel output and a separate stereo output. Both outputs can be set in DSD and in PCM-I2S mode. 7.4 SDRAM interface The SDRAM interface forms a glueless interface to one 64 Mbit SDRAM device. Supported devices are only PC100 compliant or faster SDRAM devices: • • • • • Organization: 64 Mbit (1M × 16 × 4 banks) Refresh period: 4096 cycles per 64 ms Clock frequency: fclk ≥ 100 MHz Refresh cycle: trcar ≤ 70 ns Command period: trc ≤ 70 ns. 7.5 Clock and reset input Different processing clocks are needed in the SAA7893HL: • sys_clk: system clock for data processing part; frequency can be between 27 and 35 MHz; see Figure 6 and Table 3 • aud_clk: audio clock reference; can be 256/384/512/768 × fs (fs = 44.1 to 48 kHz); see Figure 7 and Table 4 • proc_clk: host processor clock (only used in SAD16_01/02 mode) • B_BCLK: front-end bit/byte clock. It is not required that these clocks are locked. RESETn is an asynchronous reset and should be kept LOW for at least 10 periods of sys_clk. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 12 of 66 SAA7893HL Philips Semiconductors Super audio media player 7.5.1 System clock (sys_clk) definitions Tclk tclk(l) tclk(h) MDB146 tr tf Fig 6. Sys_clk characteristics Table 3: Definitions of sys_clk Symbol Parameter Conditions Min Max Unit Tclk clock cycle time clock frequency from 27 to 35 MHz 28.5 37.4 ns tclk(l) clock time low 11.4 22.4 ns tclk(h) clock time high 11.4 22.4 ns tf fall time - 4 ns tr rise time - 4 ns δclk clock duty cycle 40 60 % 7.5.2 Audio clock (aud_clk) definitions Tclk tclk(l) tclk(h) tr tf MDB146 Fig 7. Aud_clk characteristics Table 4: Definitions of aud_clk Symbol Parameter Conditions Min Max Unit Tclk clock cycle time clock frequency from 256 × 44.1 kHz to 768 × 48 kHz 27 88.6 ns tclk(l) clock time low 10.8 53.1 ns tclk(h) clock time high 10.8 53.1 ns tf fall time - 4 ns tr rise time - 4 ns δclk clock duty cycle 40 60 % 7.6 Test inputs Standard BST functionality is provided. Device data: Version: B0010 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 13 of 66 SAA7893HL Philips Semiconductors Super audio media player Manufacturer ID: B000 0001 0101 Part no: B0011 0101 0110 0100. 8. Host interface 8.1 General description The SAA7893HL is capable to communicate with the hosts (families) via their own busses as given in Table 5. Table 5: Host communications Name Description SAD16_01 Separate Address/Data on 16-bit data bus with wait signal, based on proc_clk SAD16_02 Separate Address/Data on 16-bit data bus with wait signal, based on sys_clk and proc_clk SAD16_03 Separate Address/Data on 16-bit data bus without wait signal MAD16_01 Multiplexed Address/Data on 16-bit data bus mode 01 MAD16_02 Multiplexed Address/Data on 16-bit data bus mode 02 SAD08 Separate Address/Data on 8-bit data bus The type of host is selected via two input pins H_sel[1] and H_sel[0] and the proc_clk signal. In Table 6 the settings for the different host modes are given with the expected input clock(s). Table 6: Clock selection H_sel[1:0] Mode External provided clocks sys_clk proc_clk Internal used system clock 00 SAD16_01 no yes proc_clk/2 10 SAD16_02 yes yes sys_clk 01 SAD16_03 yes logic 1 sys_clk 11 MAD16_01 yes logic 0 sys_clk 11 MAD16_02 yes logic 1 sys_clk 01 SAD08 yes logic 0 sys_clk In all modes the range of the required internal system clock is between 27 and 35 MHz. The pin mapping in the different modes is shown in Table 7. Table 7: Host communication data mapping SAA7893HL name Type SAD16_01; SAD16_02 SAD08 MAD16_01 MAD16_02 SAD16_03 H_A_sel IN CPU_A(7) A(11) ALE ALE LA(7) H_A[3:1] IN CPU_A(4:1) A(3:1) LA(2:0) addr[3:1] LA(3:1) H_A[4] IN CPU_A(4:1) A(4) LA(3) n.c. LA(4) H_A[6:5] IN CPU_A(6:5) A(6:5) AD(21:20) n.c. LA(6:5) H_DQ[7:0] I/O CPU_D(7:0) D(7:0) AD(11:4) data(7:0) LD(7:0) © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 14 of 66 SAA7893HL Philips Semiconductors Super audio media player Table 7: Host communication data mapping…continued SAA7893HL name Type SAD16_01; SAD16_02 SAD08 MAD16_01 MAD16_02 SAD16_03 H_DQ[11:8] I/O CPU_D(11:8) A(10:7) AD(1512) data(11:8) LD(11:8) H_DQ[12] I/O CPU_D(12) n.c. AD(16) data(12) LD(12) H_DQ[13] I/O CPU_D(13) ASn AD(17) data(13) LD(13) H_DQ[14] I/O CPU_D(14) DSn AD(18) data(14) LD(14) H_DQ[15] I/O CPU_D(15) A(0) AD(19) data(15) LD(15) H_IRQn O IRQN IRQn IRQN IRQN IRQN H_procclock IN CPU_procclk logic 0 logic 0 logic 1 logic 1 sys_clk IN n.c.; sysclk PCI-clk Sclk sys_clk sys_clk H_RWn IN CPU_RWn R/Wn RD_ RD_ RD_ H_WAITn O CPU_wait DSACKn ACK HDTACKn n.c. H_CSn IN CPU_CSn CS XIO CSn CSn H_sel[0] IN 0 logic 1 logic 1 logic 1 logic 1 H_sel[1] IN logic 0: mode 1; logic 1: mode 2 logic 0 logic 1 logic 1 logic 0 The internal SAA7893HL address is differently composed in the different modes. 8.2 SAD16_01/02 mode Reading and writing is always done on 16 bits (Hword) base. To save physical pins on the SAA7893HL, the data bus is used to write the 16 MSB address bits, hereafter called ‘the base address’ into the SAA7893HL. Therefore, to access an address inside the SAA7893HL first these 16 MSB bits of the address must be written as a base address for the SAA7893HL indicated by the H_A_sel line. Pin H_A_sel can be mapped to a physical address pin of the host device. indication of an access to the base address H_CSn H_A_sel H_RWn H_A[6:1] H_DQ[15:0] A(22:7) A(6:1) A(6:1) D(15:0) D(15:0) MCE038 write base address Fur_base = A(22:7) write/read on SAA7893HL address locations Fur_A[22:1] = Fur_base&A(6:1) Fig 8. Write to or read from the SAA7893HL. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 15 of 66 SAA7893HL Philips Semiconductors Super audio media player In Figure 8 the principle of first writing the base address indicated by H_A_sel is here visualized. Pin H_A_sel is mapped on address pin H_A[7] of the host. The timing is, of course, not to scale. When the base address is written, multiple accesses can be done whereby the different LSB addresses are mapped on pins H_A[6:1]. In this way a burst of 64 Hwords can be read or written to the same address. The 16 bits base address can be read when H_A_sel is logic 1 and the signal H_RWn indicates a read operation. Remark: The H_waitn signal is synchronized to H_procclock (pin 18). So it depends on the host used which H_procclock is provided. When the host can accept an asynchronous H_waitn signal, the clock signal connected to the sys_clk input (pin 21) can also be used as the clock signal to the H_procclock input. 8.2.1 Write mode: minimum cycle ttot H_CSn th tsu H_RWn H_DQ[15:0] H_A[6:1] H_A_sel H_WAITn MBL622 Fig 9. Timing diagram of writing registers with no wait cycles. Table 8: Timing numbers of writing registers with no wait cycles Symbol Parameter Min Typ Max Unit ttot total CSn time 14 - - sys_clk tsu set-up time from CS to host control/address lines - - 30 ns th hold time from CS to host control/address lines 0 - - ns © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 16 of 66 SAA7893HL Philips Semiconductors Super audio media player 8.2.2 Read mode: minimum cycle ttot H_CSn th tsu H_RWn H_A[6:1] H_A_sel ttri th(D) Z H_DQ[15:0] undefined Z data tset H_WAITn MBL633 Fig 10. Timing diagram of reading registers with no wait cycles. Table 9: Timing numbers of reading registers with no wait cycles Symbol Parameter Conditions Min Typ Max Unit ttot total CSn time 14 - - sys_clk tsu set-up time from CS to host control/address lines 0 - 30 ns th hold time from CS to host control/address lines 0 - - ns ttri time that data bus is set from 3-state to output 1 - 3 sys_clk tset time that data is valid before CS is set to logic 1 60 - - ns th(D) hold time from CS to data bus 0 - - ns 8.2.3 maximum time is not needed; can be forever Write mode: cycles extended using wait protocol ttot H_CSn tsu th H_RWn H_DQ[15:0] H_A[6:1] H_A_sel twt twt(st) twt(en) H_WAITn MBL635 Fig 11. Timing diagram of writing registers with wait cycles. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 17 of 66 SAA7893HL Philips Semiconductors Super audio media player Table 10: Timing numbers of writing registers with wait cycles Symbol Parameter ttot Min Typ Max Unit total CSn time 14 - - sys_clk tsu set-up time from CS to host control/address lines 0 - 30 ns th hold time from CS to host control/address lines 0 - - ns twt active time of H_WAIT when Pi registers are accessed speed is dependent on load on PI-bus 3 8 11 sys_clk active time of H_WAIT when external SDRAM is speed is dependent on load accessed on PI-bus 3 11 17 sys_clk twt(st) time from CS until wait becomes active 5[1] - 6[1] sys_clk twt(en) time H_WAIT inactive until CS becomes inactive 10 - - ns [1] Conditions When the SAA7893HL SAD16 interface is programmed to generate always a H_WAIT signal, the minimum time will be 2 sys_clk cycles and the maximum time will be 3 sys_clk cycles. 8.2.4 Read mode: cycles extended using wait protocol ttot H_CSn th tsu H_RWn H_A[6:1] H_A_sel t tri t set Z H_DQ[15:0] undefined t wt t wt(st) t h(D) Z data t wt(en) H_WAITn MBL636 Fig 12. Timing diagram of reading registers via PI-bus. Table 11: Timing numbers of reading registers via PI-bus Symbol Parameter Conditions Min Typ Max Unit - - sys_clk - 30 ns ttot total CSn time 14[1] tsu set-up time from CS to host control/address lines 0 th hold time from CS to host control/address lines twt active time of H_WAIT when Pi registers are accessed twt(st) 0 - - ns speed is dependent on load on PI-bus 3 8 11 sys_clk active time of H_WAIT when external SDRAM is speed is dependent on load accessed on PI-bus 3 11 17 sys_clk time from CS until wait becomes active 5[2] - 6[2] sys_clk © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 18 of 66 SAA7893HL Philips Semiconductors Super audio media player Table 11: Timing numbers of reading registers via PI-bus…continued Symbol Parameter Min Typ Max Unit twt(en) time from H_WAIT negative slope to data set-up - - 0 ns ttri time that data bus is set from 3-state to output 1 - 3 sys_clk tset time that data is valid before CS is set to logic 1 30 - - ns th(D) hold time from CS to H_data bus 0 - - ns [1] [2] Conditions When the SAA7893HL SAD16 interface is programmed to generate always a H_WAIT signal of at least 7 sys_clk cycles, then it is no longer required that the minimum time of ttot is 14 sys_clk cycles. The data at the H_DQ output is always available at the negative edge of the H_WAIT signal. The host can deactivate the H_CS signal after the negative edge of the H_WAIT signal and when it has read the data at the H_DQ lines. When a H_WAIT signal is always generated then the timing diagrams in Figure 9 and Figure 10 are no longer applicable. When the SAA7893HL SAD16 interface is programmed to generate always a H_WAIT signal, the minimum time will be 2 sys_clk cycles and the maximum time will be 3 sys_clk cycles. 8.2.5 Host interface connection SAD16_01 mode SAA7893HL 26 CPU_RW 24 CE2n 27 CPU_WAIT H_RWn H_CSn H_WAIT 10 kΩ 123 CPU_ADDR(7) CPU_ADDR(6:1) 124, 125, 126, 127, 128, 1 H_A_sel H_A[6:1] 2, 3, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 22, 23, 25 H_DQ[15:0] CPU_ADDR(15:0) 18 CPU_PROCCLK 28 IRQ_x GND_IO GND_IO GND_IO 21 62 63 H_procclk H_IRQn sys_clk H_sel[0] H_sel[1] MCE039 Fig 13. Host interface connection. 8.3 SAD16_03 mode To save physical pins on the SAA7893HL, the data bus is used to write the 16 MSB address bits, hereafter called ‘the base address’, into the SAA7893HL. Therefore, to access an address inside the SAA7893HL first this 16 MSB bits of the address must be written as a base address for the SAA7893HL indicated by the H_A_sel line. Pin H_A_sel can be mapped to a physical address pin of the host device. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 19 of 66 SAA7893HL Philips Semiconductors Super audio media player indication of an access to the base address H_CSn H_A_sel H_RWn H_A[6:1] H_DQ[15:0] A(22:7) A(6:1) A(6:1) D(15:0) D(15:0) MCE038 write base address Fur_base = A(22:7) write/read on SAA7893HL address locations Fur_A[22:1] = Fur_base&A(6:1) Fig 14. Write to or read from the SAA7893HL. In Figure 14 the principle of first writing the base address indicated by H_A_sel is here visualized. Pin H_A_sel is mapped on address pin H_A[7] of the host. The timing is of course not to scale. When the base address is written, multiple accesses can be done whereby the different LSB addresses are mapped on pins H_A[6:1]. In this way a burst of 64 Hwords can be read or written to the same address. The 16 bits base address can be read when H_A_sel is logic 1 and the signal H_RWn indicates a read operation. In SAD16_03 mode there is in principle no handshake available. Therefore, to read data a double read must be done. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 20 of 66 SAA7893HL Philips Semiconductors Super audio media player 8.3.1 Read mode indication of an access to the base address H_CSn twt H_A_sel H_RWn H_A[6:1] H_DQ[15:0] A(22:7) A(6:1) undefined undefined D(15:0) MCE040 write base address Fur_base = A(22:7) data is read indicated by H_A_sel read ’indication’ on SAA7893HL address locations Fur_A[22:1] = Fur_base&A(6:1) Fig 15. Read from the SAA7893HL. First the 16 bits of the base address are set indicated by the H_A_sel line. Then a read access is started. In SAD16_03 mode there is no handshake line on which the SAA7893HL can indicate that internal read operation is ready. Therefore, to be sure that the requested data is read correctly, an extra read is needed indicated by the H_A_sel line. In this read the data is presented as read by the previous read access. The maximum time that the host must wait before this extra read is started is approximately 30 sys_clk cycles. If in this time a new access is activated this access can be lost. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 21 of 66 SAA7893HL Philips Semiconductors Super audio media player 8.3.2 Write mode indication of an access to the base address H_CSn twt H_A_sel H_RWn H_A[6:1] H_DQ[15:0] undefined A(6:1) A(22:7) D(15:0) write base address Fur_base = A(22:7) write on SAA7893HL address locations Fur_A[22:1] = Fur_base&A(6:1) MCE041 Fig 16. Write to the SAA7893HL. When a write operation is issued the same wait time twt must be taken into account before a next access may start, but here no double write has to be done. 8.3.3 Writing of base address ttot twt H_CSn tsu(rw) th H_RWn H_A_sel tsu(ad) H_A[6:1] H_DQ[15:0] undefined address[22:7] MCE042 Fig 17. Timing diagram of writing the base address. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 22 of 66 SAA7893HL Philips Semiconductors Super audio media player Table 12: Timing numbers of base address writing Symbol Parameter ttot total LOW time of H_CSn twt wait time before next cycle may start tsu(rw) set-up time of H_RWn tsu(ad) set-up time for address 8.3.4 Conditions Min Max Unit 270 - ns if in this time a new cycle is started, 100 the new access cycle could be neglected - ns - 0 ns - 10 ns Min Max Unit Writing data to the SAA7893HL ttot twt H_CSn tsu(rw) th H_RWn H_A_sel tsu(ad) H_A[6:1] H_DQ[15:0] address[6:1] data[15:0] MCE043 Fig 18. Writing data to the SAA7893HL. Table 13: Timing numbers of writing data Symbol Parameter Conditions ttot total LOW time of H_CSn twt wait time before next cycle may start 270 - ns if in this time a new cycle is started, 700 the new access cycle could be neglected - ns tsu(rw) set-up time of H_RWn 0 ns tsu(ad) set-up time for address - 10 ns th hold time of H_RWn/address/data with respect to H_CSn 0 - ns - © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 23 of 66 SAA7893HL Philips Semiconductors Super audio media player 8.3.5 Reading data from the SAA7893HL ttot twt ttot H_CSn tsu(rw) th H_RWn H_A_sel tsu(ad) H_a(6:1) H_address(6:1) don’t care td(tri) H_data Z th(D) Z undefined data MCE044 Fig 19. Reading data from the SAA7893HL. Table 14: Timing numbers of reading data Symbol Parameter ttot total LOW time of H_CSn twt wait time before next cycle may start tsu(rw) set-up time of H_RWn tsu(ad) set-up time for address ttri time that data bus is enabled Conditions Min Max Unit 270 - ns if in this time a new cycle is started, 700 the new access cycle could be neglected - ns - 0 ns - 10 ns 1 3 sys_clk time dependent on system clock © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 24 of 66 SAA7893HL Philips Semiconductors Super audio media player 8.3.6 Host interface connection SAD16_03 mode SAA7893HL 26 RD_ 24 CSn n.c. 123 LA(7) LA(6:1) 27 124, 125, 126, 127, 128, 1 H_RWn H_CSn H_WAIT H_A_sel H_A[6:1] 2, 3, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 22, 23, 25 H_DQ[15:0] LD(15:0) 28 IRQ_x VCC_IO 18 21 VCC_IO sys_clk or video clock GND_IO 62 63 H_IRQn H_procclk sys_clk H_sel[0] H_sel[1] MCE045 Fig 20. Host interface connection. 8.4 MAD16_01 mode Data communication is here always done on a 16-bit data bus. The address is mapped on 6 separate address pins and 16 address/data pins of the SAA7893HL. Therefore, in this mode the complete address is transferred directly in each access cycle. In Table 7 the internal SAA7893HL address is mapped as follows to the SAA7893HL pins: Fur_H_A[22:1] = H_A[6:5] & H_DQ[15:0] & H_A[4:1]. This address mapping is the default setting, the following address is also possible: Fur_H_A[22:1] = H_A[6:1] & H_DQ[15:0]. The system clock provided in the MAD16_01 mode must be synchronized to the host interface timing. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 25 of 66 SAA7893HL Philips Semiconductors Super audio media player 8.4.1 Write mode: minimum cycle sys_clk ttot H_CSn trd H_A_sel H_RWn H_WAIT tsu th H_A[6:1] addr H_DQ[15:0] addr data MBL637 tdw Fig 21. Timing diagram writing to the SAA7893HL. Table 15: Timing numbers of writing registers Symbol Parameter Min Max Unit ttot total H_CSn time 8 - sys_clk tsu set-up time H_A_sel 5 - ns th hold time of H_A_sel with respect to sys_clk 5 - ns trd time H_RWn can change from H_CSn signal - 1 sys_clk tsu(D) data set-up time after H_CSn 0 1 sys_clk © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 26 of 66 SAA7893HL Philips Semiconductors Super audio media player 8.4.2 Read mode: minimum cycle sys_clk H_CSn trd H_A_sel H_RWn H_WAIT tsu th H_A[6:1] addr H_DQ[15:0] addr data MBL638 tdr Fig 22. Timing diagram reading from the SAA7893HL. Table 16: Timing numbers of reading registers Symbol Parameter tsu Conditions Min Max Unit set-up time H_A_sel 5 - ns th hold time of H_A_sel with respect to sys_clk 5 - ns trd time H_RWn can change from H_CSn signal - 1 sys_clk tdr data set-up time after CSn time dependent on system clock used 6 8 sys_clk tdc data hold time before CSn not important data is sample after detecting H_CSn = logic 0 - - ns © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 27 of 66 SAA7893HL Philips Semiconductors Super audio media player 8.4.3 Write mode: cycles extended using wait protocol sys_clk ttot H_CSn trd H_A_sel H_RWn H_WAIT tsu th H_A[6:1] addr H_DQ[15:0] addr data tdw1 MBL639 twt tdw2 Fig 23. Timing diagram writing to the SAA7893HL (with wait cycles). Table 17: Timing numbers of writing registers (with wait cycles) Symbol Parameter ttot Conditions Min Max Unit total H_CSn time 8 - sys_clk tsu set-up time H_A_sel 5 - ns th hold time of H_A_sel with respect to sys_clk 5 - ns trd time H_RWn can change from H_CSn signal - 1 sys_clk tdw1 data set-up time after H_CSn time dependent on system clock used 1 3 sys_clk tdw2 time H_WAIT is activated after H_CSn is activated dependent on SAA7893HL settings 2 6 sys_clk twt total time wait can be active 2 24 sys_clk © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 28 of 66 SAA7893HL Philips Semiconductors Super audio media player 8.4.4 Read mode: cycles extended using wait protocol sys_clk H_CSn trd H_A_sel H_RWn H_WAIT tsu th H_A[6:1] addr H_DQ[15:0] addr data tdw twt MBL640 tac Fig 24. Timing diagram reading from the SAA7893HL (with wait cycles). Table 18: Timing numbers of reading registers (with wait cycles) Symbol Parameter ttot total H_CSn time 8 - sys_clk tsu set-up time H_A_sel 5 - ns th hold time of H_A_sel with respect to sys_clk 5 - ns trd time H_RWn can change from H_CSn signal - 1 sys_clk tdw time H_WAIT is activated after H_CSn is activated dependent on SAA7893HL settings 2 5 sys_clk twt total time wait can be active 2 24 sys_clk tac data active until H_CSn is deactivated 1 - sys_clk Min Unit © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Max Rev. 02 — 26 February 2003 29 of 66 SAA7893HL Philips Semiconductors Super audio media player 8.4.5 Host interface connection MAD16_01 mode SAA7893HL 26 XIO_x 24 XIO_x H_RWn H_CSn VCC_IO 10 kΩ 27 X_ACK 123 ALE H_WAIT H_A_sel 124, 125, 126, 127, 128, 1 H_A[6:1] AD(21:16) 2, 3, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 22, 23, 25 H_DQ[15:0] AD(15:0) 21 SCLK 28 IRQ_x GND_IO VCC_IO VCC_IO 18 62 63 sys_clk H_IRQn H_procclk H_sel[0] H_sel[1] MCE046 Fig 25. Host interface connection. 8.5 MAD16_02 mode In the MAD16_02 mode there is a 16-bit combined address/data bus and a dedicated 3-bit address bus. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 30 of 66 SAA7893HL Philips Semiconductors Super audio media player H_CSn H_A_sel H_RWn ha[22:20] H_A[3:1] ha[3:1] H_WAITn H_DQ[15:0] ha[19:4] Z undefined data[15:0] Z MCE047 Fig 26. Principle read. The multiplexing of the address/data pins is done as a regular host communication, meaning that during a read or write the host must automatically generate the timing according to Figure 26. It is not needed that the provided system clock is a synchronous clock with respect to the H_A_sel line. 8.5.1 Write mode ttot H_CSn tsu th(cs) H_A_sel th(ad) H_RWn H_A[3:1] H_DQ[15:0] ha[22:20] ha[3:1] ha[19:4] data[15:0] tdw1 twt H_WAITn MCE048 Fig 27. Timing diagram writing to the SAA7893HL. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 31 of 66 SAA7893HL Philips Semiconductors Super audio media player 8.5.2 Table 19: Timing numbers of MAD16_02 write Symbol Parameter Min Max Unit ttot total LOW time of H_CSn 300 + twt - ns th hold time of address/data with respect to H_A_sel 10 - ns tdw1 wait time until H_WAIT is activated 2 5 sys_clk twt time of H_WAIT signal 2 24 sys_clk tsu set-up time of H_RWn/address with respect to H_CSn - 10 ns Read mode ttot H_CSn H_A_sel th H_RWn H_A[3:1] ha[22:20] ha[3:1] twt tsu H_WAITn ttri H_DQ[15:0] ha[19:4] tdw1 tset(D) Z undefined data[15:0] MCE049 Fig 28. Timing diagram reading from the SAA7893HL. Table 20: Timing numbers of MAD16_02 read Symbol Parameter Min Typ Max Unit ttot total H_CSn time 8 + twt - - ns tsu set-up time of address/data/H_RWn with respect to H_CSn - 0 ns th hold time of address with respect to H_A_sel falling edge - - ns tdw1 time H_WAIT is activated after H_CSn is activated - 4 sys_clk © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data 10 Rev. 02 — 26 February 2003 32 of 66 SAA7893HL Philips Semiconductors Super audio media player 8.5.3 Table 20: Timing numbers of MAD16_02 read…continued Symbol Parameter Min Typ Max Unit ttri time data bus becomes active after H_CSn - 2 - sys_clk tset(D) time data available with respect to H_WAIT signal 15 - - ns twt time H_WAIT can be active 2 - 24 sys_clk Host interface connection MAD16_02 mode SAA7893HL 26 RD_ 24 CSn 27 HDTACKn 123 ALE H_RWn H_CSn H_WAIT H_A_sel 124, 125, 126 H_A[6:4] n.c. 127, 128, 1 H_A[3:1] ADDR(3:1) 2, 3, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 22, 23, 25 H_DQ[15:0] DATA(15:0) 28 IRQ_x VCC_IO 18 21 sys_clk or video clock VCC_IO VCC_IO 62 63 H_IRQn H_procclk sys_clk H_sel[0] H_sel[1] MCE050 Fig 29. Host interface connection. 8.6 SAD08 mode Here the reading and writing is always done on 8-bit. From pin mapping it can be seen that the byte indication is done via bit A(0) which is mapped on H_DQ(15) of the SAA7893HL. The internal SAA7893HL communication stays on 16-bit. Therefore, the host interface block ‘translates’ the 8 bits external communication to the 16 bits internal. To save physical pins on the SAA7893HL device, the data bus and 4 address bits are used to write the 12 MSB address bits, hereafter called ‘the base address’, into the SAA7893HL device. Therefore, to access an address inside the SAA7893HL first this 12 MSB bits of the address must be written as a base address for the SAA7893HL indicated by the H_A_sel line. Pin H_A_sel can be mapped to a physical address pin of the host. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 33 of 66 SAA7893HL Philips Semiconductors Super audio media player 8.6.1 Writing base address indication of an access to the base address H_CSn H_RWn H_A_sel H_A[6:1] A(6:1) A(6:1) H_DQ[15] LSB write/read MSB write/read H_DQ[7:0] A(22:15) D(7:0) D(15:8) H_DQ[11:8] A(14:11) A(10:7) A(10:7) MCE051 write base address Fur_base = A(22:11) write/read on SAA7893HL address locations Fur_A[22:1] = Fur_base&A(10:1) Fig 30. Base address writing. In Figure 30 the writing of the base address and a Hword to the host is given in SAD08 mode. First, the 12 bits base address is written indicated by H_A_sel line. The SAA7893HL samples the base address on H_DQ(7:0) and H_DQ(11:8). After that the normal write operation is performed as explained in Section 8.6.2. 8.6.2 Writing to the SAA7893HL A write to address N of 16 bits to the SAA7893HL will be translated to two byte accesses. First the LSB byte is written to address N [so A(0) = logic 0] and stored in cache. Then the MSB byte is written to address N+1 [so A(0) = logic 1]. When the SAA7893HL receives a write command at an odd address [A(0) = logic 1] always 16 bits are internally written whereby the Hword is composed of LSB byte in cache and the MSB byte received at present write command. The SAA7893HL can be set to big and little endian, whereby the described situation is the power-on state. Byte read or write operations are not supported in SAD08 mode. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 34 of 66 SAA7893HL Philips Semiconductors Super audio media player sys_clk th tsu H_CSn H_DQ[11:8] H_A[7:0] address th H_RWn td(as) H_DQ[13] data H_DQ[7:0] td(ds) H_DQ[14] td H_WAIT MBL641 M clock cycles Fig 31. Timing diagram SAD08 write to SAA7893HL. Table 21: Timing numbers of SAD08 write Symbol Parameter tsu Min Max Unit set-up time from H_CSn, H_RWn and H_DQ(13) to sys_clk 5 - ns th hold time from clk to H_CSn, H_RWn and H_DQ(13) 5 - ns td(as) delay from H_CSn to negative slope of H_DQ(13) - 1 sys_clk td(ds) delay from H_CSn to negative slope of H_DQ(14) and data - 2 sys_clk M number of clock cycles 4 15 sys_clk td delay from clk to DSACKn 2 12 ns 8.6.3 Conditions dependent on access type and traffic on PI-bus Reading from the SAA7893HL When the LSB is read [A(0) = logic 0], the host interface will read an Hword on the address location A(22:1). The LSB byte is set on the output bus and the read MSB byte is stored internally. When a read action is now started whereby the MSB byte is selected to read [A(0) = logic 1] the stored byte is available on the output independent on the other address bits A(22:1). © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 35 of 66 SAA7893HL Philips Semiconductors Super audio media player sys_clk th tsu H_CSn H_DQ[11:8] H_A[7:0] address th H_RWn H_DQ[13] data H_DQ[7:0] tdat H_DQ[14] td H_WAIT MBL623 N clock cycles Fig 32. Timing diagram SAD08 read from the SAA7893HL. Table 22: Timing numbers of SAD08 read Symbol Parameter tsu set-up time from H_CSn, H_RWn and H_DQ[13] to sys_clk 5 ns th hold time from clk to H_CSn, H_RWn and H_DQ[13] 5 ns N number of clock cycles td tdat Conditions Min dependent on access type and traffic on PI-bus. Max Unit 5 20 sys_clk delay from clk to H_WAIT 2 12 ns data available before H_WAIT is asserted - 0 ns © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 36 of 66 SAA7893HL Philips Semiconductors Super audio media player 8.6.4 Host interface connection SAD08 mode SAA7893HL 26 CPU_RW 24 CE2n H_RWn H_CSn VCC_IO 10 kΩ 27 CPU_WAIT 123 XIO_ADDR(11) XIO_ADDR(10:7) 7, 8, 9, 11 H_WAIT H_A_sel H_DQ[11:8] 124, 125, 126, 127, 128, 1 XIO_ADDR(6:1) H_A[6:1] 2 XIO_ADDR(0) 3 DS 5 AS H_DQ[15] H_DQ[14] H_DQ[13] 12, 13, 14, 15, 16, 22, 23, 25 H_DQ[7:0] XIO_DATA(7:0) 21 PCI_CLK 28 IRQ_x GND_IO VCC_IO GND_IO 18 62 63 sys_clk H_IRQn H_procclk H_sel[0] H_sel[1] MCE052 Fig 33. Host interface connection. 8.7 Interrupt The interrupt output is a LOW level interrupt which must be connected to the interrupt input of the DVD host. 9. Front-end interface First the SACD sector structure is explained and how to connect the SAA7893HL in the different modes. For these different modes the interface timing figures will be given. The supported sector format interface is sketched in Figure 34. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 37 of 66 SAA7893HL Philips Semiconductors Super audio media player Byte 0 to 11 Byte 12 to 2059 Byte 2060 to 2063 HEADER MAIN DATA EDC 12 2048 stored in VBR sector format 4 Byte 1 to 3 Byte 4 to 5 Byte 6 to 11 INFORMATION Byte 0 NUMBER IED CPSI ID[31...24] ID[23...0] MBL616 Fig 34. SACD sector format. The SAA7893HL supports a data input bit rate of maximal 40 Mbits/s. The connections to the SAA7893HL in the different front-end modes are given in Table 23. Table 23: Connection of different front-end interfaces SAA7893HL name Type I2S_mode FEC B_FLAG IN I2S_err n.c.[1] SERR B_SYNC IN I2S_sync OUT_SYNC SYNC B_WCLK IN I2S_wclk OUT_DVALID SENB B_BCLK IN I2S_bclk OUT_CLK SDCLK B_DATA IN I2S_data OUT_DATA0 MPEG(0) Be_dat(7:1) IN n.c.[1] n.c.[1] MPEG(7:1) UDE_req IN n.c.[1] n.c.[1] UDE_req Data_req O n.c. n.c. REQ [1] Parallel mode The n.c. input pins must be connected to VCC or GND. 9.1 I2S-bus interface 9.1.1 Input timing In Figure 35 the functional input timing is given. Note that B_SYNC, B_FLAG are sampled simultaneously with D11. Since B_FLAG indicates the error in a byte, it is also sampled simultaneously with D3. The sampling moment during D11 for the high byte (D15 to D8), sampling moment D3 for the low byte (D7 to D0). © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 38 of 66 SAA7893HL Philips Semiconductors Super audio media player I2S-bus half word B_DATA D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 B_BCLK B_WCLK B_SYNC B_FLAG MBL617 Fig 35. Front-end input timing. When the B_SYNC signal is set to logic 1 between bit position D15 and D11 the SAA7893HL accepts this word as the start of a sector. The SAA7893HL does not perform EDC checking on the main data, but is dependent on the B_FLAG. A sector is set to erroneous if B_FLAG is set to logic 1. 9.1.2 Interface timing B_BCLK B_SYNC B_FLAG B_WCLK B_DATA MBL624 tsu th Fig 36. Timing in I2S-bus interface. Table 24: Timing in I2S-bus interface Symbol Parameter Min Unit tsu set-up time to rising edge of the clock 5 ns th hold time after rising edge of the clock 5 ns © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 39 of 66 SAA7893HL Philips Semiconductors Super audio media player 9.1.3 Interface connection I2S-BUS front-end IC SAA7893HL I2S_clk I2S_wclk I2S_sync I2S_err I2S_dat 46 44 43 42 45 49-55 open 47 48 B_BCLK B_WCLK B_SYNC B_FLAG B_DATA Be_dat(7:1) UDE_req Data_req MCE053 Not used input pins must be connected to VCC or GND. Fig 37. Front-end interface connection. 9.2 UDE data interface In the SA-MP the synchronous parallel mode is supported. There are three types of parallel data transfer modes supported: • Synchronous mode (see Section 9.2.1) • Asynchronous mode: – Handshake to enable data transfer – Handshake for every byte transfer. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 40 of 66 SAA7893HL Philips Semiconductors Super audio media player 9.2.1 Parallel mode tclk(h) tclk(l) B_BCLK th th Data_req tsu B_WCLK B_FLAG tsu Sb_6 Sb_5 Sb_4 Empty Sb_3 Sb_2 Sb_1 Sb_0 Sa_2063 Sa_2062 Empty Empty Empty Sa_2061 Sa_2060 Be_dat(7:0) Sa_2059 B_SYNC MCE054 Fig 38. Timing diagram for UDE interface with level sync mode. Polarity of Data_req, B_WCLK, B_FLAG and B_SYNC is programmable. The UDE transmitter must react on the Data_req signal within 5 B_BCLK cycles. The SAA7893HL samples the data on the positive slope of B_BCLK when the B_WCLK signal is active. When B_FLAG signal is active for one byte of the sector, the total sector will be treated as erroneous. The maximum clock frequency of B_BCLK is 20 MHz. The Data_req line generated by the SAA7893HL is synchronized to the internal sys_clk signal. Therefore, the Data_req line is asynchronous with respect to BCLK line. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 41 of 66 SAA7893HL Philips Semiconductors Super audio media player B_BCLK th th Data_req tsu B_WCLK B_FLAG tsu Sb_6 Sb_5 Sb_4 Empty Sb_3 Sb_2 Sb_1 Sb_0 Sa_2063 Sa_2062 Empty Empty Empty Sa_2061 Sa_2060 Be_dat(7:0) Sa_2059 B_SYNC MCE055 Fig 39. Timing diagram for UDE interface with sync edged triggered mode. Polarity of Data_req, B_WCLK, B_FLAG and B_SYNC is programmable. Table 25: Timing in synchronous parallel mode Symbol Parameter Conditions Min Max Unit tclk(h)(l) HIGH/LOW time of the B_BCLK signal maximum clock frequency of B_BCLK is 20 MHz 20 - ns tsu set-up time to rising edge of the clock data/control must be stable during tsu before positive slope of B_BCLK 10 - ns th hold time after rising edge of the clock 5 data/control must be kept at least during th after positive slope of B_BCLK - ns to output delay from the clock 15 ns 2 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 42 of 66 SAA7893HL Philips Semiconductors Super audio media player 9.2.2 Interface connection UDE front-end IC SAA7893HL 46 sdclk 44 senb 43 sync 42 serr 45 data 49-55 48 req 47 B_BCLK B_WCLK B_SYNC B_FLAG B_DATA Be_dat(7:1) Data_req UDE_req DVD back-end IC sdclk with UDE req senb sync serr data MCE056 Fig 40. Front-end interface connection. 9.3 FEC interface This is a serial interface for communication to a special front-end IC. bclk/ ser_bclk be_dat(0)/ ser_data bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 bit 14 bit 15 bit 16 wclk/ ser_valid sync/ ser_sync MBL619 Fig 41. FEC interface. The timing diagram of the FEC interface is given in Figure 41. The first bit of a sector is indicated by the sync signal; this is the MSB bit of the first byte of the header. The sector error indication is in FEC mode indicated by two extra bytes at the end of the sector. This means that the sector length is increased to 2066 bytes. The indication of errors is as follows: FF = error; 00 = no error. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 43 of 66 SAA7893HL Philips Semiconductors Super audio media player 9.3.1 Timing B_BCLK B_SYNC B_FLAG B_WCLK B_DATA MBL624 tsu th Fig 42. Timing in FEC interface. 9.3.2 Table 26: Timing in FEC interface Symbol Parameter tsu set-up time to rising edge of the clock 10 ns th hold time after rising edge of the clock 5 ns Min Unit Interface connection FEC front-end IC SAA7893HL 46 ser_clk 44 ser_valid 43 ser_sync GND_IO 42 45 ser_dat 49-55 open 47 48 B_BCLK B_WCLK B_SYNC B_FLAG B_DATA Be_dat(7:1) UDE_req Data_req MCE057 Fig 43. Front-end interface connection. 10. HF input 10.1 General On every SACD disc a PSP signal must be recorded. The player is only allowed to play a disc if a valid PSP signal is detected. This PSP key is recorded via a special mechanism in the EFM signal on disc. The EFM+ signal must be fed to the SAA7893HL as shown in Figure 44. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 44 of 66 SAA7893HL Philips Semiconductors Super audio media player +1.8 V VDDA 10 nF EFM+ Agcinp 100 nF Adcrefl 12 kΩ biasin VSSA MBL620 Fig 44. Connection of EFM+ input. The detection of the PSP key is dependent of the polarity of the EFM+ signal. The SA-MP settings are that a pit on the disc must have a higher output voltage than the land. The EFM+ input signal has no timing requirements with respect to the digital input of the front-end interface of the SAA7893HL. The SAA7893HL supports also an inversion of the EFM+ signal. 10.2 HF input specification The AGC circuit must be able to handle the following signal characteristics of the HF input signal. Table 27: HF signal characteristics HF Value Remark Input range 0.2 to 0.8 V (p-p) HF input voltage Bandwidth 9 MHz front-end running on maximum speed needed for SACD The HF is AC-coupled via a capacitor of 10 nF to pin Agcinp. The internal resistance of pin Agcinp is 1 MΩ. Table 28: Signal connections Pin name Description Agcinp HF output from pickup unit connected via a 10 nF couple capacitor biasin bias current; connect a 12 kΩ resistor to VSS (ground) Adcrefl reference voltage for internal resistor trap; decouple with 100 nF to VSS (ground) VSSA analog ground VDDA 1.8 V analog power supply © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 45 of 66 SAA7893HL Philips Semiconductors Super audio media player 10.3 HF-input application diagram +1.8 V ≥4.7 µF 100 nF 32 EFM+ (0.2-0.8 V) 10 nF 100 nF 12 kΩ 35 VDDA Agcinp SAA7893HL 36 34 Adcrefl biasin VSSA 33 MCE058 Fig 45. EFM input interface connection. 11. Audio interfaces 11.1 Audio input interface The PCM-I2S audio input signals can be either directly couple, without any processing to the DSD_PCM output lines, or further processed inside the SAA7893HL. When directly coupled, only a combinatorial delay must be taken into account; no dependency on any clock signal (see Section 11.1.1). The input signal characteristics, when audio processing must be performed, are given in Section 11.1.2. 11.1.1 Audio input directly coupled When no processing is done inside the SAA7893HL with respect to the I2S-PCM input stream, this input stream is sent via a multiplexer to the I2S-bus output paths. So no clocking is done on this signal, meaning that also no locked audio clock needs to be present. input pin td(as) output pin MBL627 Fig 46. Delay from input to output pin. Table 29: Timing numbers in PCM audio Symbol Parameter Min Typ Max Unit td(as) asynchronous delay 8 13 18 ns © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 46 of 66 SAA7893HL Philips Semiconductors Super audio media player 11.1.2 Audio input ‘with processing’ right channel right surround LFE left channel left surround center PCM_wclk_in 16/24/32/48 clock cycles tsu th PCM_dclk_in th tsu PCM_LeRi_in PCM_LsRs_in PCM_CeLf_in MSB 1 2 3 22 LSB MSB 1 2 3 MBL628 24 data bits Fig 47. Audio I2S-bus input timing. Table 30: Timing numbers in PCM audio Symbol Parameter Conditions Min PCM-I2S Unit tsu set-up time to rising edge to the pcm_dclk_in signal in mode, the data is always outputted on 8 the negative edge of the bit clock; so here data is sampled on positive edge of the clock ns th hold time after rising edge of the pcm_dclk_in signal in PCM-I2S mode, the data is always outputted on 5 the negative edge of the bit clock; so here data is sampled on positive edge of the clock ns 11.1.3 Interface connection audio clock 256/384/512/768 x fs DVD back-end IC aud_clk_in I2S_clk I2S_wclk I2S_leri I2S_Celfe I2S_Isrs SAA7893HL 29 30 31 40 39 41 aud_clk PCM_dclk_in PCM_wclk_in PCM_LeRi_in PCM_CeLf_in PCM_LsRs_in MCE059 Fig 48. Audio I2S-PCM input interface connection. 11.2 Audio output interface The 6-channel outputs can be either DSD format or PCM-I2S format. The connections are given in Table 31. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 47 of 66 SAA7893HL Philips Semiconductors Super audio media player The SAA7893HL has 12 output lines: 8 lines are allocated for connection to a 6-channel DAC and 4 are for connection to a 2-channel DAC or a 75 Hz reference signal. The DSD data on the MCH output lines are outputted 6412 clocks after the positive edge of the 75 Hz signal, if no additional post-processing is done. SA-MP DSD_PCM_0 DSD_PCM_1 DSD_PCM_2 DSD_PCM_3 to 6-channel DAC DSD_PCM_4 DSD_PCM_5 DSD_PCM_6 DSD_PCM_7 DSD_PCM_8 DSD_PCM_9 to 2-channel DAC DSD_PCM_10 DSD_PCM_11 MBL621 Fig 49. SA-MP output line allocation. The SA-MP delivers extra flexibility when connecting to different DAC types, which can be: DSD only, PCM only or multi standard (DSD + PCM)]. In Table 31 the signal allocation is given for the 6-channel output in DSD and in PCM-I2S mode. Table 31: Connection to a 6-channel DAC Output line Pin Mode = DSD number Mode = PCM DSD_PCM_0 108 left channel Lf + Rf; Ls + Rs; C + LFE; 0 or 1; PCM data/word clock DSD_PCM_1 109 right channel Lf + Rf; Ls + Rs; C + LFE; 0 or 1; PCM data/word clock DSD_PCM_2 110 center channel Lf + Rf; Ls + Rs; C + LFE; 0 or 1; PCM data/word clock DSD_PCM_3 111 LFE channel Lf + Rf; Ls + Rs; C + LFE; 0 or 1; PCM data/word clock DSD_PCM_4 113 left surround Lf + Rf; Ls + Rs; C + LFE; 0 or 1; PCM data/word clock DSD_PCM_5 114 right surround Lf + Rf; Ls + Rs; C + LFE; 0 or 1; PCM data/word clock DSD_PCM_6 115 DSD clock or 0 or 1 PCM data/word clock DSD_PCM_7 116 DSD clock or 0 or 1 PCM data/word clock In Table 32 the signal allocation is given for the DSD/PCM signals to be connected to the stereo DAC. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 48 of 66 SAA7893HL Philips Semiconductors Super audio media player Table 32: Connection to a 4-channel DAC Output line Pin Mode = DSD number Mode = PCM Mode = 75 Hz DSD_PCM_8 117 DSD clock PCM data/word clock 0 or 1 DSD_PCM_9 120 0 or 1 PCM data/word clock 0 or 1 DSD_PCM_10 119 left channel Lf + Rf; 0 or 1 75 Hz DSD_PCM_11 121 right channel Lf + Rf; 0 or 1 0 or 1 Both tables show that DSD has a fixed allocation while PCM outputs are selectable. The I2S-bus bit stream, generated by the SAA7893HL decimation filter, is in the Philips format as can be seen in the timing diagrams. The number of data bits is always 24. Table 33: Serial bit clock frequency Audio input clock I2S output ‘wclk’ frequency DCLK (data bit) frequency 256fs 2fs 128fs 4fs 256fs 2fs 128fs no symmetrical bit clock 4fs 384fs 48 clocks for a word identification 2fs 128fs 4fs 256fs 2fs 128fs 4fs 256fs 384fs 512fs 768fs Remark The wclk identification is always active for 32 clocks for each left and right sample, except when the input clock is 384fs and the output sample frequency is 4fs; then the wclk is 48 samples active. 11.2.1 DSD output aud_clk td(o) dsd_clk (= 64fs) dsd_pcm-data SAMPLE N SAMPLE N + 1 MBL629 Fig 50. Audio I2S-bus output timing. Remark: in this example timing of the aud_clk is 256 × fs and DSD clock phase is set to logic 0. If phase is set to logic 1, the dsd_clk signal will be inverted. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 49 of 66 SAA7893HL Philips Semiconductors Super audio media player 11.2.2 Table 34: Timing numbers in DSD audio Symbol Parameter Min Max Unit td(o) output delay time with respect to the audio clock 4 20 ns I2S-PCM generated by the SAA7893HL In Figure 51 and Figure 52 the timing diagrams are given when the internal PCM generator of the SAA7893HL generates the I2S-PCM output signals. right channel right surround LFE left channel left surround center pcm_wclk_out twclk 32 pcm_dclk_out clock cycles pcm_dclk_out tdata pcm_LeRi_out pcm_LsRs_out pcm_CeLf_out MSB 1 2 3 22 LSB MSB 1 2 3 MBL630 24 data bits Fig 51. Audio I2S-bus output timing in Philips format. left channel left surround center right channel right surround LFE twclk 32 clock cycles tdata MSB 1 2 3 22 LSB MSB 1 2 3 MBL631 24 data bits Fig 52. Audio I2S-bus output timing in left justified format. Table 35: Timing numbers for PCM-I2S output Symbol Parameter Min Max Unit twclk pcm_wclk_out timing with respect to negative edge of pcm_dclk_out −10 +10 ns tdata pcm_data_out timing with respect to negative edge of pcm_dclk_out −10 +10 ns © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 50 of 66 SAA7893HL Philips Semiconductors Super audio media player 11.3 Audio output application diagrams 11.3.1 Hybrid DAC connection SAA7893HL 108 DSD_PCM_0 all slew rate controlled 109 DSD_PCM_1 output pins (no serial 110 resistors needed) DSD_PCM_2 DSD_PCM_3 DSD_PCM_4 DSD_PCM_5 DSD_PCM_6 DSD_PCM_7 DSD_PCM_8 DSD_PCM_9 DSD_PCM_10 aud_clk DSD_PCM_11 29 hybrid MCA DAC dsd_left/ i2s_lfrf sdata_ifrf dsd_right/ ’0’ dsd_centre/ i2s_celfe 111 dsd_lfe/ ’0’ 113 dsd_left_sur/ i2s_lsrs 114 dsd_right_sur/ ’0’ 115 dsd_clk/ i2s_dclk 116 ’0’/ i2s_wclk 117 dsd_clk/ i2s_dclk 120 ’0’/ i2s_wclk 119 dsd_left_mix/ i2s_lmrm 121 dsd_right_mix/ ’0’ M_x sdata_celfe M_x sdata_Isrs M_x sclk wclk sclk hybrid stereo DAC wclk sdata_Ifrf M_x audio clock mclk mclk MCE060 Fig 53. Hybrid DAC interface connection. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 51 of 66 SAA7893HL Philips Semiconductors Super audio media player 11.3.2 DSD DAC connection SAA7893HL DSD_PCM_0 DSD_PCM_1 DSD_PCM_2 DSD_PCM_3 DSD_PCM_4 DSD_PCM_5 DSD_PCM_6 DSD_PCM_7 DSD_PCM_8 DSD_PCM_9 DSD_PCM_10 DSD_PCM_11 aud_clk 29 108 dsd_left 109 dsd_right 110 dsd_centre 111 dsd_lfe 113 dsd_left_sur 114 dsd_right_sur 115 dsd_clk 116 dsd_left dsd_right dsd_centre dsd_lfe dsd_ls dsd_rs sclk n.c. mclk dsd_clk 117 120 DSD MCA DAC dsd_clk DSD stereo DAC n.c. 119 dsd_left_mix 121 dsd_right_mix dsd_left dsd_right audio clock mclk MCE061 Fig 54. DSD DAC interface connection. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 52 of 66 SAA7893HL Philips Semiconductors Super audio media player 11.3.3 PCM DAC connection SAA7893HL DSD_PCM_0 DSD_PCM_1 DSD_PCM_2 DSD_PCM_3 DSD_PCM_4 DSD_PCM_5 DSD_PCM_6 DSD_PCM_7 DSD_PCM_8 DSD_PCM_9 DSD_PCM_10 DSD_PCM_11 aud_clk 29 i2s_lfrf 108 109 i2s_celfe i2s_lsrs sdata_lsrs n.c. 115 i2s_dclk 116 i2s_wclk 117 i2s_dclk 120 i2s_wclk 119 i2s_lmrm 121 sdata_celfe n.c. 113 114 sdata_lfrf n.c. 110 111 PCM MCA DAC sclk wclk sclk mclk PCM stereo DAC wclk sdata_lfrf n.c. audio clock mclk MCE062 Fig 55. PCM DAC interface connection. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 53 of 66 SAA7893HL Philips Semiconductors Super audio media player 12. SDRAM interface 12.1 Writing clk td D_clk tcmd D_RASn D_CASn D_Wen nop active write precharge taddr D_ADDR[13:0] XX address address XX tdqm D_UDQM D_LDQM upper/lower byte tdata ZZZZ D_DQ[15:0] data ZZZZ MBL632 Fig 56. SDRAM interface writing. Table 36: Timing numbers of SDRAM interface writing Symbol Parameter Min Max Unit td delay from clk to D_clk of SDRAM interface D_clk is clock of SDRAM Conditions 3 9 ns tcmd delay from clk to control signals 1 15 ns taddr delay from clk to address lines 1 15 ns tdqm delay from clk to D_UDQM and D_LDQM signals 1 12 ns tdata delay from clk to data output signals 1 12 ns © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 54 of 66 SAA7893HL Philips Semiconductors Super audio media player 12.2 Reading clk td D_clk tcmd D_RASn D_CASn D_Wen nop active read nop nop nop precharge taddr D_ADDR[13:0] address address tdqm D_UDQM D_LDQM upper/lower byte tsu th data to SAA7893HL D_DQ[15:0] MBL634 Fig 57. SDRAM interface reading. Table 37: Timing numbers of SDRAM interface reading Symbol Parameter Conditions Min Max Unit td delay from clk to D_clk of SDRAM interface D_clk is clock of SDRAM 3 9 ns tcmd delay from clk to control signals 1 15 ns taddr delay from clk to address lines 1 15 ns tdqm delay from clk to D_UDQM and D_LDQM signals 1 12 ns tsu set-up time of data to clk 3 - ns th hold time of data from clk 3 - ns © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 55 of 66 SAA7893HL Philips Semiconductors Super audio media player 12.3 Interface connection +3.3 V 64 Mbit SDRAM SAA7893HL CKE D_DQ[15:0] DQ(15:0) D_ADDR[11:0] D_ADDR[12] D_ADDR[13] D_RASn D_CASn D_Wen D_clk D_UDQM D_LDQM A(11:0) 78 75 81 82 80 86 88 89 BA0 BA1 RAS_ CAS_ WE_ CLK DQMH DQML CS_ MCE063 Fig 58. SDRAM interface connection. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 56 of 66 SAA7893HL Philips Semiconductors Super audio media player 13. Power supply connections SAA7893HL 10 4.7 µF 100 nF 100 nF 4 37 100 nF 38 58 100 nF 17 76 100 nF 3.3 V 69 92 100 nF 83 106 100 nF 99 118 100 nF 100 MHz coil 4.7 µF 3.3 to 1.8 V CONVERTOR (LF18CD) 112 19 4.7 µF 100 nF 100 nF 20 85 100 MHz coil 4.7 µF 100 nF 3.3 to 1.8 V CONVERTOR (LF18CD) 84 32 4.7 µF 100 nF 100 nF 33 VCC_IO1 GND_IO1 VCC_IO7 GND_IO7 VCC_IO2 GND_IO2 VCC_IO3 GND_IO3 VCC_IO4 GND_IO4 VCC_IO5 GND_IO5 VCC_IO6 GND_IO6 VCC_Core1 GND_Core1 VCC_Core2 GND_Core2 VDDA VSSA MCE064 Fig 59. Power supply connections. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 57 of 66 SAA7893HL Philips Semiconductors Super audio media player 14. Software API 14.1 API provided by SA-MP Table 38: API provided by SA-MP Name Description Playback API NAV_AreaSwitch Switch SACD Area NAV_PlayTrack Start playing at the index of the track NAV_PlayAtTimecode Start playing at the given time NAV_Stop Stop playback NAV_Pause Pause playback NAV_ResumePlay Resume playback at normal speed NAV_NextTrack Continue with next track NAV_PreviousTrack Continue with previous track NAV_Repeat Set the repeat mode for playback NAV_RepeatAB Set the repeat AB mode NAV_Shuffle Play tracks in random order NAV_IntroScan Play only intro part of each track NAV_ForwardScan Start scanning forward – fast playback with burst sound NAV_BackwardScan Start scanning backward – fast playback with burst sound NAV_SetPlaySequence Set play sequence mode NAV_SetProgramList Set program list NAV_GetState Returns navigator states NAV_GetPlayList Returns navigator play list Post-processing API APM_SetSpeakers Select speaker configuration APM_SetInputMode Select between DSD or PCM as APM input APM_SetOutputMode Select APM output mode (DSD or PCM) APM_Set6chDownMix Set the downmix of six-channel output stream APM_Set2chDownMix Set the downmix of two-channel output stream APM_SetBassFilters Select the bass management frequency and slope APM_SetAttenuation Set attenuation of an output channel APM_SetDelay Set delay of a channel of output stream APM_SetFilterMode Set Sigma Delta modulator filter mode APM_SetPcmUpsampling Set the PCM upsampling mode APM_SetPIO Set the DAC PIO pins Text and Data API SDI_SetAvailableCharSets Set a list of character sets, application can handle SDI_SetLanguagePreference Set a list of preferred languages SDI_GetAlbumInfo Retrieve information about the album of active disc SDI_GetAlbumText Retrieve album text items © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 58 of 66 SAA7893HL Philips Semiconductors Super audio media player Table 38: API provided by SA-MP…continued Name Description SDI_GetNumberOfIndices Retrieve number of indices for specified track SDI_GetDiscInfo Retrieve information about the active disc SDI_GetDiscText Retrieve disc text items SDI_GetAreaText Retrieve area text items SDI_GetTrackInfo Retrieve information about the specified track SDI_GetTrackText Retrieve track text items System configuration API SDM_SetBeType Select the front-end interface attached to SA-MP SDM_SetDacPinnning Configure the DAC pins SDM_SetAudioClock Configure the audio clock for different input stream modes SDM_SetMemoryConfig Configure the SDRAM attached to the SAA7893HL SDM_GetHandler Return the pointer to SA-MP interrupt handler SDM_SetDsdClockPolarity Configure the DSD clock polarity SDM_SetSystemClock Inform SA-MP about the system clock SDM_SetBurstLength Configure the burst length for fast play General API SAMP_Init Initialize SA-MP SAMP_Term Terminate SA-MP SAMP_Activate Activate SA-MP SAMP_Reactivate Reactivate SA-MP SAMP_Deactivate Deactivate SA-MP SAMP_SACDDiscReq SACD disc recognition 14.2 API required by SA-MP Software to be provided by the DVD host: • For the front-end: Seek, GetDataArea, TransferRate (optional) • For the operating system: Tasks, Interrupts, Semaphores, Mailboxes, Timers. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 59 of 66 SAA7893HL Philips Semiconductors Super audio media player 15. Limiting values Table 39: Absolute maximum ratings In accordance with the Absolute Maximum Rating System (IEC 60134). Note 1. Symbol Parameter Min Max Unit VCC_Core digital core supply voltage −0.5 +2.1 V VCC_IO IO pins supply voltage −0.5 +3.8 V VDDA analog supply voltage −0.5 +2.1 V VI DC input voltage −0.5 +5.5 V Tamb ambient temperature 0 70 °C Tstg storage temperature −25 +125 °C Tj junction temperature −150 +150 °C [1] Stresses above the absolute maximum ratings may cause permanent damage to the device. Exposure to absolute maximum ratings for extended periods may effect device reliability. 16. Characteristics Table 40: Characteristics Symbol Parameter Min Typ Max Unit Power supply: VCC_Core (digital core supply voltage) VCC_Core digital core supply voltage 1.65 1.8 1.95 V P power dissipation 90 110 150 mW Power supply: VDDA (analog supply voltage) VDDA analog supply voltage 1.65 1.8 1.95 V P power dissipation during disc recognition only - 40 60 mW Power supply: VCC_IO (I/O pins supply voltage) VCC_IO I/O pins supply voltage 3.0 3.3 3.6 V P power dissipation during disc recognition only - 70 100 mW Digital inputs and outputs VIH HIGH-level input voltage 2.0 - VCC_IO + 0.5 V VIL LOW-level input voltage - - 0.8 V VOH HIGH-level output voltage VCC_IO − 0.4 - - V VOL LOW-level output voltage - - 0.4 V Ci input capacitance - - 10 pF Co output capacitance - - 10 pF ILI input leakage current - - ±10 µA Ii(n) input current on any pin except supplies - - ±10 mA © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 60 of 66 SAA7893HL Philips Semiconductors Super audio media player 17. Package outline LQFP128: plastic low profile quad flat package; 128 leads; body 14 x 20 x 1.4 mm SOT425-1 c y X A 65 102 64 103 ZE e E HE A A2 A 1 (A 3) θ wM Lp bp pin 1 index L detail X 39 128 1 38 v M A ZD wM bp e D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 20.1 19.9 14.1 13.9 0.5 HD HE 22.15 16.15 21.85 15.85 L Lp v w y 1.0 0.75 0.45 0.2 0.12 0.1 Z D(1) Z E(1) 0.81 0.59 0.81 0.59 θ o 7 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT425-1 136E28 MS-026 EIAJ EUROPEAN PROJECTION ISSUE DATE 99-12-27 00-01-19 Fig 60. LQFP128 (SOT425-1) package outline. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 61 of 66 SAA7893HL Philips Semiconductors Super audio media player 18. Soldering 18.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 18.2 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferably be kept: • below 220 °C for all the BGA packages and packages with a thickness ≥ 2.5mm and packages with a thickness <2.5 mm and a volume ≥350 mm3 so called thick/large packages • below 235 °C for packages with a thickness <2.5 mm and a volume <350 mm3 so called small/thin packages. 18.3 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 62 of 66 SAA7893HL Philips Semiconductors Super audio media player • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 18.4 Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 18.5 Package related soldering information Table 41: Suitability of surface mount IC packages for wave and reflow soldering methods Package[1] Soldering method BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS Reflow[2] not suitable suitable not suitable[3] suitable PLCC[4], SO, SOJ suitable suitable LQFP, QFP, TQFP not recommended[4][5] suitable SSOP, TSSOP, VSO, VSSOP [1] [2] [3] [4] [5] [6] not recommended[6] suitable For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Wave Rev. 02 — 26 February 2003 63 of 66 SAA7893HL Philips Semiconductors Super audio media player 19. Revision history Table 42: Revision history Rev Date 02 20030226 CPCN Description - Product data (9397 750 10925) Modifications: • • • • • 01 20021014 - The value of the capacitor to pin Adcrefl in Figure 44 is changed from 10 nF to 100 nF The system clock definitions are added in Section 7.5.1 The audio clock definitions are added in Section 7.5.2 A remark is added at the end of Section 8.2. A note is added to Table 11. Product data (9397 750 10341) © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Product data Rev. 02 — 26 February 2003 64 of 66 SAA7893HL Philips Semiconductors Super audio media player 20. Data sheet status Level Data sheet status[1] Product status[2][3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 21. Definitions customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 22. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors 23. Trademarks Dolby — Available only to licensees of Dolby Laboratories Licensing Corporation, San Francisco, CA94111, USA, from whom licensing and application information must be obtained. Dolby is a registered trade-mark of Dolby Laboratories Licensing Corporation. Contact information For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: [email protected]. Product data Fax: +31 40 27 24825 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10925 Rev. 02 — 26 February 2003 65 of 66 SAA7893HL Philips Semiconductors Super audio media player Contents 1 1.1 1.2 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.6 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 9 9.1 9.2 9.3 10 10.1 10.2 10.3 11 11.1 11.2 11.3 12 General description . . . . . . . . . . . . . . . . . . . . . . 1 Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Components . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 HW interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . 3 SW interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . 3 System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 System configuration . . . . . . . . . . . . . . . . . . . . 4 SACD playback. . . . . . . . . . . . . . . . . . . . . . . . . 4 Audio postprocessing . . . . . . . . . . . . . . . . . . . . 4 SACD data and text . . . . . . . . . . . . . . . . . . . . . 5 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Ordering information . . . . . . . . . . . . . . . . . . . . . 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 7 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Host interface . . . . . . . . . . . . . . . . . . . . . . . . . 11 Front-end interface . . . . . . . . . . . . . . . . . . . . . 11 Audio interface . . . . . . . . . . . . . . . . . . . . . . . . 12 SDRAM interface . . . . . . . . . . . . . . . . . . . . . . 12 Clock and reset input . . . . . . . . . . . . . . . . . . . 12 Test inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Host interface . . . . . . . . . . . . . . . . . . . . . . . . . . 14 General description. . . . . . . . . . . . . . . . . . . . . 14 SAD16_01/02 mode . . . . . . . . . . . . . . . . . . . . 15 SAD16_03 mode . . . . . . . . . . . . . . . . . . . . . . 19 MAD16_01 mode . . . . . . . . . . . . . . . . . . . . . . 25 MAD16_02 mode . . . . . . . . . . . . . . . . . . . . . . 30 SAD08 mode . . . . . . . . . . . . . . . . . . . . . . . . . 33 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Front-end interface . . . . . . . . . . . . . . . . . . . . . 37 I2S-bus interface . . . . . . . . . . . . . . . . . . . . . . . 38 UDE data interface . . . . . . . . . . . . . . . . . . . . . 40 FEC interface . . . . . . . . . . . . . . . . . . . . . . . . . 43 HF input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 HF input specification . . . . . . . . . . . . . . . . . . . 45 HF-input application diagram . . . . . . . . . . . . . 46 Audio interfaces. . . . . . . . . . . . . . . . . . . . . . . . 46 Audio input interface . . . . . . . . . . . . . . . . . . . . 46 Audio output interface . . . . . . . . . . . . . . . . . . . 47 Audio output application diagrams . . . . . . . . . 51 SDRAM interface . . . . . . . . . . . . . . . . . . . . . . . 54 © Koninklijke Philips Electronics N.V. 2003. Printed in The Netherlands All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 26 February 2003 Document order number: 9397 750 10925 12.1 12.2 12.3 13 14 14.1 14.2 15 16 17 18 18.1 18.2 18.3 18.4 18.5 19 20 21 22 23 Writing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interface connection . . . . . . . . . . . . . . . . . . . . Power supply connections . . . . . . . . . . . . . . . Software API . . . . . . . . . . . . . . . . . . . . . . . . . . API provided by SA-MP . . . . . . . . . . . . . . . . . API required by SA-MP . . . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Characteristics . . . . . . . . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Manual soldering . . . . . . . . . . . . . . . . . . . . . . Package related soldering information . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Data sheet status. . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 55 56 57 58 58 59 60 60 61 62 62 62 62 63 63 64 65 65 65 65