INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4078B gates 8-input NOR gate Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification HEF4078B gates 8-input NOR gate DESCRIPTION The HEF4078B provides the positive 8-input NOR function. The outputs are fully buffered for highest noise immunity and pattern insensitivity of output impedance. Fig.2 Pinning diagram. HEF4078BP(N): 14-lead DIL; plastic HEF4078BD(F): 14-lead DIL; ceramic (cerdip) (SOT27-1) (SOT73) HEF4078BT(D): 14-lead SO; plastic (SOT108-1) Fig.1 Functional diagram. ( ): Package Designator North America FAMILY DATA, IDD LIMITS category GATES See Family Specifications Fig.3 Logic diagram. January 1995 2 Philips Semiconductors Product specification HEF4078B gates 8-input NOR gate AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V SYMBOL TYP. TYPICAL EXTRAPOLATION FORMULA MAX. Propagation delays In → On HIGH to LOW 80 160 ns 53 ns + (0,55 ns/pF) CL 35 70 ns 24 ns + (0,23 ns/pF) CL 25 50 ns 17 ns + (0,16 ns/pF) CL 80 160 ns 53 ns + (0,55 ns/pF) CL 35 70 ns 24 ns + (0,23 ns/pF) CL 15 25 50 ns 17 ns + (0,16 ns/pF) CL 5 60 120 ns 10 ns + (1,0 ns/pF) CL 30 60 ns 5 10 tPHL 15 5 LOW to HIGH 10 tPLH Output transition times HIGH to LOW LOW to HIGH 10 tTHL 6 ns + (0,28 ns/pF) CL 15 20 40 ns 5 60 120 ns 30 60 ns 9 ns + (0,42 ns/pF) CL 20 40 ns 6 ns + (0,28 ns/pF) CL 10 tTLH 15 VDD V Dynamic power 9 ns + (0,42 ns/pF) CL 5 10 ns + (1,0 ns/pF) CL TYPICAL FORMULA FOR P (µW) 750 fi + ∑ (foCL) × VDD 2 dissipation per 10 2800 fi + ∑ (foCL) × VDD package (P) 15 7500 fi + ∑ (foCL) × VDD 2 2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) January 1995 3