INTEGRATED CIRCUITS 74LV74 Dual D-type flip-flop with set and reset; positive-edge trigger Product specification Supersedes data of 1996 Nov 07 IC24 Data Handbook 1998 Apr 20 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive edge-trigger FEATURES 74LV74 DESCRIPTION • Wide operating voltage: 1.0 to 5.5V • Optimized for Low Voltage applications: 1.0 to 3.6V • Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V • Typical VOLP (output ground bounce) 0.8V @ VCC = 3.3V, The 74LV74 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT74. The 74LV74 is a dual positive edge triggered, D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (SD) and (RD) inputs; also complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation. Tamb = 25°C • Typical VOHV (output VOH undershoot) 2V @ VCC = 3.3V, Tamb = 25°C • Output capability: standard • ICC category: flip-flops Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; tr =tf 2.5 ns SYMBOL PARAMETER tPHL/tPLH Propagation delay nCP to nQ, nQ nSD to nQ, nQ nRD to nQ, nQ fmax Maximum clock frequency CI Input capacitance CPD Power dissipation capacitance per flip-flop CONDITIONS TYPICAL CL = 15pF VCC = 3.3V UNIT 11 14 14 CL = 15pF VCC = 3.3V Notes 1 and 2 ns 76 MHz 3.5 pF 24 pF NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD VCC2 x fi (CL VCC2 fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL VCC2 fo) = sum of the outputs. 2. The condition is VI = GND to VCC ORDERING INFORMATION TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. # 14-Pin Plastic DIL PACKAGES –40°C to +125°C 74LV74 N 74LV74 N SOT27-1 14-Pin Plastic SO –40°C to +125°C 74LV74 D 74LV74 D SOT108-1 14-Pin Plastic SSOP Type II –40°C to +125°C 74LV74 DB 74LV74 DB SOT337-1 14-Pin Plastic TSSOP Type I –40°C to +125°C 74LV74 PW 74LV74PW DH SOT402-1 PIN DESCRIPTION PIN NUMBER SYMBOL FUNCTION Asynchronous reset-direct input (active-LOW) 1, 13 1RD, 2RD 2, 12 1D, 2D 3, 11 1CP, 2CP Clock input (LOW-to-HIGH), edge-triggered) 4, 10 1SD, 2SD Asynchronous set-direct input (active-LOW) 5, 9 1Q, 2Q True flip-flop outputs 6, 8 1Q, 2Q Complement flip-flop outputs Data inputs 7 GND Ground (0V) 14 VCC Positive supply voltage 1998 Apr 20 FUNCTION TABLE INPUTS SD RD CP L H X H L X L L X OUTPUTS D Q Q X X X H L H L H H INPUTS SD RD CP D Qn+1 Qn+1 H H H H L H L H H L H L X Qn+1 2 OUTPUTS = = = = = HIGH voltage level LOW voltage level don’t care LOW-to-HIGH CP transition state after the next LOW-to-HIGH CP transition 853-1888 19258 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive edge-trigger 74LV74 PIN CONFIGURATION LOGIC SYMBOL 1RD 1 14 VCC 1D 2 13 2RD 1CP 3 12 2D 1SD 4 11 2CP 1Q 5 10 2SD 4 10 1SD 2SD 2 1D 12 2D 3 1CP 11 2CP SD D Q CP 6 9 2Q GND 7 8 2Q Q 1RD 1 2 1 11 5 4 1SD 2 1D 6 3 1CP R S D SD Q 2D 13 R 1Q 5 1Q 6 2Q 9 2Q 8 CP FF1 RD 9 1 1RD C2 12 8 2RD 13 Q 10 6 2Q FUNCTIONAL DIAGRAM C1 1D 1Q SV00331 LOGIC SYMBOL (IEEE/IEC) S 9 FF SV00330 3 5 2Q RD 1Q 4 1Q 10 2SD 8 12 2D SV00332 11 2CP D SD Q CP FF2 Q RD 13 2RD SV00333 1998 Apr 20 3 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive edge-trigger 74LV74 LOGIC DIAGRAM (ONE FLIP-FLOP) Q C C C C C C D Q C C RD SD CP C C SV00334 RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER CONDITIONS MIN TYP. MAX UNIT See Note1 1.0 3.3 5.5 V 0 – VCC V 0 – VCC V +85 +125 °C 500 200 100 50 ns/V DC supply voltage VI Input voltage VO Output voltage Tamb Operating ambient temperature range in free air tr, tf Input rise and fall times except for Schmitt-trigger inputs See DC and AC characteristics VCC = 1.0V to 2.0V VCC = 2.0V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V to 5.5V –40 –40 – – – – – – – – NOTE: 1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V. ABSOLUTE MAXIMUM RATINGS1, 2 In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) SYMBOL PARAMETER VCC DC supply voltage CONDITIONS RATING UNIT –0.5 to +7.0 V ±IIK DC input diode current VI < –0.5 or VI > VCC + 0.5V 20 mA ±IOK DC output diode current VO < –0.5 or VO > VCC + 0.5V 50 mA ±IO DC output source or sink current – standard outputs –0.5V < VO < VCC + 0.5V 25 ±IGND, ±ICC DC VCC or GND current for types with –standard outputs Tstg Storage temperature range Ptot t t Power dissipation per package –plastic DIL –plastic mini-pack (SO) –plastic shrink mini-pack (SSOP and TSSOP) 50 –65 to +150 for temperature range: –40 to +125°C above +70°C derate linearly with 12mW/K above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K 750 500 400 mA mA °C mW NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 1998 Apr 20 4 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive edge-trigger 74LV74 DC CHARACTERISTICS Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS SYMBOL PARAMETER -40°C to +85°C TEST CONDITIONS MIN VIH VIL HIGH level Input voltage LOW level Input voltage TYP1 VOH VOL VOL HIGH level output voltage; g STANDARD outputs LOW level output voltage all outputs out uts voltage; LOW level output voltage; g STANDARD outputs MIN 0.9 0.9 VCC = 2.0V 1.4 1.4 VCC = 2.7 to 3.6V 2.0 2.0 VCC = 4.5 to 5.5V 0.7*VCC UNIT MAX V 0.7*VCC VCC = 1.2V 0.3 0.3 VCC = 2.0V 0.6 0.6 VCC = 2.7 to 3.6V 0.8 0.8 0.3*VCC 0.3*VCC VCC = 1.2V; VI = VIH or VIL; –IO = 100µA HIGH level output voltage out uts voltage; all outputs MAX VCC = 1.2V VCC = 4.5 to 5.5 VOH -40°C to +125°C V 1.2 VCC = 2.0V; VI = VIH or VIL; –IO = 100µA 1.8 2.0 1.8 VCC = 2.7V; VI = VIH or VIL; –IO = 100µA 2.5 2.7 2.5 VCC = 3.0V; VI = VIH or VIL; –IO = 100µA 2.8 3.0 2.8 VCC = 4.5V;VI = VIH or VIL; –IO = 100µA 4.3 4.5 4.3 VCC = 3.0V;VI = VIH or VIL; –IO = 6mA 2.40 2.82 2.20 VCC = 4.5V;VI = VIH or VIL; –IO = 12mA 3.60 4.20 3.50 V V VCC = 1.2V; VI = VIH or VIL; IO = 100µA VCC = 2.0V; VI = VIH or VIL; IO = 100µA 0 0 0.2 0.2 VCC = 2.7V; VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VCC = 3.0V;VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VCC = 4.5V;VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VCC = 3.0V;VI = VIH or VIL; IO = 6mA 0.25 0.40 0.50 VCC = 4.5V;VI = VIH or VIL; IO = 12mA 0.35 0.55 0.65 V V Input leakage current VCC = 5.5V; VI = VCC or GND 1.0 1.0 µA ICC Quiescent supply current; flip-flops VCC = 5.5V; VI = VCC or GND; IO = 0 20.0 80 µA ∆ICC Additional quiescent supply current per input VCC = 2.7V to 3.6V; VI = VCC –0.6V 500 850 µA II NOTE: 1. All typical values are measured at Tamb = 25°C. 1998 Apr 20 5 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive edge-trigger 74LV74 AC CHARACTERISTICS GND = 0V; tr = tf 2.5ns; CL = 50pF; RL = 1KΩ SYMBOL tPHL/tPLH tPHL/tPLH tPHL/tPLH tW tW trem tsu th fmax PARAMETER Propagation delay nCP to nQ, nQ Propagation delay nSD to nQ, nQ Propagation delay nRD to nQ, nQ Clock pulse width HIGH to LOW Set or reset pulse width LOW Removal time set or reset Set up time Set-up nD to nCP Hold time nD to nCP Maximum clock pulse frequency WAVEFORM TYP1 1.2 – 2.0 – MIN 70 – – – 24 44 – 56 18 28 – 41 132 26 – 33 4.5 to 5.5 – 9.53 17 – 23 1.2 – 90 – – – 2.0 – 31 46 – 58 2.7 – 23 34 – 43 3.0 to 3.6 – 172 27 – 34 4.5 to 5.5 – 123 19 – 24 1.2 – 90 – – – 2.0 – 31 46 – 58 2.7 – 23 34 – 43 3.0 to 3.6 – 172 27 – 34 4.5 to 5.5 – 123 19 – 24 2.0 34 10 – 41 – 2.7 25 8 – 30 – 3.0 to 3.6 20 72 – 24 – 4.5 to 5.5 15 63 – 18 – 2.0 34 10 – 41 – 2.7 25 8 – 30 – 3.0 to 3.6 20 72 – 24 – 4.5 to 5.5 15 63 – 18 – 1.2 – 5 – – – 2.0 14 2 – 15 – 2.7 10 1 – 11 – 3.0 to 3.6 8 12 – 9 – 4.5 to 5.5 6 13 – 7 – 1.2 – 10 – – – 2.0 22 4 – 26 – 2.7 12 3 – 15 – 3.0 to 3.6 8 22 – 10 – 4.5 to 5.5 6 12 – 8 – 1.2 – –10 – – – 2.0 3 –2 – 3 – 2.7 3 –2 – 3 – 3.0 to 3.6 3 –22 – 3 – 4.5 to 5.5 3 –23 – 3 – 2.0 14 40 – 12 – 2.7 50 90 – 40 – 3.0 to 3.6 60 1002 – 48 – 4.5 to 5.5 70 1103 – 56 – Figure 2 Figure 1 Figure 1 6 UNIT MAX – NOTE: 1. Unless otherwise stated, all typical values are at Tamb = 25°C. 2. Typical value measured at VCC = 3.3V. 3. Typical value measured at VCC = 5.0V. 1998 Apr 20 MAX – Figures 2, 3 Figure 1 MIN 2.7 Figures 2, 3 Figure 2 VCC(V) LIMITS –40 to +125 °C 3.0 to 3.6 Figures, 1, 3 Figure 1 LIMITS –40 to +85 °C CONDITION ns ns ns ns ns ns ns ns MHz Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive edge-trigger 74LV74 AC WAVEFORMS TEST CIRCUIT VM = 1.5V at VCC 2.7V 3.6V VM = 0.5 * VCC at VCC 2.7V and 4.5V VOL and VOH are the typical output voltage drop that occur with the output load. Vcc ÏÏÏ ÏÏÏÏ ÏÏÏ ÏÏÏ ÏÏÏÏ ÏÏÏ VI nD INPUT 1/fmax VI DEFINITIONS RL = Load resistor VM GND CL = Load capacitance includes jig and probe capacitiance RT = Termination resistance should be equal to ZOUT of pulse generators. tW tPHL tPLH VOH TEST nQ OUTPUT VM VCC tPLH/tPHL VOL VOH nQ OUTPUT RL= 1k CL Test Circuit for Outputs tsu nCP INPUT 50pF RT th th tsu VI < 2.7V VCC 2.7–3.6V 2.7V ≥ 4.5 V VCC VM SV00902 VOL Figure 3. Load circuitry for switching times tPHL tPLH SV00335 Figure 1.The clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nD to nCP setup times, the nCP to nD hold times, the output transition times and the maximum clock pulse frequency NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. VI VM nCP INPUT GND trem VI nSD INPUT GND VI VM tW tW VM nRD INPUT GND VOH nQ OUTPUT tPLH tPHL VM VOL VOH nQ OUTPUT VOL VM tPHL tPLH SV00336 Figure 2.The set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set and reset pulse widths and the nRD to nCP removal time 1998 Apr 20 D.U.T. VM GND VO Vl PULSE GENERATOR 7 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive edge-trigger 74LV74 DIP14: plastic dual in-line package; 14 leads (300 mil) 1998 Apr 20 8 SOT27-1 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive edge-trigger 74LV74 SO14: plastic small outline package; 14 leads; body width 3.9 mm 1998 Apr 20 9 SOT108-1 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive edge-trigger SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm 1998 Apr 20 10 74LV74 SOT337-1 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive edge-trigger TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm 1998 Apr 20 11 74LV74 SOT402-1 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive edge-trigger 74LV74 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 05-96 9397-750-04414