INTEGRATED CIRCUITS 74ALS373/74ALS374 Latch/flip–flop Product specification IC05 Data Handbook 1991 Feb 08 Philips Semiconductors Product specification Latch/flip-flop 74ALS373/74ALS374 74ALS373 Octal transparent latch (3-State) 74ALS374 Octal D flip-flop (3-State) FEATURES DESCRIPTION • 8-bit transparent latch – 74ALS373 • 8-bit positive edge triggered register – 74ALS374 • 3-State output buffers • Common 3-State output register • Independent register and 3-State buffer operation TYPE The 74ALS373 is an octal transparent latch coupled to eight 3-State output devices. The two sections of the device are controlled independently by enable (E) and output enable (OE) control gates. The data on the D inputs is transferred to the latch outputs when the enable (E) input is High. The latch remains transparent to the data input while E is High, and stores the data that is present one setup time before the High-to-Low enable transition. TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 6.0ns 14mA 74ALS373 TYPE 74ALS374 TYPICAL fMAX TYPICAL SUPPLY CURRENT (TOTAL) 50MHz 17mA The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active-Low output enable (OE) controls all eight 3-State buffers independent of the latch operation. When OE is Low, latched or transparent data appears at the output. When OE is High, the outputs are in High impedance “off” state, which means they will neither drive nor load the bus. The 74ALS374 is an 8-bit edge triggered register coupled to eight 3-State output buffers. The two sections of the device are controlled independently by clock (CP) and output enable (OE) control gates. The register is fully edge triggered. The state of the D input, one setup time before the Low-to-High clock transition is transferred to the corresponding flip-flop’s Q output. ORDERING INFORMATION The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C DRAWING NUMBER 20-pin plastic DIP 74ALS373N, 74ALS374N SOT146-1 20-pin plastic SOL 74ALS373D, 74ALS374D SOT163-1 20-pin plastic SSOP Type II 74ALS373DB, 74ALS374DB SOT339-1 The active-Low output enable (OE) controls all eight 3-State buffers independent of the register operation. When OE is Low, the data in the register appears at the outputs. When OE is High, the outputs are in High impedance “off” state, which means they will neither drive nor load the bus. INPUT AND OUTPUT LOADING AND FAN-OUT TABLE 74ALS (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW Data inputs 1.0/1.0 20µA/0.1mA Enable input (active-High) 1.0/1.0 20µA/0.1mA Output enable inputs (active-Low) 1.0/1.0 20µA/0.1mA Clock pulse input (active rising edge) 1.0/1.0 20µA/0.1mA 3-State outputs 130/240 2.6mA/24mA PINS D0 – D7 E (74ALS373) OE CP (74ALS374) Q0 – Q7 DESCRIPTION NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state. 1991 Feb 08 2 853–1243 01670 Philips Semiconductors Product specification Latch/flip-flop 74ALS373/74ALS374 PIN CONFIGURATION – 74ALS373 PIN CONFIGURATION – 74ALS374 OE 1 20 VCC Q0 2 19 Q7 D0 3 OE 1 20 VCC Q0 2 19 Q7 D0 3 18 D7 D1 4 17 D6 Q1 5 16 Q6 Q2 6 15 Q5 D2 7 14 D5 D3 8 13 D4 Q3 9 12 Q4 GND 10 11 CP 18 D7 D1 4 17 D6 Q1 5 16 Q6 Q2 6 15 Q5 D2 7 14 D5 D3 8 13 D4 Q3 9 12 Q4 GND 10 11 E SF00250 SF00253 LOGIC SYMBOL – 74ALS373 3 4 7 8 13 LOGIC SYMBOL – 74ALS374 14 17 18 3 D0 D1 D2 D3 D4 D5 D6 D7 11 E 11 CP 1 OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 5 6 9 12 15 16 8 13 14 17 18 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 19 2 5 6 9 12 15 16 19 VCC = Pin 20 GND = Pin 10 VCC = Pin 20 GND = Pin 10 SF00254 SF00251 IEC/IEEE SYMBOL – 74ALS373 1 11 IEC/IEEE SYMBOL – 74ALS374 1 EN1 11 EN2 EN1 C1 2 3 4 5 4 5 7 6 7 6 8 9 8 9 3 2D 1 2D 1 2 13 12 13 12 14 15 14 15 17 16 17 16 18 19 18 19 SF00252 1991 Feb 08 7 D0 D1 D2 D3 D4 D5 D6 D7 OE 1 4 SC00098 3 Philips Semiconductors Product specification Latch/flip-flop 74ALS373/74ALS374 LOGIC DIAGRAM – 74ALS373 D1 4 D0 3 D E E OE D2 7 D E Q D3 8 D E Q D4 13 D E Q D5 14 D E Q D6 17 D E Q D7 18 D E Q D E Q Q 11 1 VCC = Pin 20 GND = Pin 10 2 5 6 9 Q0 Q1 Q2 Q3 12 15 Q4 Q5 16 Q6 19 Q7 SF00256 FUNCTION TABLE – 74ALS373 INPUTS OUTPUTS INTERNAL REGISTER Dn OPERATING MODE OE E Q0 – Q7 L H L L L L H H H H L ↓ l L L L ↓ h H H L L X NC NC H L X NC Z H H Dn Dn Z Enable and read register H = h = L = l = NC= X = Z = ↓ = Latch and read register High-voltage level High state must be present one setup time before the High-to-Low enable transition Low-voltage level Low state must be present one setup time before the High-to-Low enable transition No change Don’t care High impedance “off” state High-to-Low enable transition 1991 Feb 08 4 Hold Disable outputs Philips Semiconductors Product specification Latch/flip-flop 74ALS373/74ALS374 LOGIC DIAGRAM – 74ALS374 D1 4 D0 3 D CP Q D CP Q CP OE D2 7 D3 8 D CP Q D4 13 D CP Q D5 14 D CP Q D6 17 D CP Q D7 18 D CP Q D CP Q 11 1 VCC = Pin 20 GND = Pin 10 2 5 6 9 Q0 Q1 Q2 Q3 12 15 Q4 Q5 16 19 Q6 Q7 SF00257 FUNCTION TABLE – 74ALS374 INPUTS OUTPUTS INTERNAL REGISTER H = h = L = l = NC= X = Z = ↑ = ↑ = Dn OPERATING MODE OE CP Q0 – Q7 L ↑ l L L L ↑ h H H L ↑ X NC NC H ↑ X NC Z H ↑ Dn Dn Z Load and read register Hold Disable outputs High-voltage level High state must be present one setup time before the Low-to-High clock transition Low-voltage level Low state must be present one setup time before the Low-to-High clock transition No change Don’t care High impedance “off” state Low-to-High clock transition Not Low-to-High clock transition ABSOLUTE MAXIMUM RATINGS (Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) PARAMETER SYMBOL RATING UNIT VCC Supply voltage –0.5 to +7.0 V VIN Input voltage –0.5 to +7.0 V IIN Input current –30 to +5 mA –0.5 to VCC V VOUT Voltage applied to output in High output state IOUT Current applied to output in Low output state Tamb Operating free-air temperature range Tstg Storage temperature range 1991 Feb 08 5 48 mA 0 to +70 °C –65 to +150 °C Philips Semiconductors Product specification Latch/flip-flop 74ALS373/74ALS374 RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL PARAMETER UNIT MIN NOM MAX 5.0 5.5 VCC Supply voltage 4.5 VIH High-level input voltage 2.0 VIL Low-level input voltage 0.8 V IIK Input clamp current –18 mA IOH High-level output current –2.6 mA IOL Low-level output current 24 mA +70 °C Tamb Operating free-air temperature range V V 0 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL LIMITS TEST CONDITIONS1 PARAMETER MIN VOH O High level output voltage High-level TYP2 UNIT MAX VCC = ±10%,, VIL = MAX,, VIH = MIN IOH = –0.4mA VCC – 2 V IOH = MAX 2.4 VCC = MIN,, VIL = MAX,, VIH = MIN IOL = 12mA 0.25 0.40 V IOL = 24mA 0.35 0.50 V –0.73 –1.2 V 3.2 V VOL O Low level output voltage Low-level VIK Input clamp voltage VCC = MIN, II = IIK II Input current at maximum input voltage VCC = MAX, VI = 7.0V 0.1 mA IIH High-level input current VCC = MAX, VI = 2.7V 20 µA Low-level input current –0.1 mA IIL –0.2 mA 74ALS373 74ALS374 VCC = MAX, MAX VI = 0 0.4V 4V IOZH Off-state output current, High-level voltage applied VCC = MAX, VI = 2.7V 20 µA IOZL Off-state output current, Low-level voltage applied VCC = MAX, VI = 0.4V –20 µA Output current3 VCC = MAX, VO = 2.25V –112 mA 7 16 mA 14 25 mA ICCZ 17 27 mA ICCH 11 19 mA 19 29 mA 20 31 mA IO ICCH 74ALS373 ICC Supply current (total) 74ALS374 ICCL ICCL VCC = MAX VCC = MAX ICCZ –30 NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. 1991 Feb 08 6 Philips Semiconductors Product specification Latch/flip-flop 74ALS373/74ALS374 AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω MIN MAX UNIT tPLH tPHL Propagation delay Dn to Qn Waveform 3 2.0 2.0 12.0 14.0 ns tPLH tPHL Propagation delay E to Qn Waveform 2 3.0 3.0 14.0 14.0 ns tPZH tPZL Output enable time to High or Low level Waveform 6 Waveform 7 2.0 3.0 14.0 14.0 ns tPHZ tPLZ Output disable time from High or Low level Waveform 6 Waveform 7 2.0 2.0 10.0 12.0 ns fMAX Maximum clock frequency Waveform 1 50 tPLH tPHL Propagation delay CP to Qn Waveform 1 3.0 4.0 12.0 14.0 ns Waveform 6 Waveform 7 3.0 3.0 9.0 11.0 ns Waveform 6 Waveform 7 2.0 3.0 10.0 12.0 ns 74ALS373 74ALS374 tPZH tPZL Output enable time to High or Low level tPHZ tPLZ Output disable time from High or Low level MHz AC SETUP REQUIREMENTS LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω MIN tsu(H) tsu(L) Setup time, High or Low Dn to E th(H) th(L) Hold time, High or Low Dn to E tw(H) E Pulse width, High tsu(H) tsu(L) Setup time, High or Low Dn to CP th(H) th(L) Hold time, High or Low Dn to CP tw(H) tw(L) CP Pulse width, High or Low 1991 Feb 08 74ALS373 74ALS374 7 UNIT MAX Waveform 4 6.0 6.0 ns Waveform 4 6.0 6.0 ns Waveform 2 10.0 ns Waveform 5 6.0 6.0 ns Waveform 5 1.0 1.0 ns Waveform 1 10.0 10.0 ns Philips Semiconductors Product specification Latch/flip-flop 74ALS373/74ALS374 AC WAVEFORMS For all waveforms, VM = 1.3V. The shaded areas indicate when the input is permitted to change for predictable output performance. 1/fmax CP V M tw(H) VM E VM VM VM VM tw(H) tPLH tw(L) tPHL VM Qn tPHL tPLH Qn VM VM VM SF00258 SF00259 Waveform 1. Propagation Delay for Clock Input to Output, Clock Pulse Widths, and Maximum Clock Frequency Dn VM Waveform 2. Propagation Delay for Enable to Output and Enable Pulse Width VM tPHL tPLH Qn VM VM SF00260 Waveform 3. Propagation Delay for Data to Output Dn VM tsu(H) E VM VM tsu(L) th(H) Dn VM th(L) tsu(H) CP VM VM VM VM VM tsu(L) th(H) VM VM th(L) VM SF00261 SF00262 Waveform 4. Data Setup Time and Hold Times OE VM Waveform 5. Data Setup Time and Hold Times OE VM tPZH tPHZ VOH -0.3V VM VM tPZL tPLZ 3.5V Qn Qn VM VM 0V VOL +0.3V SC00099 SC00100 Waveform 6. 3-State Output Enable Time to High Level and Output Disable Time from High Level Waveform 7. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level 1991 Feb 08 8 Philips Semiconductors Product specification Latch/flip-flop 74ALS373/74ALS374 TEST CIRCUIT AND WAVEFORMS VCC 7.0V VIN VOUT PULSE GENERATOR tw 90% NEGATIVE PULSE 10% RL CL RL AMP (V) VM VM D.U.T. RT 90% 10% tTHL (tff) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0.3V AMP (V) 90% Test Circuit for 3-State Outputs POSITIVE PULSE VM VM 10% 10% tw SWITCH POSITION TEST SWITCH closed tPLZ, tPZL All other 90% 0.3V Input Pulse Definition open INPUT PULSE REQUIREMENTS Family Amplitude VM DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators. 74ALS 3.5V 1.3V Rep.Rate tw tTLH tTHL 1MHz 500ns 2.0ns 2.0ns SC00072 1991 Feb 08 9 Philips Semiconductors Product specification Latch/flip–flop 74ALS373/74ALS374 DIP20: plastic dual in-line package; 20 leads (300 mil) 1991 Feb 08 10 SOT146-1 Philips Semiconductors Product specification Latch/flip–flop 74ALS373/74ALS374 SO20: plastic small outline package; 20 leads; body width 7.5 mm 1991 Feb 08 11 SOT163-1 Philips Semiconductors Product specification Latch/flip–flop 74ALS373/74ALS374 SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm 1991 Feb 08 12 SOT339-1 Philips Semiconductors Product specification Latch/flip–flop 74ALS373/74ALS374 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Copyright Philips Electronics North America Corporation 1997 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 1991 Feb 08 13