PHILIPS 74F395

Philips Semiconductors
Product specification
4-bit cascadable shift register (3-State)
FEATURES
74F395
PIN CONFIGURATION
• 4-bit parallel load shift register
• Independent 3-State buffer outputs, Q0–Q3
• Separate Qs output for serial expansion
• Asynchronous Master Reset
DESCRIPTION
The 74F395 is a 4-bit Shift Register with serial and parallel
synchronous operating modes and 3-State buffer outputs. The
shifting and loading operations are controlled by the state of the
Parallel Enable (PE) input. When PE is High, data is loaded from the
Parallel Data inputs (D0–D3) into the register synchronous with the
High-to-Low transition of the Clock input (CP). When PE is Low, the
data at the Serial Data input (Ds) is loaded into the Q0 flip-flop, and
the data in the register is shifted one bit to the right in the direction
(Q0Q1Q2Q3) synchronous with the negative clock transition.
The PE and Data inputs are fully edge-triggered and must be stable
one setup prior to the High-to-Low transition of the clock.
MR
1
16
VCC
Ds
2
15
Q0
D0
3
14
Q1
D1
4
13
Q2
D2
5
12
Q3
D3
6
11
Qs
PE
7
10
CP
GND
8
9
OE
SF00940
TYPE
TYPICAL fMAX
TYPICAL SUPPLY CURRENT
(TOTAL)
74F395
120MHz
32mA
ORDERING INFORMATION
The Master Reset (MR) is an asynchronous active-Low input. When
Low, the MR overrides the clock and all other inputs and clears the
register.
The 3-state output buffers are designed to drive heavily loaded
3-State buses, or large capacitive loads.
The active-Low Output Enable (OE) controls all four 3-State buffers
independent of the register operation. The data in the register
appears at the outputs when OE is Low. The outputs are in High
impedance “OFF” state, which means they will neither drive nor load
the bus when OE is High. The output from the last stage is brought
out separately. This output (Qs) is tied to the Serial Data input (Ds)
of the next register for serial expansion applications. The Qs output
is not affected by the 3-State buffer operation.
DESCRIPTION
COMMERCIAL RANGE
VCC = 5V ±10%, Tamb = 0°C to +70°C
16-pin plastic DIP
N74F395N
16-pin plastic SO
N74F395D
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
Data inputs
1.0/1.0
20µA/0.6mA
PINS
D0 – D3
DESCRIPTION
Ds
Serial data input
1.0/1.0
20µA/0.6mA
PE
Parallel Enable input
1.0/1.0
20µA/0.6mA
MR
Master Reset input (active Low)
1.0/1.0
20µA/0.6mA
OE
Output Enable input (active Low)
1.0/1.0
20µA/0.6mA
CP
Clock Pulse input (active falling edge)
1.0/1.0
20µA/0.6mA
Qs
Serial expansion output
50/33
1.0mA/20mA
Data outputs (3-State)
150/40
3.0mA/24mA
Q0–Q3
NOTE:
One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
1990 Oct 23
1
853–0370 00780
Philips Semiconductors
Product specification
4-bit cascadable shift register (3-State)
74F395
LOGIC SYMBOL
IEC/IEEE SYMBOL (IEEE/IEC)
2
Ds
7
PE
10
CP
3
4
D0
5
D1
1
6
D2
D3
EN4
7
M1[LOAD]
M2[SHIFT]
10
9
OE
1
MR
SRG4
R
9
Qs
Q0
Q1
Q2
Q3
15
14
13
12
11
2
C3/2
2,3D
3
1,3D
4
1,3D
15
4
14
4
5
13
6
12
11
VCC = Pin 16
GND = Pin 8
SF00941
SF00942
LOGIC DIAGRAM
OE
CP
MR
PE
Ds
D0
9
10
1
7
2
Q
CP
R
3
S
Q
15
Q0
CLR
Q
CP
D1
R
4
S
Q
14
Q1
CLR
Q
CP
D2
R
5
S
Q
13
Q2
CLR
Q
CP
D3
R
6
Q
S
12
Q3
11
Qs
CLR
VCC = Pin 16
GND = Pin 8
1990 Oct 23
SF00943
2
Philips Semiconductors
Product specification
4-bit cascadable shift register (3-State)
74F395
MODE SELECT–FUNCTION TABLE
MR
CP
PE
Ds
Dn
Q0
Q1
Q2
Q3
REGISTER
OPERATING
MODES
L
X
X
X
X
L
L
L
L
Reset (clear)
H
#
l
l
X
L
q0
q1
q2
H
#
l
h
X
H
q0
q1
q2
H
#
h
X
l
L
L
L
L
H
#
h
X
h
H
H
H
H
3-STATE BUFFER
OPERATING
MODES
INPUTS
OUTPUTS
H = High voltage level
h = High voltage level one set-up time prior to the High-to-Low
clock transition
L = Low voltage level
l = Low voltage level one set-up time prior to the High-to-Low
clock transition
qn = Lower case letters indicate the state of the referenced input
(or output) one set-up time prior to the High-to-Low clock
transition
X = Don’t care
Z = High impedance “OFF” state
# = High-to-Low clock transition
Shift right
Parallel load
INPUTS
OUTPUTS
OE
Qn (Register)
Q0, Q1, Q2, Q3
Qs
L
L
L
L
L
H
H
H
H
L
Z
L
H
H
Z
H
Read
Disable buffers
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
PARAMETER
RATING
UNIT
VCC
Supply voltage
–0.5 to +7.0
V
VIN
Input voltage
–0.5 to +7.0
V
IIN
Input current
VOUT
Voltage applied to output in High output state
IOUT
Current applied to output in Low output state
Tamb
Operating free-air temperature range
Tstg
Storage temperature range
–30 to +5
mA
–0.5 to +5.5
V
Qs
40
mA
Q0–Q3
48
mA
0 to +70
°C
–65 to +150
°C
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
UNIT
MIN
NOM
MAX
5.0
5.5
VCC
Supply voltage
4.5
VIH
High-level input voltage
2.0
VIL
Low-level input voltage
0.8
V
IIK
Input clamp current
–18
mA
Qs
–1
mA
IOH
High-level output current
Q0–Q3
–3
mA
Qs
20
mA
IOL
Low-level output current
Q0–Q3
24
mA
Tamb
Operating free-air temperature range
70
°C
1990 Oct 23
0
3
V
V
Philips Semiconductors
Product specification
4-bit cascadable shift register (3-State)
74F395
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
TEST CONDITIONS1
PARAMETER
Qs
VOH
High-level output voltage
Q0–Q3
IOH=–1mA
VCC = MIN,
VIL = MAX,
VIH=MIN
IOH =–3mA
LIMITS
MIN
TYP2
MAX
UNIT
±10%VCC
2.5
±5%VCC
2.7
±10%VCC
2.4
V
±5%VCC
2.7
V
V
3.4
V
±10%VCC
0.35
0.50
V
±5%VCC
0.35
0.50
V
–0.73
–1.2
V
VCC = MAX, VI = 7.0V
100
µA
High-level input current
VCC = MAX, VI = 2.7V
20
µA
IIL
Low-level input current
VCC = MAX, VI = 0.5V
–0.6
mA
IOZH
Off-state output current High
level of voltage applied
Q0–Q3
only
VCC = MAX, VO = 2.7V
50
µA
IOZL
Off-state output current Low
level of voltage applied
Q0–Q3
only
VCC = MAX, VO = 0.5V
–50
µA
IOS
Short-circuit output current3
–150
mA
VCC = MIN,
VIL = MAX,
VIH = MIN,
VOL
Low-level output voltage
IOL = MAX
VIK
Input clamp voltage
VCC = MIN, II = IIK
II
Input current at maximum input voltage
IIH
VCC = MAX
–60
ICCH
ICC
Supply current (total)
ICCL
VCC = MAX
ICCZ
MR=PE=Dn=Ds=4.5V,
OE=GND, CP=#
33
48
mA
MR=OE=Dn=Ds=GND,
PE=4.5V, CP=#
35
50
mA
MR=Dn=Ds=GND,
OE=4.5V
32
46
mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at VCC = 5V, Tamb = 25°C.
3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, IOS tests should be performed last.
1990 Oct 23
4
Philips Semiconductors
Product specification
4-bit cascadable shift register (3-State)
74F395
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
VCC = +5V
Tamb = +25°C
CL = 50pF, RL = 500Ω
TEST
CONDITION
MIN
TYP
VCC = +5V ± 10%
Tamb = 0°C to +70°C
CL = 50pF, RL = 500Ω
MAX
MIN
UNIT
MAX
fMAX
Maximum clock frequency
Waveform 1
105
120
MHz
tPLH
tPHL
Propagation delay
CP to Qn
Waveform 1
3.5
5.0
6.0
8.0
8.5
11.0
3.5
5.0
9.5
11.5
ns
tPLH
tPHL
Propagation delay
CP to Qs
Waveform 1
4.5
5.5
6.0
7.5
8.5
10.0
4.0
5.0
9.5
10.5
ns
tPHL
Propagation delay
MR to Qn
Waveform 2
5.0
7.5
10.0
5.0
10.5
ns
tPHL
Propagation delay
MR to Qs
Waveform 2
4.5
7.0
9.0
4.5
9.5
ns
tPZH
tPZL
Output Enable time
to High or Low level
Waveform 4
Waveform 5
4.0
3.5
6.5
6.0
9.0
8.0
4.0
3.5
10.0
8.5
ns
tPHZ
tPLZ
Output Disable time
from High or Low level
Waveform 4
Waveform 5
1.0
1.0
2.5
3.5
4.5
5.5
1.0
1.0
5.5
6.5
ns
AC SETUP REQUIREMENTS
LIMITS
SYMBOL
PARAMETER
VCC = +5V
Tamb = +25°C
CL = 50pF, RL = 500Ω
TEST
CONDITION
MIN
TYP
MAX
VCC = +5V ± 10%
Tamb = 0°C to +70°C
CL = 50pF, RL = 500Ω
MIN
UNIT
MAX
ts(H)
ts(L)
Setup time, High or Low
Dn to CP
Waveform 3
2.5
1.5
3.0
2.0
ns
th(H)
th(L)
Hold time, High or Low
Dn to CP
Waveform 3
1.5
1.5
1.5
1.5
ns
ts(H)
ts(L)
Setup time, High or Low
PE to CP
Waveform 3
6.5
6.0
7.0
6.5
ns
th(H)
th(L)
Hold time, High or Low
PE to CP
Waveform 3
0
0
0
0
ns
tW(H)
tW(L)
CP Pulse width
High or Low
Waveform 1
5.0
4.0
5.5
4.5
ns
tW(L)
MR Pulse width
Low
Waveform 2
2.5
3.0
ns
tREC
Recovery time
MR to CP
Waveform 2
6.0
7.0
ns
1990 Oct 23
5
Philips Semiconductors
Product specification
4-bit cascadable shift register (3-State)
74F395
AC WAVEFORMS
For all waveforms, VM = 1.5V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
1/fMAX
MR
CP
VM
VM
VM
tw(L)
VM
tw(L)
tREC
tw(H)
VM
CP
tPHL
tPLH
tPHL
Qn, Qs
VM
VM
VM
Qn, Qs
SF00944
SF00945
Waveform 1. Propagation Delay, Clock Input to Output,
Clock Widths, and Maximum Clock Frequency
Dn
Waveform 2. Master Reset Pulse Width, Master Reset to
Output Delay, and Master Reset to Clock Recovery Time
STABLE
VM
VM
OE
ts
ts
CP
VM
tPZH
STABLE
VM
VM
Ds
PE
VM
th
VM
VM
VM
ts
th
ts
VM
Qn
tPHZ
VOH -0.3V
VM
0V
th
SF00343
Waveform 4. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
VM
th
VM
OE
SF00946
VM
VM
tPZL
Waveform 3. Parallel Enable and
Data Setup Time and Hold Time
Qn
tPLZ
VM
VOL +0.3V
SF00344
Waveform 5. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
1990 Oct 23
6
Philips Semiconductors
Product specification
4-bit cascadable shift register (3-State)
74F395
TEST CIRCUIT AND WAVEFORMS
VCC
7.0V
VIN
RL
VOUT
PULSE
GENERATOR
tw
90%
NEGATIVE
PULSE
VM
CL
AMP (V)
VM
10%
D.U.T.
RT
90%
10%
tTHL (tf )
tTLH (tr )
tTLH (tr )
tTHL (tf )
0V
RL
AMP (V)
90%
90%
Test Circuit for 3-State Outputs and
Totem-Pole Output (Qs)
POSITIVE
PULSE
VM
VM
10%
10%
tw
0V
SWITCH POSITION
TEST
tPLZ
tPZL
All other
Input Pulse Definition
SWITCH
closed
closed
open
DEFINITIONS:
RL = Load resistor;
see AC electrical characteristics for value.
CL = Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
RT = Termination resistance should be equal to ZOUT of
pulse generators.
INPUT PULSE REQUIREMENTS
family
amplitude VM
74F
3.0V
1.5V
rep. rate
tw
tTLH
tTHL
1MHz
500ns
2.5ns
2.5ns
SF00957
1990 Oct 23
7