INTEGRATED CIRCUITS DATA SHEET 74LVC2G34 Dual buffer gate Product specification Supersedes data of 2003 Jul 25 2004 Sep 10 Philips Semiconductors Product specification Dual buffer gate 74LVC2G34 FEATURES DESCRIPTION • Wide supply voltage range from 1.65 V to 5.5 V The 74LVC2G34 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. • 5 V tolerant input/output for interfacing with 5 V logic • High noise immunity Inputs can be driven from either 3.3 V or 5 V devices. These feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment. • Complies with JEDEC standard: – JESD8-7 (1.65 V to 1.95 V) – JESD8-5 (2.3 V to 2.7 V) This device is fully specified for partial power-down applications using Ioff. The Ioff circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. – JESD8B/JESD36 (2.7 V to 3.6 V). • ESD protection: – HBM EIA/JESD22-A114-B exceeds 2000 V The 74LVC2G34 provides two buffers. – MM EIA/JESD22-A115-A exceeds 200 V. • ±24 mA output drive (VCC = 3.0 V) • CMOS low power consumption • Latch-up performance exceeds 250 mA • Direct interface with TTL levels • Multiple package options • Specified from −40 °C to +85 °C and −40 °C to +125 °C. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C. SYMBOL tPHL/tPLH PARAMETER propagation delay input nA to output nY CI input capacitance CPD power dissipation capacitance CONDITIONS UNIT VCC = 1.8 V; CL = 30 pF; RL = 1 kΩ 3.8 ns VCC = 2.5 V; CL = 30 pF; RL = 500 Ω 2.4 ns VCC = 2.7 V; CL = 50 pF; RL = 500 Ω 2.5 ns VCC = 3.3 V; CL = 50 pF; RL = 500 Ω 2.2 ns VCC = 5.0 V; CL = 50 pF; RL = 500 Ω 1.9 ns 2.5 pF 20 pF VCC = 3.3 V; notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; ∑(CL × VCC2 × fo) = sum of outputs. 2. The condition is VI = GND to VCC. 2004 Sep 10 TYPICAL 2 Philips Semiconductors Product specification Dual buffer gate 74LVC2G34 FUNCTION TABLE See note 1. INPUT OUTPUT nA nY L L H H Note 1. H = HIGH voltage level; L = LOW voltage level. ORDERING INFORMATION PACKAGE TYPE NUMBER TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE MARKING 74LVC2G34GW −40 °C to +125 °C 6 SC-88 plastic SOT363 YA 74LVC2G34GV −40 °C to +125 °C 6 SC-74 plastic SOT457 Y34 74LVC2G34GM −40 °C to +125 °C 6 XSON6 plastic SOT886 YA PINNING PIN SYMBOL DESCRIPTION 1 1A data input 2 GND ground (0 V) 3 2A data input 4 2Y data output 5 VCC supply voltage 6 1Y data output 34 1A 1 GND 2 2A 3 34 6 1Y 5 VCC 4 2Y 1A 1 6 1Y GND 2 5 VCC 2A 3 4 2Y 001aab676 001aab677 Transparent top view Fig.1 Pin configuration SC-88 and SC-74. 2004 Sep 10 Fig.2 Pin configuration XSON6. 3 Philips Semiconductors Product specification Dual buffer gate 74LVC2G34 handbook, halfpage 1 1A 1Y 6 3 2A 2Y 4 handbook, halfpage 1 1 6 1 3 4 MNB064 MNB063 Fig.3 Logic symbol. Fig.4 Logic symbol (IEEE/IEC). RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCC supply voltage 1.65 5.5 V VI input voltage 0 5.5 V VO output voltage Tamb operating ambient temperature tr, tf input rise and fall times active mode 0 VCC V VCC = 0 V; Power-down mode 0 5.5 V −40 +125 °C VCC = 1.65 V to 2.7 V 0 20 ns/V VCC = 2.7 V to 5.5 V 0 10 ns/V LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCC supply voltage −0.5 +6.5 V IIK input diode current VI < 0 V − −50 mA VI input voltage note 1 −0.5 +6.5 V IOK output diode current VO > VCC or VO < 0 V − ±50 mA VO output voltage active mode; notes 1 and 2 −0.5 VCC + 0.5 V Power-down mode; notes 1 and 2 −0.5 +6.5 V IO output source or sink current − ±50 mA ICC, IGND VCC or GND current − ±100 mA Tstg storage temperature −65 +150 °C Ptot power dissipation − 300 mW VO = 0 V to VCC Tamb = −40 °C to +125 °C Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. 2004 Sep 10 4 Philips Semiconductors Product specification Dual buffer gate 74LVC2G34 DC CHARACTERISTICS At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER MIN. TYP. MAX. UNIT VCC (V) OTHER Tamb = −40 °C to +85 °C; note 1 VIH VIL VOL VOH HIGH-level input voltage LOW-level input voltage 1.65 to 1.95 0.65 × VCC − − V 2.3 to 2.7 1.7 − − V 2.7 to 3.6 2.0 − − V 4.5 to 5.5 0.7 × VCC − − V 1.65 to 1.95 − − 0.35 × VCC V 2.3 to 2.7 − − 0.7 V 2.7 to 3.6 − − 0.8 V 4.5 to 5.5 − − 0.3 × VCC V LOW-level output voltage VI = VIH or VIL HIGH-level output voltage IO = 100 µA 1.65 to 5.5 − − 0.1 V IO = 4 mA 1.65 − − 0.45 V IO = 8 mA 2.3 − − 0.3 V IO = 12 mA 2.7 − − 0.4 V IO = 24 mA 3.0 − − 0.55 V IO = 32 mA 4.5 − − 0.55 V VI = VIH or VIL IO = −100 µA 1.65 to 5.5 VCC − 0.1 − − V IO = −4 mA 1.65 1.2 − − V IO = −8 mA 2.3 1.9 − − V IO = −12 mA 2.7 2.2 − − V IO = −24 mA 3.0 2.3 − − V IO = −32 mA 4.5 3.8 − − V ILI input leakage current VI = 5.5 V or GND 5.5 − ±0.1 ±5 µA Ioff power OFF leakage current VI or VO = 5.5 V 0 − ±0.1 ±10 µA ICC quiescent supply current VI = VCC or GND; IO = 0 A 5.5 − 0.1 10 µA ∆ICC additional quiescent supply current per pin 2.3 to 5.5 − 5 500 µA 2004 Sep 10 VI = VCC − 0.6 V; IO = 0 A 5 Philips Semiconductors Product specification Dual buffer gate 74LVC2G34 TEST CONDITIONS SYMBOL PARAMETER MIN. OTHER TYP. MAX. UNIT VCC (V) Tamb = −40 °C to +125 °C VIH VIL VOL VOH HIGH-level input voltage LOW-level input voltage 1.65 to 1.95 0.65 × VCC − − V 2.3 to 2.7 1.7 − − V 2.7 to 3.6 2.0 − − V 4.5 to 5.5 0.7 × VCC − − V 1.65 to 1.95 − − 0.35 × VCC V 2.3 to 2.7 − − 0.7 V 2.7 to 3.6 − − 0.8 V 4.5 to 5.5 − − 0.3 × VCC V IO = 100 µA 1.65 to 5.5 − − 0.1 V IO = 4 mA 1.65 − − 0.70 V IO = 8 mA 2.3 − − 0.45 V IO = 12 mA 2.7 − − 0.60 V IO = 24 mA 3.0 − − 0.80 V IO = 32 mA 4.5 − − 0.80 V IO = −100 µA 1.65 to 5.5 VCC − 0.1 − − V IO = −4 mA 1.65 0.95 − − V IO = −8 mA 2.3 1.7 − − V IO = −12 mA 2.7 1.9 − − V IO = −24 mA 3.0 2.0 − − V LOW-level output voltage VI = VIH or VIL HIGH-level output voltage VI = VIH or VIL IO = −32 mA 4.5 3.4 − − V ILI input leakage current VI = 5.5 V or GND 5.5 − − ±20 µA Ioff power OFF leakage current VI or VO = 5.5 V 0 − − ±20 µA ICC quiescent supply current VI = VCC or GND; IO = 0 A 5.5 − − 40 µA ∆ICC additional quiescent supply current per pin 2.3 to 5.5 − − 5000 µA VI = VCC − 0.6 V; IO = 0 A Note 1. All typical values are measured at VCC = 3.3 V and Tamb = 25 °C. 2004 Sep 10 6 Philips Semiconductors Product specification Dual buffer gate 74LVC2G34 AC CHARACTERISTICS GND = 0 V. TEST CONDITIONS SYMBOL PARAMETER MIN. WAVEFORMS TYP. MAX. UNIT VCC (V) Tamb = −40 °C to +85 °C; note 1 tPHL/tPLH propagation delay input nA to output nY see Figs 5 and 6 1.65 to 1.95 1.0 3.8 8.6 ns 2.3 to 2.7 0.5 2.4 4.4 ns 2.7 0.5 2.5 5.0 ns 3.0 to 3.6 0.5 2.2 4.1 ns 4.5 to 5.5 0.5 1.9 3.2 ns Tamb = −40 °C to +125 °C tPHL/tPLH propagation delay input nA to output nY see Figs 5 and 6 1.65 to 1.95 1.0 − 10.8 ns 2.3 to 2.7 0.5 − 5.5 ns 2.7 0.5 − 6.3 ns 3.0 to 3.6 0.5 − 5.1 ns 4.5 to 5.5 0.5 − 4.0 ns Note 1. All typical values are measured at VCC = 3.3 V and Tamb = 25 °C. AC WAVEFORMS VI nA input VM VM GND tPLH tPHL VOH VM nY output VM VOL mnb072 INPUT VCC VM 1.65 V to 1.95 V 0.5 × VCC VCC ≤ 2.0 ns 2.3 V to 2.7 V 0.5 × VCC VCC ≤ 2.0 ns 2.7 V 1.5 V 2.7 V ≤ 2.5 ns 3.0 V to 3.6 V 1.5 V 2.7 V ≤ 2.5 ns 4.5 V to 5.5 V 0.5 × VCC VCC ≤ 2.5 ns VI tr = tf VOL and VOH are typical output voltage drop that occur with the output load. Fig.5 Input nA to output nY propagation delay times. 2004 Sep 10 7 Philips Semiconductors Product specification Dual buffer gate 74LVC2G34 VEXT VCC PULSE GENERATOR VI RL VO D.U.T. CL RT RL mna616 VCC VI CL RL VEXT tPLH/tPHL 1.65 V to 1.95 V VCC 30 pF 1 kΩ open 2.3 V to 2.7 V VCC 30 pF 500 Ω open 2.7 V 2.7 V 50 pF 500 Ω open 3.0 V to 3.6 V 2.7 V 50 pF 500 Ω open 4.5 V to 5.5 V VCC 50 pF 500 Ω open Definitions for test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. Fig.6 Load circuitry for switching times. 2004 Sep 10 8 Philips Semiconductors Product specification Dual buffer gate 74LVC2G34 PACKAGE OUTLINES Plastic surface mounted package; 6 leads SOT363 D E B y X A HE 6 v M A 4 5 Q pin 1 index A A1 1 2 e1 3 bp c Lp w M B e detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp c D E e e1 HE Lp Q v w y mm 1.1 0.8 0.1 0.30 0.20 0.25 0.10 2.2 1.8 1.35 1.15 1.3 0.65 2.2 2.0 0.45 0.15 0.25 0.15 0.2 0.2 0.1 OUTLINE VERSION SOT363 2004 Sep 10 REFERENCES IEC JEDEC EIAJ SC-88 9 EUROPEAN PROJECTION ISSUE DATE 97-02-28 Philips Semiconductors Product specification Dual buffer gate 74LVC2G34 Plastic surface mounted package; 6 leads SOT457 D E B y A HE 6 X v M A 4 5 Q pin 1 index A A1 c 1 2 3 Lp bp e w M B detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 bp c D E e HE Lp Q v w y mm 1.1 0.9 0.1 0.013 0.40 0.25 0.26 0.10 3.1 2.7 1.7 1.3 0.95 3.0 2.5 0.6 0.2 0.33 0.23 0.2 0.2 0.1 OUTLINE VERSION SOT457 2004 Sep 10 REFERENCES IEC JEDEC EIAJ SC-74 10 EUROPEAN PROJECTION ISSUE DATE 97-02-28 01-05-04 Philips Semiconductors Product specification Dual buffer gate 74LVC2G34 XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm SOT886 b 1 2 3 4× (2) L L1 e 6 5 e1 4 e1 6× A (2) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A (1) max A1 max b D E e e1 L L1 mm 0.5 0.04 0.25 0.17 1.5 1.4 1.05 0.95 0.6 0.5 0.35 0.27 0.40 0.32 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT886 2004 Sep 10 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 04-07-15 04-07-22 MO-252 11 Philips Semiconductors Product specification Dual buffer gate 74LVC2G34 DATA SHEET STATUS LEVEL DATA SHEET STATUS(1) PRODUCT STATUS(2)(3) Development DEFINITION I Objective data II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Production This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2004 Sep 10 12 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: [email protected]. SCA76 © Koninklijke Philips Electronics N.V. 2004 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R20/02/pp13 Date of release: 2004 Sep 10 Document order number: 9397 750 13784