INTEGRATED CIRCUITS 74ABT16899 74ABTH16899 18-bit latched transceiver with 16-bit parity generator/checker (3-State) Product specification Supersedes data of 1997 Mar 28 IC23 Data Handbook 1998 Feb 25 Philips Semiconductors Product specification 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 74ABT16899 74ABTH16899 Parity error checking of the A and B bus latches is continuously provided with ERRA and ERRB, even with both buses in 3-State. FEATURES • Symmetrical (A and B bus functions are identical) • Selectable generate parity or ”feed-through” parity for A-to-B and The 74ABT/H16899 features independent latch enables for the A and B bus latches, a select pin for ODD/EVEN parity, and separate error signal output pins for checking parity. B-to-A directions • Independent transparent latches for A-to-B and B-to-A directions • Selectable ODD/EVEN parity • Continuously checks parity of both A bus and B bus latches as FUNCTIONAL DESCRIPTION The 74ABT/H16899 has three principal modes of operation which are outlined below. All modes apply to both the A-to-B and B-to-A directions. ERRA and ERRB • Open-collector ERR output • Ability to simultaneously generate and check parity • Can simultaneously read/latch A and B bus data • Output capability: +64 mA/–32mA • Latch-up protection exceeds 500mA per Jedec Std 17 • ESD protection exceeds 2000 V per MIL STD 883 Method 3015 Transparent latch, Generate parity, Check A and B bus parity: Bus A (B) communicates to Bus B (A), parity is generated and passed on to the B (A) Bus as BPAR (APAR). If LEA and LEB are High and the Mode Select (SEL) is Low, the parity generated from A0-A7 and B0-B7 can be checked and monitored by ERRA and ERRB. (Fault detection on both input and output buses.) Transparent latch, Feed-through parity, Check A and B bus parity: Bus A (B) communicates to Bus B (A) in a feed-through mode if SEL is High. Parity is still generated and checked as ERRA and ERRB and can be used as an interrupt to signal a data/parity bit error to the CPU. and 200 V per Machine Model • Power up 3-State • Power-up reset • Live insertion/extraction permitted • Bus-hold data inputs eliminate the need for external pull-up Latched input, Generate/Feed-through parity, Check A (and B) bus parity: Independent latch enables (LEA and LEB) allow other permutations of: resistors to hold unused inputs DESCRIPTION • Transparent latch / 1 bus latched / both buses latched • Feed-through parity / generate parity • Check in bus parity / check out bus parity / check in and out bus The 74ABT/H16899 is a 16-bit to 16-bit parity transceiver with separate transparent latches for the A bus and B bus. Either bus can generate or check parity. The parity bit can be fed-through with no change or the generated parity can be substituted with the SEL input. parity QUICK REFERENCE DATA SYMBOL CONDITIONS Tamb = 25°C; GND = 0V PARAMETER TYPICAL UNIT tPLH tPHL Propagation delay An to Bn or Bn to An CL = 50pF; VCC = 5V 2.7 ns tPLH tPHL Propagation delay An to ERRA CL = 50pF; VCC = 5V 5.0 ns CIN Input capacitance VI = 0V or VCC 4 pF CI/O Output capacitance Outputs disabled; VO = 0V or VCC 7 pF Outputs disabled; VCC =5.5V 500 µA Output Low; VCC = 5.5V 10.5 mA ICCZ Quiescent supply current ICCL ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 56-Pin Plastic SSOP Type III –40°C to +85°C 74ABT16899 DL BT16899 DL SOT371-1 56-Pin Plastic TSSOP Type II –40°C to +85°C 74ABT16899 DGG BT16899 DGG SOT364-1 56-Pin Plastic SSOP Type III –40°C to +85°C 74ABTH16899 DL BH16899 DL SOT371-1 56-Pin Plastic TSSOP Type II –40°C to +85°C 74ABTH16899 DGG BH16899 DGG SOT364-1 1998 Feb 25 2 853-1960 19018 Philips Semiconductors Product specification 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 74ABT16899 74ABTH16899 PIN CONFIGURATION ODD/EVEN 1 56 SEL OEA 2 55 LEA 1B0 1A0 3 54 GND 4 53 GND 1A1 5 52 1B1 1B2 1A2 6 51 1A3 7 50 1B3 1A4 8 49 1B4 VCC 9 48 VCC 1A5 10 47 1B5 1A6 11 46 1B6 1A7 12 45 1B7 1APAR 13 44 1BPAR 1ERRA 14 43 1ERRB GND 15 42 GND 2ERRA 16 41 2ERRB 2APAR 17 40 2BPAR 2A7 18 39 2B7 2A6 19 38 2B6 2A5 20 37 2B5 VCC 21 36 VCC 2A4 22 35 2B4 2A3 23 34 2B3 2A2 24 33 2B2 2A1 25 32 2B1 GND 26 31 GND 2A0 27 30 2B0 LEB 28 29 OEB SH00082 PIN DESCRIPTION SYMBOL PIN NUMBER 1A0 - 1A7 2A0 - 2A7 3, 5, 6, 7, 8, 10, 11, 12 27, 25, 24, 23, 22, 20, 19, 18 Latched A bus 3-State inputs/outputs 1B0 - 1B7 2B0 - 2B7 54, 52, 51, 50, 49, 47, 46, 45 30, 32, 33, 34, 35, 37, 38, 39 Latched B bus 3-State inputs/outputs 1APAR 2APAR 13, 17 A bus parity 3-State input 1BPAR 2BPAR 44, 40 B bus parity 3-State input ODD/EVEN 1 OEA, OEB 2, 29 SEL 56 NAME AND FUNCTION Parity select input (Low for EVEN parity) Output enable inputs (gate A to B, B to A) Mode select input (Low for generate) LEA, LEB 55, 28 Latch enable inputs (transparent High) 1ERRA, 1ERRB 2ERRA, 2ERRB 14, 43, 16, 41 Error signal outputs (active-Low) GND 4, 15, 26, 31, 42, 53 VCC 9, 21, 36, 48 1998 Feb 25 Ground (0V) Positive supply voltage 3 Philips Semiconductors Product specification 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 74ABT16899 74ABTH16899 LOGIC SYMBOL 3 5 6 7 8 10 11 12 13 27 1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1APAR 25 24 23 22 20 19 18 17 2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2APAR 55 LEA 55 LEA 28 LEB 28 LEB 56 SEL 14 56 SEL 2ERRA 16 43 1 ODD/EVEN 2ERRB 41 1ERRA 1 ODD/EVEN 2 OEA 2 OEA 29 OEB 29 OEB 1ERRB 1B0 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1BPAR 54 52 51 50 49 47 46 45 2B0 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2BPAR 44 30 32 33 34 35 37 38 39 40 SH00083 PARITY AND ERROR FUNCTION TABLE INPUTS SEL H H xPAR (A or B) Σ of High Inputs xPAR (B or A) ERRt ERRr* H Even Odd H H H L H L L L L H L H H H L Even Odd H L H Even Odd H H L H L H L L H L H L H L L Even Odd L H H Even Odd H L H L H H H L L H H H L H L Even Odd L L H Even Odd L H L H H H L Even Odd L H H L H H L H L t r * ODD/EVEN OUTPUTS L = High voltage level = Low voltage level = Transmit–if the data path is from A→B then ERRt is ERRA = Receive–if the data path is from A→B then ERRr is ERRB Blocked if latch is not transparent 1998 Feb 25 4 PARITY MODES Odd Mode Feed-through/check parity Even Mode Odd Mode Even Mode Generate parity Philips Semiconductors Product specification 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 74ABT16899 74ABTH16899 BLOCK DIAGRAM OE 9–bit Transparent Latch LEA OEB 9–bit Output Buffer LE A0 A1 1 mux Parity Generator B0 B1 0 A2 A3 B2 B3 B4 A4 A5 B5 B6 A6 A7 B7 BPAR APAR 9–bit Transparent Latch 9–bit Output Buffer OEA OE LE 1 mux Parity Generator 0 LEB ERRA SEL ERRB (1 of 2 parity blocks) ODD/ EVEN SH00084 FUNCTION TABLE INPUTS OPERATING MODE OEB OEA SEL LEA LEB H H X X X 3-State A bus and B bus (input A & B simultaneously) H L L L H B → A, transparent B latch, generate parity from B0 - B7, check B bus parity H L L H H B → A, transparent A & B latch, generate parity from B0 - B7, check A & B bus parity H L L X L B → A, B bus latched, generate parity from latched B0 - B7 data, check B bus parity H L H X H B → A, transparent B latch, parity feed-through, check B bus parity H L H H H B → A, transparent A & B latch, parity feed-through, check A & B bus parity L H L H X A → B, transparent A latch, generate parity from A0 - A7, check A bus parity L H L H H A → B, transparent A & B latch, generate parity from A0 - A7, check A & B bus parity L H L L X A → B, A bus latched, generate parity from latched A0 - A7 data, check A bus parity L H H H L A → B, transparent A latch, parity feed-through, check A bus parity L H H H H A → B, transparent A & B latch, parity feed-through, check A & B bus parity L L X X X Output to A bus and B bus (NOT ALLOWED) H = High voltage level L = Low voltage level X = Don’t care 1998 Feb 25 5 Philips Semiconductors Product specification 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 74ABT16899 74ABTH16899 ABSOLUTE MAXIMUM RATINGS1, 2 PARAMETER SYMBOL VCC IIK CONDITIONS RATING UNIT –0.5 to +7.0 V –18 mA –1.2 to +7.0 V VO < 0 –50 mA output in Off or High state –0.5 to +5.5 V output in Low state 128 output in High state –64 DC supply voltage DC input diode current VI < 0 voltage3 VI DC input IOK DC output diode current voltage3 VOUT DC output IOUT O DC output current Tstg Storage temperature range mA –65 to 150 °C NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 1505C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER LIMITS DC supply voltage UNIT Min Max 4.5 5.5 V 0 VCC V VI Input voltage VIH High-level input voltage VIL Low-level Input voltage 0.8 V IOH High-level output current –32 mA IOL Low-level output current 64 mA 0 5 ns/V –40 +85 °C ∆t/∆v Input transition rise or fall rate Tamb Operating free-air temperature range 1998 Feb 25 2.0 6 V Philips Semiconductors Product specification 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 74ABT16899 74ABTH16899 DC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITIONS Min VIK VOH Input clamp voltage High-level output voltage Tamb = –40°C to +85°C Tamb = +25°C VCC = 4.5V; IIK = –18mA Typ Max –0.7 –1.2 Min UNIT Max –1.2 V VCC = 4.5V; IOH = –3mA; VI = VIL or VIH 2.5 3.1 2.5 V VCC = 5.0V; IOH = –3mA; VI = VIL or VIH 3.0 3.6 3.0 V VCC = 4.5V; IOH = –32mA; VI = VIL or VIH 2.0 2.7 2.0 V VOL Low-level output voltage VCC = 4.5V; IOL = 64mA; VI = VIL or VIH 0.36 0.55 0.55 V VRST Power-up output low voltage3 VCC = 5.5V; IO = 1mA; VI = GND or VCC 0.13 0.55 0.55 V Input leakage Control pins VCC = 5.5V; VI = GND or 5.5V ±0.2 ±1.0 ±1.0 µA current Data pins VCC = 5.5V; VI = GND or 5.5V ±1.0 ±100 ±100 µA II IHOLD Bushold current A or B inputs5 74ABTH16899 VCC = 4.5V; VI = 0.8V 75 75 VCC = 4.5V; VI = 2.0V –75 –75 VCC = 5.5V; VI = 0 to 5.5V ±500 µA Power-off leakage current VCC = 0.0V; VO or VI ≤ 4.5V ±2.0 ±100 ±100 µA Power-up/down 3-State output current4 VCC = 2.1V; VO = 0.5V; VI = GND or VCC ±5.0 ±50 ±50 µA IIH + IOZH 3-State output High current VCC = 5.5V; VO = 2.7V; VI = VIL or VIH 2.0 50 50 µA IIL + IOZL 3-State output Low current VCC = 5.5V; VO = 0.5V; VI = VIL or VIH –2.0 –50 –50 µA Output High leakage current VCC = 5.5V; VO = 5.5V; VI = GND or VCC 2.0 50 50 µA –100 –180 –180 mA VCC = 5.5V; Outputs High, VI = GND or VCC 0.5 1 1 mA VCC = 5.5V; Outputs Low, VI = GND or VCC 10.5 19 19 mA VCC = 5.5V; Outputs 3-State; VI = GND or VCC 0.5 1 1 mA VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND 0.2 1.5 1.5 mA IOFF IPU/IPD ICEX IO Output current1 ICCH ICCL Quiescent supply current ICCZ ∆ICC Additional supply current per input pin2 VCC = 5.5V; VO = 2.5V –50 –50 NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V. 3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 4. This parameter is valid for any VCC between 0V and 2.1V, with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V ± 10%, a transition time of up to 100µsec is permitted. 5. This is the bus hold overdrive current required to force the input to the opposite logic state. 1998 Feb 25 7 Philips Semiconductors Product specification 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 74ABT16899 74ABTH16899 AC CHARACTERISTICS GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER Tamb = +25oC VCC = +5.0V CL = 50pF RL = 500Ω WAVEFORM Tamb = –40 to +85oC VCC = +5.0V ±10% CL = 50pF RL = 500Ω Min Typ Max Min Max UNIT tPLH tPHL Propagation delay An to Bn or Bn to An 1 1.0 1.0 2.7 2.2 4.5 3.5 1.0 1.0 5.5 6.9 ns tPLH tPHL Propagation delay An to BPAR or Bn to APAR 2 2.5 2.5 4.9 5.0 7.2 7.4 2.5 2.5 8.8 8.7 ns tPLH tPHL Propagation delay An to ERRA or Bn to ERRB 3 2.8 2.8 5.0 4.9 9.3 8.0 2.8 2.8 11.0 10.2 ns tPLH tPHL Propagation delay APAR to BPAR or BPAR to APAR 1 1.5 1.5 3.1 2.5 3.9 3.1 1.5 1.5 4.8 3.9 ns tPLH tPHL Propagation delay APAR to ERRA or BPAR to ERRB 6 1.0 1.0 2.5 2.5 3.3 3.3 1.0 1.0 4.3 3.9 ns tPLH tPHL Propagation delay ODD/EVEN to APAR or BPAR 5 2.5 2.5 4.1 3.9 5.1 5.0 2.5 2.5 6.1 5.7 ns tPLH tPHL Propagation delay ODD/EVEN to ERRA or ERRB 4 2.5 2.5 4.1 4.0 6.1 5.5 2.5 2.5 7.1 6.6 ns tPLH tPHL Propagation delay SEL to APAR or BPAR 8 1.5 1.5 3.1 2.6 4.0 3.4 1.5 1.5 5.0 4.2 ns tPLH tPHL Propagation delay SEL to ERRA or ERRB 8 2.5 2.5 5.0 4.4 7.5 5.9 2.5 2.5 8.3 7.1 ns tPLH tPHL Propagation delay LEA to Bn or LEB to An 9 1.0 1.0 3.1 2.8 4.2 4.3 1.0 1.0 5.2 4.7 ns tPLH tPHL Propagation delay LEA to BPAR or LEB to APAR 9 2.8 2.8 5.5 5.1 8.0 7.7 2.8 2.8 9.7 9.1 ns tPLH tPHL Propagation delay LEA to ERRA or LEB to ERRB 7 1.1 1.2 5.4 5.8 8.0 8.0 1.1 1.2 9.2 9.6 ns tPZH tPZL Output enable time OEA to An, APAR or OEB to Bn, BPAR 11, 12 1.0 1.0 2.6 2.3 3.6 3.2 1.0 1.0 5.1 4.5 ns tPHZ tPLZ Output disable time OEA to An, APAR or OEB to Bn, BPAR 11, 12 2.5 1.5 3.9 2.8 5.6 4.1 2.5 1.5 6.0 4.4 ns AC SETUP REQUIREMENTS GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500Ω LIMITS +25oC SYMBOL PARAMETER Tamb = –40 to +85oC VCC = +5.0V ±10% CL = 50pF RL = 500Ω UNIT Min Typ Min 10 1.5 1.0 0.3 –0.1 1.5 1.0 ns Hold time, High or Low An, APAR to LEA or Bn, BPAR to LEB 10 1.5 1.0 0.1 –0.2 1.5 1.0 ns Pulse width, High LEA or LEB 10 3.0 1.0 3.0 ns ts(H) ts(L) Setup time, High or Low An, APAR to LEA or Bn, BPAR to LEB th(H) th(L) tw(H) 1998 Feb 25 WAVEFORM Tamb = VCC = +5.0V CL = 50pF RL = 500Ω 8 Philips Semiconductors Product specification 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 74ABT16899 74ABTH16899 AC WAVEFORMS VM = 1.5V, VIN = GND to 3.0V 1 SEL An, APAR (Bn, BPAR) INPUT VM VM tPLH tPHL Bn, BPAR (An, APAR) VM OUTPUT VM SA00293 Waveform 1. Propagation Delay, An to Bn, Bn to An, APAR to BPAR, BPAR to APAR SEL 0 ODD/EVEN 0 LEA (LEB) An (Bn) 1 ODD PARITY EVEN PARITY VM VM tPHL ODD PARITY INPUT tPLH BPAR (APAR) VM VM OUTPUT NOTE: Only even parity mode is shown, odd parity mode would be with ODD/EVEN = 1 SA00294 Waveform 2. Propagation Delay, An to BPAR or Bn to APAR ODD/EVEN 0 APAR (BPAR) 0 LEA (LEB) SEL An (Bn) 1 ODD PARITY EVEN PARITY VM tPLH VM ODD PARITY INPUT tPHL ERRA (ERRB) VM VM OUTPUT NOTE: Only even parity mode is shown, odd parity mode would be with ODD/EVEN = 1 SA00295 Waveform 3. Propagation Delay, An to ERRA or Bn to ERRB 1998 Feb 25 9 Philips Semiconductors Product specification 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 74ABT16899 74ABTH16899 1 APAR (BPAR) An (Bn) EVEN PARITY INPUT INPUT ODD/EVEN VM VM tPLH ERRA (ERRB) tPHL VM OUTPUT VM NOTE: Only even parity mode is shown, odd parity mode would cause inverted output SA00296 Waveform 4. Propagation Delay, ODD/EVEN to ERRA or ODD/EVEN to ERRB SEL 0 APAR (BPAR) 0 An (Bn) ODD/EVEN EVEN PARITY VM INPUT VM tPLH BPAR (APAR) INPUT tPHL VM VM OUTPUT NOTE: Only even parity mode is shown, odd parity mode would cause inverted output SA00297 Waveform 5. Propagation Delay, ODD/EVEN to APAR or ODD/EVEN to BPAR 1998 Feb 25 10 Philips Semiconductors Product specification 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 74ABT16899 74ABTH16899 ODD/EVEN 0 An (Bn) EVEN PARITY APAR (BPAR) VM INPUT VM tPLH ERRA (ERRB) INPUT tPHL VM OUTPUT VM NOTE: Only even parity mode is shown with even parity. Odd parity mode would cause inverted output and odd parity mode would be with ODD/EVEN = 1 SA00298 Waveform 6. Propagation Delay, APAR to ERRA or BPAR to ERRB 1 ODD/EVEN APAR (BPAR) 0 An (Bn) LEA (LEB) EVEN PARITY ODD PARITY VM EVEN PARITY INPUT VM tPHL tPLH ERRA (ERRB) INPUT VM VM OUTPUT NOTE: Only odd parity mode is shown. Even parity mode would be with ODD/EVEN = o SA00299 Waveform 7. Propagation Delay, LEA to ERRA or LEB to ERRB 1998 Feb 25 11 Philips Semiconductors Product specification 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 74ABT16899 74ABTH16899 1 ODD/EVEN APAR (BPAR) 0 An (Bn) EVEN PARITY SEL VM INPUT INPUT VM tPHL tPLH BPAR (APAR) VM OUTPUT VM NOTE: Only even parity mode is shown with even parity. Odd parity mode would cause inverted output and odd parity mode would be with ODD/EVEN = 1 SA00300 Waveform 8. Propagation Delay, SEL to BPAR or SEL to APAR 1 SEL APAR, An] (BPAR, Bn) INPUT LEA (LEB) VM INPUT VM tPHL tPLH Bn, BPAR (An, APAR) VM OUTPUT VM SA00301 Waveform 9. Propagation Delay, LEA to BPAR or LEB to APAR, LEA to Bn or LEB to An ÉÉÉ ÉÉÉ ÉÉÉ APAR, BPAR, An, Bn VM ÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉ VM ts(H) VM th(H) VM ts(L) th(L) LEA, LEB VM VM tw(H) VM The shaded areas indicate when the input is permitted to change for predictable output performance. SA00302 Waveform 10. Data Setup and Hold Times, Pulse Width High 1998 Feb 25 12 Philips Semiconductors Product specification 18-bit latched transceiver with 16-bit parity generator/checker (3-State) OEA, OEB 74ABT16899 74ABTH16899 VM VM tPZH tPHZ An, APAR, Bn, BPAR VOH –0.3V VM 0V SA00303 Waveform 11. 3-State Output Enable Time to High Level and Output Disable Time from High Level OEA, OEB VM VM tPZL An, APAR, Bn, BPAR tPLZ VM VOL +0.3V SA00304 Waveform 12. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level TEST CIRCUIT AND WAVEFORM VCC VX VIN RX VOUT PULSE GENERATOR NEGATIVE PULSE 90% VM CL AMP (V) VM 10% D.U.T. RT tW 90% 10% tTHL (tf ) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0V RL AMP (V) 90% 90% Test Circuit for Open Collector Outputs POSITIVE PULSE VM VM 10% SWITCH POSITION TEST tPLZ tPZL All other SWITCH closed closed open RT = Termination resistance should be equal to ZOUT of pulse generators. 0V Input Pulse Definition DEFINITIONS: RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. 10% tW LOAD VALUES OUTPUT R X VX ERROR 100 Ω VCC All other 500 Ω 7.0V INPUT PULSE REQUIREMENTS FAMILY 74ABT/H16 Amplitude Rep. Rate tw tR tF 3.0V 1MHz 500ns 2.5ns 2.5ns SH00009 1998 Feb 25 13 Philips Semiconductors Product specification 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 74ABT16899 74ABTH16899 SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm 1998 Feb 25 14 SOT371-1 Philips Semiconductors Product specification 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 74ABT16899 74ABTH16899 TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm 1998 Feb 25 15 SOT364-1 Philips Semiconductors Product specification 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 74ABT16899 74ABTH16899 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: yyyy mmm dd 16 Date of release: 05-96 9397-750-03507