INTEGRATED CIRCUITS DATA SHEET SAA7102; SAA7103 Digital video encoder Product specification File under Integrated Circuits, IC22 2001 Sep 25 Philips Semiconductors Product specification Digital video encoder SAA7102; SAA7103 CONTENTS 12 APPLICATION INFORMATION 1 FEATURES 12.1 12.2 Analog output voltages Suggestions for a board layout 2 GENERAL DESCRIPTION 13 PACKAGE OUTLINES 3 ORDERING INFORMATION 14 SOLDERING 4 QUICK REFERENCE DATA 14.1 5 BLOCK DIAGRAM 6 PINNING 7 FUNCTIONAL DESCRIPTION 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 7.20 7.21 7.22 Reset conditions Input formatter RGB LUT Cursor insertion RGB Y-CB-CR matrix Horizontal scaler Vertical scaler and anti-flicker filter FIFO Border generator Oscillator and Discrete Time Oscillator (DTO) Low-pass Clock Generation Circuit (CGC) Encoder RGB processor Triple DAC Timing generator I2C-bus interface Programming the SAA7102; SAA7103 Input levels and formats Bit allocation map I2C-bus format Slave receiver Slave transmitter Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods 8 BOUNDARY SCAN TEST 8.1 8.2 Initialization of boundary scan circuit Device identification codes 9 LIMITING VALUES 10 THERMAL CHARACTERISTICS 11 CHARACTERISTICS 11.1 Teletext timing 2001 Sep 25 14.2 14.3 14.4 14.5 2 15 DATA SHEET STATUS 16 DEFINITIONS 17 DISCLAIMERS 18 PURCHASE OF PHILIPS I2C COMPONENTS Philips Semiconductors Product specification Digital video encoder 1 SAA7102; SAA7103 FEATURES • Digital PAL/NTSC encoder with integrated high quality scaler and anti-flicker filter for TV output from a PC • 27 MHz crystal-stable subcarrier generation • Maximum graphics pixel clock 45 MHz at double edged clocking, synthesized on-chip or from external source • Joint Test Action Group (JTAG) boundary scan test • Up to 800 × 600 graphics data at 60 Hz or 50 Hz with programmable underscan range • Monolithic CMOS 3.3 V device, 5 V tolerant I/Os • Three Digital-to-Analog Converters (DACs) at 27 MHz sample rate for CVBS (BLUE, CB), VBS (GREEN, CVBS) and C (RED, CR) (signals in parenthesis are optional); all at 10-bit resolution • Same footprint as SAA7108E; SAA7109E. • QFP44 and BGA156 packages 2 • Non-interlaced CB-Y-CR or RGB input at maximum 4 : 4 : 4 sampling The SAA7102; SAA7103 is used to encode PC graphics data at maximum 800 × 600 resolution to PAL (50 Hz) or NTSC (60 Hz) video signals. A programmable scaler and interlacer ensures properly sized and flicker-free TV display as CVBS or S-video output. • Downscaling from 1 : 1 to 1 : 2 and up to 20% upscaling • Optional interlaced CB-Y-CR input Digital Versatile Disk (DVD) Alternatively, the three Digital-to-Analog Converters (DACs) can output RGB signals together with a TTL composite sync to feed SCART connectors. • Optional non-interlaced RGB output to drive second VGA monitor (bypass mode, maximum 45 MHz) • 3 × 256 bytes RGB Look-Up Table (LUT) When the scaler/interlacer is bypassed, a second VGA monitor can be connected to the RGB outputs and separate H and V-syncs as well, thereby serving as an auxiliary monitor at maximum 800 × 600 resolution/60 Hz (PIXCLK < 45 MHz). • Support for hardware cursor • Programmable border colour of underscan area • On-chip 27 MHz crystal oscillator (3rd-harmonic or fundamental 27 MHz crystal) • Fast I2C-bus control port (400 kHz) The device includes a sync/clock generator and on-chip DACs. • Encoder can be master or slave • Programmable horizontal and vertical input synchronization phase • Programmable horizontal sync output phase • Internal Colour Bar Generator (CBG) • Optional support of various Vertical Blanking Interval (VBI) data insertion • Macrovision Pay-per-View copy protection system rev. 7.01 and rev. 6.1 as option; this applies to SAA7102 only. The device is protected by USA patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. Use of the Macrovision anti-copy process in the device is licensed for non-commercial home use only. Reverse engineering or disassembly is prohibited. Please contact your nearest Philips Semiconductors sales office for more information. • Power-save modes 2001 Sep 25 GENERAL DESCRIPTION 3 Philips Semiconductors Product specification Digital video encoder 3 SAA7102; SAA7103 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME SAA7102E BGA156 SAA7103E SAA7102H QFP44 SAA7103H 4 DESCRIPTION VERSION plastic ball grid array package; 156 balls; body 15 × 15 × 1.15 mm SOT472-1 plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 × 10 × 1.75 mm SOT307-2 QUICK REFERENCE DATA SYMBOL PARAMETER MIN. TYP. MAX. UNIT VDDA analog supply voltage 3.15 3.3 3.45 V VDDD digital supply voltage 3.0 3.3 3.6 V IDDA analog supply current 1 110 140 mA IDDD digital supply current 1 70 90 mA Vi input signal voltage levels TTL compatible Vo(p-p) analog CVBS output signal voltage for a 100/100 colour bar at 75/2 Ω load (peak-to-peak value) − 1.23 − V RL load resistance − 37.5 − Ω ILElf(DAC) low frequency integral linearity error of DACs − − ±3 LSB DLElf(DAC) low frequency differential linearity error of DACs − − ±1 LSB Tamb ambient temperature 0 − 70 °C 2001 Sep 25 4 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... PIXCLKI 15 40 39 36 33 29 32 31 TDO TMS TCLK 38 37 7 8 6 RGB TO Y-CB-CR INPUT FORMATTER RGB LUT (OR BYPASS) CURSOR INSERTION DECIMATOR 4 : 4 : 4 to 4 : 2 : 2 (OR BYPASS) HORIZONTAL SCALER VERTICAL SCALER AND ANTI-FLICKER FILTER BORDER GENERATOR VIDEO ENCODER MATRIX (OR BYPASS) FIFO 5 30 28 TRIPLE DAC SAA7102H SAA7103H 27 26 OSCILLATOR/ DTO CGC LOW-PASS 23 35 34 XTALI XTAL 13 14 21 FSVGC 22 HSVGC 24 12 SDA TTXRQ_XCLKO2 GREEN_VBS_CVBS RED_CR_C HSM_CSYNC VSM MHB963 Product specification Fig.1 Block diagram. 5 RESET SCL CBO 27 MHz 11 BLUE_CB_CVBS SAA7102; SAA7103 VSVGC TTX_SRES 25 I2C-BUS CONTROL TIMING GENERATOR handbook, full pagewidth PIXCLKO 20 Digital video encoder PD11 to PD0 4 to 1, 44 to 41, 16 to 19 9 BLOCK DIAGRAM 10 TRST TDI Philips Semiconductors 5 2001 Sep 25 VSSA1 VDDA2 VDDD2 RSET VSSD1 VSSD2 VDDA1 DUMP VDDD1 Philips Semiconductors Product specification Digital video encoder 6 SAA7102; SAA7103 PINNING PIN SYMBOL PD8 PIN (1) TYPE BGA156 QFP44 B2 1 I DESCRIPTION see Tables 25 to 29 for pin assignment PD9 B1 2 I see Tables 25 to 29 for pin assignment PD10 C2 3 I see Tables 25 to 29 for pin assignment PD11 C1 4 I see Tables 25 to 29 for pin assignment RESET D2 5 I reset input; active LOW TMS D3 6 I test mode select input for Boundary Scan Test (BST); note 2 TDO D1 7 O test data output for BST; note 2 TCLK E1 8 I test clock input for BST; note 2 VSSD1 E4 9 S digital ground 1 (peripheral cells) VDDD1 F4 10 S digital supply voltage 1 (3.3 V, peripheral cells) SCL E2 11 I I2C-bus serial clock input SDA G2 12 I/O I2C-bus serial data input/output FSVGC G1 13 I/O frame synchronization output to Video Graphics Controller (VGC) (optional input) VSVGC F1 14 I/O vertical synchronization output to VGC (optional input) PIXCLKI F2 15 I pixel clock input (looped through) PD3 F3 16 I MSB − 4 with CB-Y-CR 4 : 2 : 2; see Tables 25 to 29 for pin assignment PD2 H1 17 I MSB − 5 with CB-Y-CR 4 : 2 : 2; see Tables 25 to 29 for pin assignment PD1 H2 18 I MSB − 6 with CB-Y-CR 4 : 2 : 2; see Tables 25 to 29 for pin assignment PD0 H3 19 I MSB − 7 with CB-Y-CR 4 : 2 : 2; see Tables 25 to 29 for pin assignment PIXCLKO G4 20 O pixel clock output to VGC CBO G3 21 O composite blanking output to VGC; active LOW HSVGC E3 22 I/O horizontal synchronization output to VGC (optional input) TTX_SRES C3 23 I teletext input or sync reset input TTXRQ_XCLKO2 C4 24 O teletext request output or 13.5 MHz clock output of the crystal oscillator VSM D7 25 O vertical synchronization output to monitor (non-interlaced auxiliary RGB) HSM_CSYNC D8 26 O horizontal synchronization output to monitor (non-interlaced auxiliary RGB) or composite sync for RGB-SCART RED_CR_C C8 27 O analog output of RED or CR or C signal GREEN_VBS_CVBS C7 28 O analog output of GREEN or VBS or CVBS signal A10, B9, C9, D9 29 S analog supply voltage 1 (3.3 V for DACs) C6 30 O analog output of BLUE or CB or CVBS signal VDDA1 BLUE_CB_CVBS 2001 Sep 25 6 Philips Semiconductors Product specification Digital video encoder SAA7102; SAA7103 PIN SYMBOL PIN (1) BGA156 QFP44 TYPE DESCRIPTION RSET A9 31 O DAC reference pin; connected via 1 kΩ resistor to analog ground (do not use capacitor in parallel with 1 kΩ resistor) DUMP A7, B7 32 O DAC reference pin; connected via 12 Ω resistor to analog ground VSSA1 A8, B8 33 S analog ground 1 XTALO A6 34 O crystal oscillator output XTALI A5 35 I crystal oscillator input VDDA2 B6, D6 36 S analog supply voltage 2 (3.3 V for DACs and oscillator) TRST A4 37 I test reset input for BST; active LOW; notes 3 and 4 TDI B5 38 I test data input for BST; note 2 VSSD2 C5, D5 39 S digital ground 2 VDDD2 D4 40 S digital supply voltage 2 (3.3 V, core) PD4 A3 41 I MSB − 3 with CB-Y-CR 4 : 2 : 2; see Tables 25 to 29 for pin assignment PD5 B3 42 I MSB − 2 with CB-Y-CR 4 : 2 : 2; see Tables 25 to 29 for pin assignment PD6 B4 43 I MSB − 1 with CB-Y-CR 4 : 2 : 2; see Tables 25 to 29 for pin assignment PD7 A2 44 I MSB with CB-Y-CR 4 : 2 : 2; see Tables 25 to 29 for pin assignment Notes 1. Pin type: I = input, O = output, S = supply. 2. In accordance with the “IEEE1149.1” standard the pins TDI, TMS, TCLK and TRST are input pins with an internal pull-up resistor and TDO is a 3-state output pin. 3. For board design without boundary scan implementation connect TRST to ground. 4. This pin provides easy initialization of the Boundary Scan Test (BST) circuit. TRST can be used to force the Test Access Port (TAP) controller to the TEST_LOGIC_RESET state (normal operation) at once. 2001 Sep 25 7 Philips Semiconductors Product specification Digital video encoder Table 1 Pin assignment SAA7102E; SAA7103E (top view) 1 2 3 4 PD7 PD4 TRST PD9 PD8 PD5 PD6 C PD11 PD10 A B D SAA7102; SAA7103 TDO RESET E TCLK SCL TMS VDDD2 7 XTALI XTALO DUMP TDI VDDA2 DUMP VSSD2 VDDA2 VSM HSVGC VSSD1 VDDD1 G FSVGC SDA CBO PIXCLKO H PD0 PD1 6 J K L M N P 2001 Sep 25 8 9 8 10 VSSA1 RSET VDDA1 VSSA1 VDDA1 TTX_ TTXRQ_ VSSD2 BLUE_ GREEN_ RED_ VDDA1 SRES XCLKO2 CB_ VBS_ CR_ CVBS CVBS C F VSVGCPIXCLKI PD3 PD2 5 HSM_ VDDA1 CSYNC 11 12 13 14 Philips Semiconductors Product specification Digital video encoder SAA7102; SAA7103 MHB907 handbook, halfpage P N M L K J H G F E D C B A SAA7102E SAA7103E 1 2 3 4 5 6 7 8 9 10 11 12 13 14 34 XTALO 35 XTALI 36 VDDA2 37 TRST 38 TDI 39 VSSD2 41 PD4 42 PD5 43 PD6 44 PD7 handbook, full pagewidth 40 VDDD2 Fig.2 Pin configuration (SAA7102E; SAA7103E). PD8 1 33 VSSA1 PD9 2 32 DUMP PD10 3 31 RSET PD11 4 30 BLUE_CB_CVBS RESET 5 29 VDDA1 SAA7102H SAA7103H TMS 6 28 GREEN_VBS_CVBS TDO 7 27 RED_CR_C TCLK 8 26 HSM_CSYNC VSSD1 9 25 VSM VDDD1 10 24 TTXRQ_XCLKO2 HSVGC 22 CBO 21 PIXCLKO 20 PD0 19 PD1 18 PD2 17 PD3 16 PIXCLKI 15 VSVGC 14 FSVGC 13 23 TTX_SRES SDA 12 SCL 11 Fig.3 Pin configuration (SAA7102H; SAA7103H). 2001 Sep 25 9 MHB908 Philips Semiconductors Product specification Digital video encoder 7 SAA7102; SAA7103 For ease of analog post filtering the signals are twice oversampled to 27 MHz before digital-to-analog conversion. FUNCTIONAL DESCRIPTION The digital video encoder encodes digital luminance and colour difference signals (CB-Y-CR) or digital RGB signals into analog CVBS, S-video and, optionally, RGB or CR-Y-CB signals. NTSC M, PAL B/G and sub-standards are supported. The total filter transfer characteristics (scaler and anti-flicker filter are not taken into account) are illustrated in Figs 4 to 8. All three DACs are realized with full 10-bit resolution. The CR-Y-CB to RGB dematrix can be bypassed (optionally) in order to provide the upsampled CR-Y-CB input signals. The SAA7102; SAA7103 can be directly connected to a PC video graphics controller with a maximum resolution of 800 × 600 at a 50 or 60 Hz frame rate. A programmable scaler scales the computer graphics picture so that it will fit into a standard TV screen with an adjustable underscan area. Non-interlaced-to-interlaced conversion is optimized with an adjustable anti-flicker filter for a flicker-free display at a very high sharpness. The 8-bit multiplexed CB-Y-CR formats are “ITU-R BT.656” (D1 format) compatible, but the SAV and EAV codes can be decoded optionally, when the device is operated in slave mode. For assignment of the input data to the rising or falling clock edge see Tables 25 to 29. Besides the most common 16-bit 4 : 2 : 2 CB-Y-CR input format (using 8 pins with double edge clocking), other CB-Y-CR and RGB formats are also supported; see Tables 25 to 29. In order to display interlaced RGB signals through a euro-connector TV set, a separate digital composite sync signal (pin 26) can be generated; it can be advanced up to 31 periods of the 27 MHz crystal clock in order to be adapted to the RGB processing of a TV set. A complete 3 × 256 bytes Look-Up Table (LUT), which can be used, for example, as a separate gamma corrector, is located in the RGB domain; it can be loaded either through the video input port PD (Pixel Data) or via the I2C-bus. The SAA7102; SAA7103 synthesizes all necessary internal signals, colour subcarrier frequency and synchronization signals from that clock. The SAA7102; SAA7103 supports a 32 × 32 × 2-bit hardware cursor, the pattern of which can also be loaded through the video input port or via the I2C-bus. Wide screen signalling data can be loaded via the I2C-bus and is inserted into line 23 for standards using a 50 Hz field rate. It is also possible to encode interlaced 4 : 2 : 2 video signals such as PC-DVD; for that the anti-flicker filter, and in most cases the scaler, will simply be bypassed. VPS data for program dependent automatic start and stop of such featured VCRs is loadable via the I2C-bus. The IC also contains Closed Caption and extended data services encoding (line 21), and supports teletext insertion for the appropriate bit stream format at a 27 MHz clock rate (see Fig.14). It is also possible to load data for the copy generation management system into line 20 of every field (525/60 line counting). Besides the applications for video output, the SAA7102; SAA7103 can also be used for generating a kind of auxiliary VGA output, when the RGB non-interlaced input signal is fed to the DACs. This may be of interest for example, when the graphics controller provides a second graphics window at its video output port. A number of possibilities are provided for setting different video parameters such as: The basic encoder function consists of subcarrier generation, colour modulation and insertion of synchronization signals at a crystal-stable clock rate of 13.5 MHz (independent of the actual pixel clock used at the input side), corresponding to an internal 4 : 2 : 2 bandwidth in the luminance/colour difference domain. Luminance and chrominance signals are filtered in accordance with the standard requirements of “RS-170-A” and “ITU-R BT.470-3”. 2001 Sep 25 • Black and blanking level control • Colour subcarrier frequency • Variable burst amplitude etc. 10 Philips Semiconductors Product specification Digital video encoder 7.1 SAA7102; SAA7103 Reset conditions If Y-CB-CR is being applied as a 27 Mbyte/s data stream, the output of the input formatter can be used directly to feed the video encoder block. To activate the reset a pulse at least of 2 crystal clocks duration is required. During reset (RESET = LOW) plus an extra 32 crystal clock periods, FSVGC, VSVGC, CBO, HSVGC and TTX_SRES are set to input mode and HSM_CSYNC and VSM are set to 3-state. A reset also forces the I2C-bus interface to abort any running bus transfer and sets it into receive condition. 7.3 The three 256 byte RAMs of this block can be addressed by three 8-bit wide signals, thus it can be used to build any transformation, e.g. a gamma correction for RGB signals. In the event that the indexed colour data is applied, the RAMs are addressed in parallel. After reset, the state of the I/Os and other functions is defined by the strapping pins until an I2C-bus access redefines the corresponding registers; see Table 2. Table 2 The LUTs can either be loaded by an I2C-bus write access or can be part of the pixel data input through the PD port. In the latter case, 256 × 3 bytes for the R, G and B LUT are expected at the beginning of the input video line, two lines before the line that has been defined as first active line, until the middle of the line immediately preceding the first active line. The first 3 bytes represent the first RGB LUT data, and so on. Strapping pins PIN FSVGC (pin 13) TIED PRESET LOW NTSC M encoding, PIXCLK fits to 640 × 480 graphics input 7.4 HIGH PAL B/G encoding, PIXCLK fits to 640 × 480 graphics input VSVGC (pin 14) LOW LOW 4 : 2 : 2 Y-CB-CR graphics input (format 0) The bit map is stored with 4 pixels per byte, aligned to the least significant bit. So the first pixel is in bits 0 and 1, the next pixel in bits 3 and 4 and so on. The first index is the column, followed by the row; index 0,0 is the upper left corner. input demultiplex phase: LSB = LOW HIGH input demultiplex phase: LSB = HIGH HSVGC (pin 22) LOW input demultiplex phase: MSB = LOW Table 3 HIGH input demultiplex phase: MSB = HIGH TTXRQ_XCLKO2 (pin 24) LOW D7 slave (FSVGC, VSVGC and HSVGC are inputs, internal colour bar is active) HIGH master (FSVGC, VSVGC and HSVGC are outputs) 7.2 Input formatter The input formatter converts all accepted PD input data formats, either RGB or Y-CB-CR, to a common internal RGB or Y-CB-CR data stream. When double-edge clocking is used, the data is internally split into portions PPD1 and PPD2. The clock edge assignment must be set according to the I2C-bus control bits EDGE1 and EDGE2 for correct operation. 2001 Sep 25 Cursor insertion The cursor bit map is set up as follows: each pixel occupies 2 bits. The meaning of these bits depends on the CMODE I2C-bus register as described in Table 5. Transparent means that the input pixels are passed through, the ‘cursor colours’ can be programmed in separate registers. HIGH 4 : 4 : 4 RGB graphics input (format 3) CBO (pin 21) RGB LUT 11 Layout of a byte in the cursor bit map D6 D5 D4 D3 D2 D1 pixel n + 3 pixel n + 2 pixel n + 1 pixel n D1 D1 D1 D1 D0 D0 D0 D0 D0 Philips Semiconductors Product specification Digital video encoder Table 4 SAA7102; SAA7103 7.6 Cursor bit map BYTE D7 D6 D5 D4 D3 D2 D1 row 0 column 3 row 0 column 2 row 0 column 1 row 0 column 0 1 row 0 column 7 row 0 column 6 row 0 column 5 row 0 column 4 2 row 0 column 11 row 0 column 10 row 0 column 9 row 0 column 8 ... ... ... ... ... 6 row 0 column 27 row 0 column 26 row 0 column 25 row 0 column 24 7 row 0 column 31 row 0 column 30 row 0 column 29 row 0 column 28 ... ... 254 255 Table 5 ... ... The scaler starts processing after a programmable horizontal offset and continues with a number of input pixels. Each input pixel is a programmable fraction of the current output pixel (XINC/4096). A special case is XINC = 0, this sets the scaling factor to 1. If the SAA7102; SAA7103 input data is in accordance with “ITU-R BT.656”, the scaler enters another mode. In this event, XINC needs to be set to 2048 for a scaling factor of 1. With higher values, upscaling will occur. The phase resolution of the circuit is 12 bits, giving a maximum offset of 0.2 after 800 input pixels. Small FIFOs rearrange a 4 : 2 : 2 data stream at the scaler output. ... row 31 column 27 row 31 column 26 row 31 column 25 row 31 column 24 row 31 column 31 row 31 column 30 row 31 column 29 row 31 column 28 7.7 Besides the entire input frame, it receives the first and last lines of the border to allow anti-flicker filtering. The circuit generates the interlaced output fields by scaling down the input frames with different offsets for odd and even fields. Increasing the YSKIP setting reduces the anti-flicker function. A YSKIP value of 4095 switches it off; see Table 94. CURSOR MODE CMODE = 0 CMODE = 1 00 second cursor colour second cursor colour 01 first cursor colour first cursor colour 10 transparent transparent 11 inverted input auxiliary cursor colour The programming is similar to the horizontal scaler. For the re-interlacing, the resolutions of the offset registers are not sufficient, so the weighting factors for the first lines can also be adjusted. YINC = 0 sets the scaling factor to 1; YIWGTO and YIWGTE must not be 0. Due to the re-interlacing, the circuit can perform upscaling. The maximum factor depends on the setting of the anti-flicker function and can be derived from the formulae given in Section 7.17. RGB Y-CB-CR matrix RGB input signals to be encoded to PAL or NTSC are converted to the Y-CB-CR colour space in this block. The colour difference signals are fed through low-pass filters and formatted to a ITU-R BT.601 like 4 : 2 : 2 data stream for further processing. The matrix and formatting blocks can be bypassed for Y-CB-CR graphics input. When the auxiliary VGA mode is selected, the output of the cursor insertion block is immediately directed to the triple DAC. 2001 Sep 25 Vertical scaler and anti-flicker filter The functions scaling, Anti-Flicker Filter (AFF) and re-interlacing are implemented in the vertical scaler. Cursor modes CURSOR PATTERN 7.5 The high quality horizontal scaler operates on the 4 : 2 : 2 data stream. Its control engines compensate the colour phase offset automatically. D0 0 Horizontal scaler 12 Philips Semiconductors Product specification Digital video encoder 7.8 SAA7102; SAA7103 Input to the encoder, at 27 MHz clock (e.g. DVD), is either originated from computer graphics at pixel clock, fed through the FIFO and border generator, or a ITU-R BT.656 style signal. FIFO The FIFO acts as a buffer to translate from the PIXCLK clock domain to the XTAL clock domain. The write clock is PIXCLK and the read clock is XTAL. An underflow or overflow condition can be detected via the I2C-bus read access. Luminance is modified in gain and in offset (the offset is programmable in a certain range to enable different black level set-ups). A blanking level can be set after insertion of a fixed synchronization pulse tip level, in accordance with standard composite synchronization schemes. Other manipulations used for the Macrovision anti-taping process, such as additional insertion of AGC super-white pulses (programmable in height), are supported by the SAA7102 only. In order to avoid underflows and overflows, it is essential that the frequency of the synthesized PIXCLK matches to the input graphics resolution and the desired scaling factor. It is suggested to refer to Tables 6 to 23 for some representative combinations. 7.9 Border generator To enable easy analog post filtering, luminance is interpolated from a 13.5 MHz data rate to a 27 MHz data rate, thereby providing luminance in a 10-bit resolution. The transfer characteristics of the luminance interpolation filter are illustrated in Figs 7 and 8. Appropriate transients at start/end of active video and for synchronization pulses are ensured. When the graphics picture is to be displayed as interlaced PAL, NTSC, S-video or RGB on a TV screen, it is desired in many cases not to lose picture information due to the inherent overscanning of a TV set. The desired amount of underscan area, which is achieved through appropriate scaling in the vertical and horizontal direction, can be filled in the border generator with an arbitrary true colour tint. 7.10 Chrominance is modified in gain (programmable separately for CB and CR), and a standard dependent burst is inserted, before baseband colour signals are interpolated from a 6.75 MHz data rate to a 27 MHz data rate. One of the interpolation stages can be bypassed, thus providing a higher colour bandwidth, which can be used for the Y and C output. The transfer characteristics of the chrominance interpolation filter are illustrated in Figs 4 and 5. Oscillator and Discrete Time Oscillator (DTO) The master clock generation is realized as a 27 MHz crystal oscillator, which can operate with either a fundamental wave crystal or a 3rd-harmonic crystal. The crystal clock supplies the DTO of the pixel clock synthesizer, the video encoder and the I2C-bus control block. It also usually supplies the triple DAC, with the exception of the auxiliary VGA mode, where the triple DAC is clocked by the pixel clock (PIXCLK). The amplitude (beginning and ending) of the inserted burst, is programmable in a certain range that is suitable for standard signals and for special effects. After the succeeding quadrature modulator, colour is provided on the subcarrier in 10-bit resolution. The DTO can be programmed to synthesize all relevant pixel clock frequencies between circa 18 and 44 MHz. 7.11 Low-pass Clock Generation Circuit (CGC) The numeric ratio between the Y and C outputs is in accordance with the standards. This block reduces the phase jitter of the synthesized pixel clock. It works as a tracking filter for all relevant synthesized pixel clock frequencies. 7.12.2 TELETEXT INSERTION AND ENCODING (NOT SIMULTANEOUSLY WITH REAL-TIME CONTROL) 7.12 7.12.1 Encoder Pin TTX_SRES receives a WST or NABTS teletext bitstream sampled at the crystal clock. At each rising edge of the output signal (TTXRQ) a single teletext bit has to be provided after a programmable delay at input pin TTX_SRES. VIDEO PATH The encoder generates luminance and colour subcarrier output signals from the Y, CB and CR baseband signals, which are suitable for use as CVBS or separate Y and C signals. 2001 Sep 25 13 Philips Semiconductors Product specification Digital video encoder SAA7102; SAA7103 The transfer curves of luminance and colour difference components of RGB are illustrated in Figs 8 and 9. Phase variant interpolation is achieved on this bitstream in the internal teletext encoder, providing sufficient small phase jitter on the output text lines. 7.14 TTXRQ_XCLKO2 provides a fully programmable request signal to the teletext source, indicating the insertion period of bitstream at lines which can be selected independently for both fields. The internal insertion window for text is set to 360 (PAL WST), 296 (NTSC WST) or 288 (NABTS) teletext bits including clock run-in bits. The protocol and timing are illustrated in Fig.14. Both Y and C signals are converted from digital-to-analog in a 10-bit resolution at the output of the video encoder. Y and C signals are also combined into a 10-bit CVBS signal. The CVBS output signal occurs with the same processing delay as the Y, C and optional RGB or CR-Y-CB outputs. Absolute amplitude at the input of the DAC for CVBS is reduced by 15⁄16 with respect to Y and C DACs to make maximum use of the conversion ranges. Alternatively, this pin can be provided with a buffered crystal clock (XCLK) of 13.5 MHz. 7.12.3 VIDEO PROGRAMMING SYSTEM (VPS) ENCODING RED, GREEN and BLUE signals are also converted from digital-to-analog, each providing a 10-bit resolution. Five bytes of VPS information can be loaded via the I2C-bus and will be encoded in the appropriate format into line 16. 7.12.4 The reference currents of all three DACs can be adjusted individually in order to adapt for different output signals. In addition, all reference currents can be adjusted commonly to compensate for small tolerances of the on-chip band gap reference voltage. CLOSED CAPTION ENCODER Using this circuit, data in accordance with the specification of Closed Caption or extended data service, delivered by the control interface, can be encoded (line 21). Two dedicated pairs of bytes (two bytes per field), each pair preceded by run-in clocks and framing code, are possible. Alternatively, all currents can be switched off to reduce power dissipation. All three outputs can be used to sense for an external load (usually 75 Ω) during a pre-defined output. A flag in the I2C-bus status byte reflects whether a load is applied or not. The actual line number in which data is to be encoded, can be modified in a certain range. The data clock frequency is in accordance with the definition for NTSC M standard 32 times horizontal line frequency. If the SAA7102; SAA7103 is required to drive a second (auxiliary) VGA monitor, the DACs receive the signal directly from the cursor insertion block. In this event, the DACs are clocked at the incoming PIXCLKI instead of the 27 MHz crystal clock used in the video encoder. Data LOW at the output of the DACs corresponds to 0 IRE, data HIGH at the output of the DACs corresponds to approximately 50 IRE. 7.15 It is also possible to encode Closed Caption data for 50 Hz field frequencies at 32 times the horizontal line frequency. 7.12.5 ANTI-TAPING (SAA7102 ONLY) In slave mode, the circuit accepts sync pulses on the bidirectional FSVGC (frame sync), VSVGC (vertical sync) and HSVGC (horizontal sync) pins: the polarities of the signals can be programmed. The frame sync signal is only necessary when the input signal is interlaced, in other cases it may be omitted. If the frame sync signal is present, it is possible to derive the vertical and the horizontal phase from it by setting the HFS and VFS bits. HSVGC and VSVGC are not necessary in this case, so it is possible to switch the pins to output mode. RGB processor This block contains a dematrix in order to produce RED, GREEN and BLUE signals to be fed to a SCART plug. Before Y, CB and CR signals are de-matrixed, individual gain adjustment for Y and colour difference signals and 2 times oversampling for luminance and 4 times oversampling for colour difference signals is performed. 2001 Sep 25 Timing generator The synchronization of the SAA7102; SAA7103 is able to operate in two modes; slave mode and master mode. For more information contact your nearest Philips Semiconductors sales office. 7.13 Triple DAC Alternatively, the device can be triggered by auxiliary codes in a ITU-R BT.656 data stream via PD7 to PD0. 14 Philips Semiconductors Product specification Digital video encoder SAA7102; SAA7103 The register bit map consists of an RGB Look-Up Table (LUT), a cursor bit map and control registers. The LUT contains three banks of 256 bytes, where each RGB triplet is assigned to one address. Thus a write access needs the LUT address and three data bytes following subaddress FFH. For further write access auto-incrementing of the LUT address is performed. The cursor bit map access is similar to the LUT access but contains only a single byte per address. Only vertical frequencies of 50 and 60 Hz are allowed with the SAA7102; SAA7103. In slave mode, it is not possible to lock the encoders colour carrier to the line frequency with the PHRES bits. In the (more common) master mode, the time base of the circuit is continuously free-running. The IC can output a frame sync at pin FSVGC, a vertical sync at pin VSVGC, a horizontal sync at pin HSVGC and a composite blanking signal at pin CBO. All of these signals are defined in the PIXCLK domain. The duration of HSVGC and VSVGC are fixed, they are 64 clocks for HSVGC and 1 line for VSVGC. The leading slopes are in phase and the polarities can be programmed. The I2C-bus slave address is defined as 88H. 7.17 In order to program the SAA7102; SAA7103 it is first necessary to determine the input and output field timings. The timings are controlled by decoding binary counters that index the position in the current line and field respectively. In both cases, 0 means the start of the sync pulse. The input line length can be programmed. The field length is always derived from the field length of the encoder and the pixel clock frequency that is being used. CBO acts as a data request signal. The circuit accepts input data at a programmable number of clocks after CBO goes active. This signal is programmable and it is possible to adjust the following (see Figs 12 and 13): At 60 Hz, the first visible pixel has the index 256, 710 pixels can be encoded; at 50 Hz, the index is 284, 702 pixels can be visible. Some variables are defined below: • The horizontal offset • The length of the active part of the line • InPix: the number of active pixels per input line • The distance from active start to first expected data • InPpl: the length of the entire input line in pixel clocks • The vertical offset separately for odd and even fields • InLin: the number of active lines per input field/frame • The number of lines per input field. • TPclk: the pixel clock period In most cases, the vertical offsets for odd and even fields are equal. If they are not, then the even field will start later. The SAA7102; SAA7103 will also request the first input lines in the even field, the total number of requested lines will increase by the difference of the offsets. • OutPix: the number of active pixels per output line • OutLin: the number of active lines per output field • TXclk: the encoder clock period (37.037 ns). The output lines should be centred on the screen. It should be noted that the encoder has 2 clocks per pixel; see Table 71. As stated above, the circuit can be programmed to accept the look-up and cursor data in the first 2 lines of each field. The timing generator provides normal data request pulses for these lines; the duration is the same as for regular lines. The additional request pulses will be suppressed with LUTL set to logic 0; see Table 104. The other vertical timings do not change in this case, so the first active line can be number 2, counted from 0. 7.16 ADWHS = 256 + 710 − OutPix (60 Hz); ADWHS = 284 + 702 − OutPix (50 Hz); ADWHE = ADWHS + OutPix × 2 (all frequencies) For vertical, the procedure is the same. At 60 Hz, the first line with video information is number 19, 240 lines can be active. For 50 Hz, the numbers are 23 and 287; see Table 77. I2C-bus interface The I2C-bus interface is a standard slave transceiver, supporting 7-bit slave addresses and 400 kbits/s guaranteed transfer rate. It uses 8-bit subaddressing with an auto-increment function. All registers are write and read, except two read only status bytes. 2001 Sep 25 Programming the SAA7102; SAA7103 240 – OutLin FAL = 19 + --------------------------------- (60 Hz); 2 287 – OutLin FAL = 23 + --------------------------------- (50 Hz); 2 LAL = FAL + OutLin (all frequencies) 15 Philips Semiconductors Product specification Digital video encoder SAA7102; SAA7103 Most TV sets use overscan, and not all pixels respectively lines are visible. There is no standard for the factor, it is highly recommended to make the number of output pixels and lines adjustable. A reasonable underscan factor is 10%, giving approximately 640 output pixels per line. YPIX = InLin The total number of pixel clocks per line and the input horizontal offset need to be chosen next. The only constraint is that the horizontal blanking has at least 10 clock pulses. OutLin YSKIP YINC = ---------------------- × 1 + ----------------- × 4096 InLin + 2 4095 YSKIP defines the anti-flicker function. 0 means maximum flicker reduction but minimum vertical bandwidth, 4095 gives no flicker reduction and maximum bandwidth. YINC YIWGTO = -------------- + 2048 2 The required pixel clock frequency can be determined in the following way: Due to the limited internal FIFO size, the input path has to provide all pixels in the same time frame as the encoders vertical active time. The scaler also has to process the first and last border lines for the anti-flicker function. Thus: YINC – YSKIP YIWGTE = -------------------------------------2 When YINC = 0 it sets the scaler to scaling factor 1. The initial weighting factors must not be set to 0 in this case. YIWGTE may go negative. In this event, YINC should be added and YOFSE incremented. This can be repeated as often as necessary to make YIWGTE positive. 262.5 × 1716 × TXclk TPclk = ---------------------------------------------------------------------------------------- (60 Hz) InLin + 2 InPpl × integer ---------------------- × 262.5 OutLin Due to the limited amount of memory it is not possible to get valid vertical scaler settings only from the formulae above. In some cases it is necessary to adjust the vertical offsets or the scaler increment to get valid settings. Tables 6 to 23 show verified settings. They are organised in the following way: The tables are separate for the standard to be encoded, the input resolution and three different anti-flicker filter settings. Each table contains 5 vertical sizes with 5 different offsets. They are intended to be selected according to the current TV set. The corresponding horizontal resolutions of 640 pixels give proper aspect ratios. They can be adjusted according to the formulae above. The next line gives a minimum size intended to fit on the screen under all circumstances. The corresponding horizontal resolution is 620 pixels. Overscan is only possible with an input resolution of 800 × 600 pixels. Where possible, the corresponding settings are given on the last lines of the tables. 312.5 × 1728 × TXclk TPclk = ---------------------------------------------------------------------------------------- (50 Hz) InLin + 2 InPpl × integer ---------------------- × 312.5 OutLin TXclk 21 and for the pixel clock generator PCL = --------------- × 2 TPclk (all frequencies); see Table 80. The input vertical offset can be taken from the assumption that the scaler should just have finished writing the first line when the encoder starts reading it: FAL × 1716 × TXclk YOFS = ---------------------------------------------------- – 2 (60 Hz) InPpl × TPclk FAL × 1728 × TXclk YOFS = ---------------------------------------------------- – 2 (50 Hz) InPpl × TPclk In most cases the vertical offsets will be the same for odd and even fields. The results should be rounded down. Once the timings are known the scaler can be programmed. XOFS can be chosen arbitrarily, the condition being that XOFS + XPIX ≤ HLEN is fulfilled. Values given by the VESA display timings are preferred. OutPix InPix HLEN = InPpl − 1 XPIX = ------------- XINC = ------------------ × 4096 InPix 2 XINC needs to be rounded up, it needs to be set to 0 for a scaling factor of 1. 2001 Sep 25 16 Philips Semiconductors Product specification Digital video encoder 7.18 SAA7102; SAA7103 Input levels and formats The SAA7102; SAA7103 accepts digital Y, CB, CR or RGB data with levels (digital codes) in accordance with “ITU-R BT.601”; see Table 23. For C and CVBS outputs, deviating amplitudes of the colour difference signals can be compensated for by independent gain control setting, while gain for luminance is set to predefined values, distinguishable for 7.5 IRE set-up or without set-up. The RGB, respectively CR-Y-CB path features an individual gain setting for luminance (GY) and colour difference signals (GCD). Reference levels are measured with a colour bar, 100% white, 100% amplitude and 100% saturation. Table 6 Y scaler programming at NTSC, input frame size: 640 × 400, full anti-flicker filter TV LINE OFFSET FAL LAL PCL YINC YSKIP YOFSO YOFSE YIWGTO YIWGTE Regular size (horizontal TV size: 640 pixels, offset ±10 pixels) 212 −4 29 241 1851099 2163 0 52 52 3128 1080 212 −2 31 243 1851099 2163 0 56 56 3128 1080 212 0 33 245 1851099 2163 0 60 60 3128 1080 212 2 35 247 1851099 2163 0 63 63 3128 1080 212 4 37 249 1851099 2163 0 67 67 3128 1080 214 −4 28 242 1836201 2181 0 50 50 3138 1090 214 −2 30 244 1836201 2181 0 54 54 3138 1090 214 0 32 246 1836201 2181 0 57 57 3138 1090 214 2 34 248 1836201 2181 0 61 61 3138 1090 214 4 36 250 1836201 2181 0 65 65 3138 1090 216 −4 27 243 1817578 2202 0 47 47 3148 1100 216 −2 29 245 1817578 2202 0 51 51 3148 1100 216 0 31 247 1817578 2202 0 55 55 3148 1100 216 2 33 249 1817578 2202 0 58 58 3148 1100 216 4 35 251 1817578 2202 0 62 62 3148 1100 218 −4 26 244 1802680 2222 0 45 45 3158 1110 218 −2 28 246 1802680 2222 0 49 49 3158 1110 218 0 30 248 1802680 2222 0 53 53 3158 1110 218 2 32 250 1802680 2222 0 56 56 3158 1110 218 4 34 252 1802680 2222 0 60 60 3158 1110 220 −4 25 245 1784057 2245 0 43 43 3168 1120 220 −2 27 247 1784057 2245 0 46 46 3168 1120 220 0 29 249 1784057 2245 0 50 50 3168 1120 220 2 31 251 1784057 2245 0 54 54 3168 1120 220 4 33 253 1784057 2245 0 57 57 3168 1120 0 0 0 0 0 0 0 1925590 2079 0 70 70 3087 1039 Overscan (horizontal size: 710 pixels) 241 0 0 0 Small size (horizontal size: 620 pixels) 204 2001 Sep 25 0 37 241 17 Philips Semiconductors Product specification Digital video encoder Table 7 SAA7102; SAA7103 Y scaler programming at NTSC, input frame size: 640 × 400, half anti-flicker filter TV LINE OFFSET FAL LAL PCL YINC YSKIP YOFSO YOFSE YIWGTO YIWGTE Regular size (horizontal TV size: 640 pixels, offset ±10 pixels) 212 −4 29 241 1851099 3123 1820 52 52 3668 596 212 −2 31 243 1851099 3123 1820 56 56 3668 596 212 0 33 245 1851099 3123 1820 60 60 3668 596 212 2 35 247 1851099 3123 1820 64 64 3668 596 212 4 37 249 1851099 3123 1820 67 67 3668 596 214 −4 28 242 1836201 3135 1790 50 50 3683 611 214 −2 30 244 1836201 3135 1790 54 54 3683 611 214 0 32 246 1836201 3135 1790 58 58 3683 611 214 2 34 248 1836201 3135 1790 61 61 3683 611 214 4 36 250 1836201 3135 1790 65 65 3683 611 216 −4 27 243 1817578 3145 1750 48 48 3698 626 216 −2 29 245 1817578 3145 1750 51 51 3698 626 216 0 31 247 1817578 3145 1750 55 55 3698 626 216 2 33 249 1817578 3145 1750 59 59 3698 626 216 4 35 251 1817578 3145 1750 63 63 3698 626 218 −4 26 244 1802680 3155 1720 45 45 3714 642 218 −2 28 246 1802680 3155 1720 49 49 3714 642 218 0 30 248 1802680 3155 1720 53 53 3714 642 218 2 32 250 1802680 3155 1720 56 56 3714 642 218 4 34 252 1802680 3155 1720 60 60 3714 642 220 −4 25 245 1784057 3165 1680 43 43 3729 657 220 −2 27 247 1784057 3165 1680 47 47 3729 657 220 0 29 249 1784057 3165 1680 50 50 3729 657 220 2 31 251 1784057 3165 1680 54 54 3729 657 220 4 33 253 1784057 3165 1680 58 58 3729 657 0 0 0 0 0 0 0 1925590 3087 1980 70 70 3589 551 Full size (horizontal size: 710 pixels) 241 0 0 0 Small size (horizontal size: 620 pixels) 204 2001 Sep 25 0 37 241 18 Philips Semiconductors Product specification Digital video encoder Table 8 SAA7102; SAA7103 Y scaler programming at NTSC, input frame size: 640 × 400, no anti-flicker filter TV LINE OFFSET FAL LAL PCL YINC YSKIP YOFSO YOFSE YIWGTO YIWGTE Regular size (horizontal TV size: 640 pixels, offset ±10 pixels) 212 −4 29 241 1851099 4094 3655 52 52 4092 216 212 −2 31 243 1851099 4094 3655 56 56 4092 216 212 0 33 245 1851099 4094 3655 60 60 4092 216 212 2 35 247 1851099 4094 3655 64 64 4092 216 212 4 37 249 1851099 4094 3655 68 68 4092 216 214 −4 28 242 1836201 4090 3580 50 50 4091 253 214 −2 30 244 1836201 4090 3580 54 54 4091 253 214 0 32 246 1836201 4090 3580 58 58 4091 253 214 2 34 248 1836201 4088 3580 61 61 4091 253 214 4 36 250 1836201 4088 3580 65 65 4091 253 216 −4 27 243 1817578 4093 3510 48 48 4091 288 216 −2 29 245 1817578 4093 3510 52 52 4091 288 216 0 31 247 1817578 4093 3510 55 55 4091 288 216 2 33 249 1817578 4093 3510 59 59 4091 288 216 4 35 251 1817578 4093 3510 63 63 4091 288 218 −4 26 244 1802680 4092 3445 46 46 4092 322 218 −2 28 246 1802680 4092 3445 49 49 4092 322 218 0 30 248 1802680 4092 3445 53 53 4092 322 218 2 32 250 1802680 4092 3445 57 57 4092 322 218 4 34 252 1802680 4092 3445 60 60 4092 322 220 −4 25 245 1784057 4090 3370 43 43 4091 358 220 −2 27 247 1784057 4090 3370 47 47 4091 358 220 0 29 249 1784057 4090 3370 50 50 4091 358 220 2 31 251 1784057 4090 3370 54 54 4091 358 220 4 33 253 1784057 4090 3370 58 58 4091 358 0 0 0 0 0 0 0 1925590 4087 3950 70 70 4089 66 Full size (horizontal size: 710 pixels) 241 0 0 0 Small size (horizontal size: 620 pixels) 204 2001 Sep 25 0 37 241 19 Philips Semiconductors Product specification Digital video encoder Table 9 SAA7102; SAA7103 Y scaler programming at NTSC, input frame size: 640 × 480, full anti-flicker filter TV LINE OFFSET FAL LAL PCL YINC YSKIP YOFSO YOFSE YIWGTO YIWGTE Regular size (horizontal TV size: 640 pixels, offset ±10 pixels) 212 −4 29 241 2219829 1804 0 63 63 2948 900 212 −2 31 243 2219829 1804 0 67 67 2948 900 212 0 33 245 2219829 1804 0 72 72 2948 900 212 2 35 247 2219829 1804 0 77 77 2948 900 212 4 37 249 2219829 1804 0 81 81 2948 900 214 −4 28 242 2201206 1819 0 60 60 2957 909 214 −2 30 244 2201206 1819 0 65 65 2957 909 214 0 32 246 2201206 1819 0 69 69 2957 909 214 2 34 248 2201206 1819 0 73 73 2957 909 214 4 36 250 2201206 1819 0 78 78 2957 909 216 −4 27 243 2178859 1836 0 57 57 2965 917 216 −2 29 245 2178859 1836 0 61 61 2965 917 216 0 31 247 2178859 1836 0 66 66 2965 917 216 2 33 249 2178859 1836 0 70 70 2965 917 216 4 35 251 2178859 1836 0 75 75 2965 917 218 −4 26 244 2160236 1853 0 54 54 2974 926 218 −2 28 246 2160236 1853 0 59 59 2974 926 218 0 30 248 2160236 1853 0 63 63 2974 926 218 2 32 250 2160236 1853 0 68 68 2974 926 218 4 34 252 2160236 1853 0 72 72 2974 926 220 −4 25 245 2141613 1870 0 52 52 2982 934 220 −2 27 247 2141613 1870 0 56 56 2982 934 220 0 29 249 2141613 1870 0 61 61 2982 934 220 2 31 251 2141613 1870 0 65 65 2982 934 220 4 33 253 2141613 1870 0 69 69 2982 934 0 0 0 0 0 0 0 2309218 1734 0 84 84 2941 866 Full size (horizontal size: 710 pixels) 241 0 0 0 Small size (horizontal size: 620 pixels) 204 2001 Sep 25 0 37 241 20 Philips Semiconductors Product specification Digital video encoder SAA7102; SAA7103 Table 10 Y scaler programming at NTSC, input frame size: 640 × 480, half anti-flicker filter TV LINE OFFSET FAL LAL PCL YINC YSKIP YOFSO YOFSE YIWGTO YIWGTE Regular size (horizontal TV size: 640 pixels, offset ±10 pixels) 212 −4 29 241 2219829 2704 2048 63 63 3399 327 212 −2 31 243 2219829 2704 2048 67 67 3399 327 212 0 33 245 2219829 2704 2048 72 72 3399 327 212 2 35 247 2219829 2704 2048 77 77 3399 327 212 4 37 249 2219829 2704 2048 81 81 3399 327 214 −4 28 242 2201206 2730 2048 60 60 3412 340 214 −2 30 244 2201206 2730 2048 65 65 3412 340 214 0 32 246 2201206 2730 2048 69 69 3412 340 214 2 34 248 2201206 2730 2048 74 74 3412 340 214 4 36 250 2201206 2730 2048 78 78 3412 340 216 −4 27 243 2178859 2756 2048 57 57 3424 352 216 −2 29 245 2178859 2756 2048 62 62 3424 352 216 0 31 247 2178859 2756 2048 66 66 3424 352 216 2 33 249 2178859 2756 2048 71 71 3424 352 216 4 35 251 2178859 2756 2048 75 75 3424 352 218 −4 26 244 2160236 2781 2048 55 55 3437 365 218 −2 28 246 2160236 2781 2048 59 59 3437 365 218 0 30 248 2160236 2781 2048 63 63 3437 365 218 2 32 250 2160236 2781 2048 68 68 3437 365 218 4 34 252 2160236 2781 2048 72 72 3437 365 220 −4 25 245 2141613 2807 2048 52 52 3450 378 220 −2 27 247 2141613 2807 2048 57 57 3450 378 220 0 29 249 2141613 2807 2048 61 61 3450 378 220 2 31 251 2141613 2807 2048 65 65 3450 378 220 4 33 253 2141613 2807 2048 70 70 3450 378 0 0 0 0 0 0 0 2309218 2602 2048 84 84 3348 276 Full size (horizontal size: 710 pixels) 241 0 0 0 Small size (horizontal size: 620 pixels) 204 2001 Sep 25 0 37 241 21 Philips Semiconductors Product specification Digital video encoder SAA7102; SAA7103 Table 11 Y scaler programming at NTSC, input frame size: 640 × 480, no anti-flicker filter TV LINE OFFSET FAL LAL PCL YINC YSKIP YOFSO YOFSE YIWGTO YIWGTE Regular size (horizontal TV size: 640 pixels, offset ±10 pixels) 212 −4 29 241 2219829 3607 4095 63 64 3849 3362 212 −2 31 243 2219829 3607 4095 68 69 3849 3362 212 0 33 245 2219829 3607 4095 72 73 3849 3362 212 2 35 247 2219829 3607 4095 77 78 3849 3362 212 4 37 249 2219829 3607 4095 81 82 3849 3362 214 −4 28 242 2201206 3639 4095 60 61 3866 3413 214 −2 30 244 2201206 3639 4095 65 66 3866 3413 214 0 32 246 2201206 3639 4095 69 70 3866 3413 214 2 34 248 2201206 3639 4095 74 75 3866 3413 214 4 36 250 2201206 3639 4095 78 79 3866 3413 216 −4 27 243 2178859 3675 4095 57 58 3883 3464 216 −2 29 245 2178859 3675 4095 62 63 3883 3464 216 0 31 247 2178859 3675 4095 66 67 3883 3464 216 2 33 249 2178859 3675 4095 71 72 3883 3464 216 4 35 251 2178859 3675 4095 75 76 3883 3464 218 −4 26 244 2160236 3709 4095 55 56 3900 3515 218 −2 28 246 2160236 3709 4095 59 60 3900 3515 218 0 30 248 2160236 3709 4095 64 65 3900 3515 218 2 32 250 2160236 3709 4095 68 69 3900 3515 218 4 34 252 2160236 3709 4095 73 74 3900 3515 220 −4 25 245 2141613 3741 4095 52 53 3917 3566 220 −2 27 247 2141613 3741 4095 57 58 3917 3566 220 0 29 249 2141613 3741 4095 61 62 3917 3566 220 2 31 251 2141613 3741 4095 65 66 3917 3566 220 4 33 253 2141613 3741 4095 70 71 3917 3566 0 0 0 0 0 0 0 2309218 3471 4095 85 86 3781 3158 Full size (horizontal size: 710 pixels) 241 0 0 0 Small size (horizontal size: 620 pixels) 204 2001 Sep 25 0 37 241 22 Philips Semiconductors Product specification Digital video encoder SAA7102; SAA7103 Table 12 Y scaler programming at NTSC, input frame size: 800 × 600, full anti-flicker filter TV LINE OFFSET FAL LAL PCL YINC YSKIP YOFSO YOFSE YIWGTO YIWGTE Regular size (horizontal TV size: 640 pixels, offset ±10 pixels) 212 −4 29 241 3551726 1443 0 79 79 2769 721 212 −2 31 243 3551726 1443 0 84 84 2769 721 212 0 33 245 3551726 1443 0 90 90 2769 721 212 2 35 247 3551726 1443 0 96 96 2769 721 212 4 37 249 3551726 1443 0 102 102 2769 721 214 −4 28 242 3518354 1457 0 75 75 2776 728 214 −2 30 244 3518354 1457 0 81 81 2776 728 214 0 32 246 3518354 1457 0 86 86 2776 728 214 2 34 248 3518354 1457 0 92 92 2776 728 214 4 36 250 3518354 1457 0 98 98 2776 728 216 −4 27 243 3484982 1470 0 72 72 2782 734 216 −2 29 245 3484982 1470 0 77 77 2782 734 216 0 31 247 3484982 1470 0 82 82 2782 734 216 2 33 249 3484982 1470 0 88 88 2782 734 216 4 35 251 3484982 1470 0 94 94 2782 734 218 −4 26 244 3451610 1484 0 68 68 2789 741 218 −2 28 246 3451610 1484 0 73 73 2789 741 218 0 30 248 3451610 1484 0 79 79 2789 741 218 2 32 250 3451610 1484 0 85 85 2789 741 218 4 34 252 3451610 1484 0 90 90 2789 741 220 −4 25 245 3423006 1497 0 65 65 2796 748 220 −2 27 247 3423006 1497 0 71 71 2796 748 220 0 29 249 3423006 1497 0 76 76 2796 748 220 2 31 251 3423006 1497 0 81 81 2796 748 220 4 33 253 3423006 1497 0 87 87 2796 748 3122659 1642 0 42 42 2867 819 1389 0 106 106 2742 694 Full size (horizontal size: 710 pixels) 241 0 18 259 Small size (horizontal size: 620 pixels) 204 2001 Sep 25 0 37 241 3689981 23 Philips Semiconductors Product specification Digital video encoder SAA7102; SAA7103 Table 13 Y scaler programming at NTSC, input frame size: 800 × 600, half anti-flicker filter TV LINE OFFSET FAL LAL PCL YINC YSKIP YOFSO YOFSE YIWGTO YIWGTE Regular size (horizontal TV size: 640 pixels, offset ±10 pixels) 212 −4 29 241 3551726 2165 2048 79 79 3129 57 212 −2 31 243 3551726 2165 2048 85 85 3129 57 212 0 33 245 3551726 2165 2048 91 91 3129 57 212 2 35 247 3551726 2165 2048 96 96 3129 57 212 4 37 249 3551726 2165 2048 102 102 3129 57 214 −4 28 242 3518354 2185 2048 75 75 3140 68 214 −2 30 244 3518354 2185 2048 81 81 3140 68 214 0 32 246 3518354 2185 2048 87 87 3140 68 214 2 34 248 3518354 2185 2048 92 92 3140 68 214 4 36 250 3518354 2185 2048 98 98 3140 68 216 −4 27 243 3484982 2205 2048 72 72 3150 78 216 −2 29 245 3484982 2205 2048 77 77 3150 78 216 0 31 247 3484982 2205 2048 83 83 3150 78 216 2 33 249 3484982 2205 2048 89 89 3150 78 216 4 35 251 3484982 2205 2048 94 94 3150 78 218 −4 26 244 3451610 2226 2048 68 68 3160 88 218 −2 28 246 3451610 2226 2048 74 74 3160 88 218 0 30 248 3451610 2226 2048 80 80 3160 88 218 2 32 250 3451610 2226 2048 85 85 3160 88 218 4 34 252 3451610 2226 2048 90 90 3160 88 220 −4 25 245 3423006 2246 2048 65 65 3170 98 220 −2 27 247 3423006 2246 2048 71 71 3170 98 220 0 29 249 3423006 2246 2048 76 76 3170 98 220 2 31 251 3423006 2246 2048 81 81 3170 98 220 4 33 253 3423006 2246 2048 87 87 3170 98 3122659 2461 2048 42 42 3277 205 2083 2048 106 106 3089 17 Full size (horizontal size: 710 pixels) 241 0 18 259 Small size (horizontal size: 620 pixels) 204 2001 Sep 25 0 37 241 3689981 24 Philips Semiconductors Product specification Digital video encoder SAA7102; SAA7103 Table 14 Y scaler programming at NTSC, input frame size: 800 × 600, no anti-flicker filter TV LINE OFFSET FAL LAL PCL YINC YSKIP YOFSO YOFSE YIWGTO YIWGTE Regular size (horizontal TV size: 640 pixels, offset ±10 pixels) 212 −4 29 241 3551726 2887 4095 79 80 3490 2282 212 −2 31 243 3551726 2887 4095 85 86 3490 2282 212 0 33 245 3551726 2887 4095 91 92 3490 2282 212 2 35 247 3551726 2887 4095 96 97 3490 2282 212 4 37 249 3551726 2887 4095 102 103 3490 2282 214 −4 28 242 3518354 2912 4095 76 77 3504 2323 214 −2 30 244 3518354 2912 4095 81 82 3504 2323 214 0 32 246 3518354 2912 4095 87 88 3504 2323 214 2 34 248 3518354 2912 4095 92 93 3504 2323 214 4 36 250 3518354 2912 4095 98 99 3504 2323 216 −4 27 243 3484982 2941 4095 72 73 3517 2364 216 −2 29 245 3484982 2941 4095 78 79 3517 2364 216 0 31 247 3484982 2941 4095 83 84 3517 2364 216 2 33 249 3484982 2941 4095 89 90 3517 2364 216 4 35 251 3484982 2941 4095 94 95 3517 2364 218 −4 26 244 3451610 2969 4095 69 70 3531 2405 218 −2 28 246 3451610 2969 4095 74 75 3531 2405 218 0 30 248 3451610 2969 4095 80 81 3531 2405 218 2 32 250 3451610 2969 4095 85 86 3531 2405 218 4 34 252 3451610 2969 4095 90 91 3531 2405 220 −4 25 245 3423006 2994 4095 65 66 3544 2446 220 −2 27 247 3423006 2994 4095 71 72 3544 2446 220 0 29 249 3423006 2994 4095 76 77 3544 2446 220 2 31 251 3423006 2994 4095 82 83 3544 2446 220 4 33 253 3423006 2994 4095 87 88 3544 2446 3122659 3282 4095 42 43 3687 2875 2778 4095 106 107 3436 2119 Full size (horizontal size: 710 pixels) 241 0 18 259 Small size (horizontal size: 620 pixels) 204 2001 Sep 25 0 37 241 3689981 25 Philips Semiconductors Product specification Digital video encoder SAA7102; SAA7103 Table 15 Y scaler programming at PAL, input frame size: 640 × 400, full anti-flicker filter TV LINE OFFSET FAL LAL PCL YINC YSKIP YOFSO YOFSE YIWGTO YIWGTE Regular size (horizontal TV size: 640 pixels, offset ±10 pixels) 255 −4 35 290 1528590 2600 0 52 52 3347 1299 255 −2 37 292 1528590 2602 0 55 55 3347 1299 255 0 39 294 1528590 2602 0 59 59 3347 1299 255 2 41 296 1528590 2602 0 62 62 3347 1299 255 4 43 298 1528590 2602 0 65 65 3347 1299 257 −4 34 291 1516163 2621 0 50 50 3357 1309 257 −2 36 293 1516163 2623 0 53 53 3357 1309 257 0 38 295 1516163 2623 0 57 57 3357 1309 257 2 40 297 1516163 2623 0 60 60 3357 1309 257 4 42 299 1516163 2623 0 63 63 3357 1309 259 −4 33 292 1506842 2641 0 49 49 3367 1319 259 −2 35 294 1506842 2641 0 52 52 3367 1319 259 0 37 296 1506842 2641 0 55 55 3367 1319 259 2 39 298 1506842 2641 0 58 58 3367 1319 259 4 41 300 1506842 2641 0 61 61 3367 1319 261 −4 32 293 1494414 2661 0 47 47 3377 1329 261 −2 34 295 1494414 2661 0 50 50 3377 1329 261 0 36 297 1494414 2661 0 53 53 3377 1329 261 2 38 299 1494414 2661 0 56 56 3377 1329 261 4 40 301 1494414 2661 0 59 59 3377 1329 263 −4 31 294 1481987 2684 0 45 45 3387 1339 263 −2 33 296 1481987 2684 0 48 48 3387 1339 263 0 35 298 1481987 2684 0 51 51 3387 1339 263 2 37 300 1481987 2684 0 54 54 3387 1339 263 4 39 302 1481987 2684 0 57 57 3387 1339 0 0 0 0 0 0 0 1559659 2549 0 63 63 3321 1273 Full size (horizontal size: 702 pixels) 288 0 0 0 Small size (horizontal size: 620 pixels) 250 2001 Sep 25 0 41 291 26 Philips Semiconductors Product specification Digital video encoder SAA7102; SAA7103 Table 16 Y scaler programming at PAL, input frame size: 640 × 400, half anti-flicker filter TV LINE OFFSET FAL LAL PCL YINC YSKIP YOFSO YOFSE YIWGTO YIWGTE Regular size (horizontal TV size: 640 pixels, offset ±10 pixels) 255 −4 35 290 1528590 3346 1170 53 53 3996 924 255 −2 37 292 1528590 3346 1170 56 56 3996 924 255 0 39 294 1528590 3346 1170 59 59 3996 924 255 2 41 296 1528590 3346 1170 62 62 3996 924 255 4 43 298 1528590 3346 1170 65 65 3996 924 257 −4 34 291 1516163 3360 1150 51 51 4012 940 257 −2 36 293 1516163 3360 1150 54 54 4012 940 257 0 38 295 1516163 3360 1150 57 57 4012 940 257 2 40 297 1516163 3360 1150 60 60 4012 940 257 4 42 299 1516163 3360 1150 63 63 4012 940 259 −4 33 292 1506842 3362 1120 49 49 4070 998 259 −2 35 294 1506842 3362 1120 52 52 4070 998 259 0 37 296 1506842 3362 1120 55 55 4070 998 259 2 39 298 1506842 3362 1120 58 58 4070 998 259 4 41 300 1506842 3362 1120 61 61 4070 998 261 −4 32 293 1494414 3378 1100 47 47 4042 970 261 −2 34 295 1494414 3378 1100 50 50 4042 970 261 0 36 297 1494414 3378 1100 53 53 4042 970 261 2 38 299 1494414 3378 1100 56 56 4042 970 261 4 40 301 1494414 3378 1100 59 59 4042 970 263 −4 31 294 1481987 3384 1070 45 45 4057 985 263 −2 33 296 1481987 3384 1070 48 48 4057 985 263 0 35 298 1481987 3384 1070 51 51 4057 985 263 2 37 300 1481987 3384 1070 54 54 4057 985 263 4 39 302 1481987 3384 1070 57 57 4057 985 0 0 0 0 0 0 0 1559659 3322 1240 63 63 3707 1039 Full size (horizontal size: 702 pixels) 288 0 0 0 Small size (horizontal size: 620 pixels) 250 2001 Sep 25 0 41 291 27 Philips Semiconductors Product specification Digital video encoder SAA7102; SAA7103 Table 17 Y scaler programming at PAL, input frame size: 640 × 400, no anti-flicker filter TV LINE OFFSET FAL LAL PCL YINC YSKIP YOFSO YOFSE YIWGTO YIWGTE Regular size (horizontal TV size: 640 pixels, offset ±10 pixels) 255 −4 35 290 1528590 4095 2350 53 53 4092 869 255 −2 37 292 1528590 4095 2350 56 56 4092 869 255 0 39 294 1528590 4095 2350 59 59 4092 869 255 2 41 296 1528590 4095 2350 62 62 4092 869 255 4 43 298 1528590 4095 2350 65 65 4092 869 257 −4 34 291 1516163 4095 2300 51 51 4092 894 257 −2 36 293 1516163 4095 2300 54 54 4092 894 257 0 38 295 1516163 4095 2300 57 57 4092 894 257 2 40 297 1516163 4095 2300 60 60 4092 894 257 4 42 299 1516163 4095 2300 63 63 4092 894 259 −4 33 292 1506842 4093 2250 49 49 4092 919 259 −2 35 294 1506842 4093 2250 52 52 4092 919 259 0 37 296 1506842 4093 2250 55 55 4092 919 259 2 39 298 1506842 4091 2250 58 58 4092 919 259 4 42 301 1506842 4091 2250 63 63 4092 919 261 −4 32 293 1494414 4094 2200 47 47 4092 944 261 −2 34 295 1494414 4094 2200 50 50 4092 944 261 0 36 297 1494414 4094 2200 53 53 4092 944 261 2 38 299 1494414 4093 2200 56 56 4092 944 261 4 40 301 1494414 4093 2200 59 59 4092 944 263 −4 31 294 1481987 4092 2150 45 45 4091 968 263 −2 33 296 1481987 4092 2150 48 48 4091 968 263 0 35 298 1481987 4092 2150 51 51 4091 968 263 2 37 300 1481987 4092 2150 54 54 4091 968 263 4 39 302 1481987 4092 2150 57 57 4091 968 0 0 0 0 0 0 0 1559659 4087 2470 63 63 4089 806 Full size (horizontal size: 702 pixels) 288 0 0 0 Small size (horizontal size: 620 pixels) 250 2001 Sep 25 0 41 291 28 Philips Semiconductors Product specification Digital video encoder SAA7102; SAA7103 Table 18 Y scaler programming at PAL, input frame size: 640 × 480, full anti-flicker filter TV LINE OFFSET FAL LAL PCL YINC YSKIP YOFSO YOFSE YIWGTO YIWGTE Regular size (horizontal TV size: 640 pixels, offset ±10 pixels) 255 −4 35 290 1833066 2168 0 63 63 3131 1083 255 −2 37 292 1833066 2168 0 67 67 3131 1083 255 0 39 294 1833066 2168 0 71 71 3131 1083 255 2 41 296 1833066 2168 0 74 74 3131 1083 255 4 43 298 1833066 2168 0 78 78 3131 1083 257 −4 34 291 1820638 2185 0 61 61 3139 1091 257 −2 36 293 1820638 2185 0 65 65 3139 1091 257 0 38 295 1820638 2185 0 69 69 3139 1091 257 2 40 297 1820638 2185 0 72 72 3139 1091 257 4 42 299 1820638 2185 0 76 76 3139 1091 259 −4 33 292 1805104 2202 0 58 58 3148 1100 259 −2 35 294 1805104 2202 0 62 62 3148 1100 259 0 37 296 1805104 2202 0 66 66 3148 1100 259 2 39 298 1805104 2204 0 70 70 3148 1100 259 4 41 300 1805104 2202 0 73 73 3148 1100 261 −4 32 293 1792676 2219 0 56 56 3156 1108 261 −2 34 295 1792676 2219 0 60 60 3156 1108 261 0 36 297 1792676 2219 0 64 64 3156 1108 261 2 38 299 1792676 2219 0 67 67 3156 1108 261 4 40 301 1792676 2219 0 71 71 3156 1108 263 −4 31 294 1777142 2238 0 54 54 3165 1117 263 −2 33 296 1777142 2238 0 58 58 3165 1117 263 0 35 298 1777142 2238 0 61 61 3165 1117 263 2 37 300 1777142 2238 0 65 65 3165 1117 263 4 39 302 1777142 2238 0 69 69 3165 1117 0 0 0 0 0 0 0 1870348 2125 0 76 76 3110 1062 Full size (horizontal size: 702 pixels) 288 0 0 0 Small size (horizontal size: 620 pixels) 250 2001 Sep 25 0 41 291 29 Philips Semiconductors Product specification Digital video encoder SAA7102; SAA7103 Table 19 Y scaler programming at PAL, input frame size: 640 × 480, half anti-flicker filter TV LINE OFFSET FAL LAL PCL YINC YSKIP YOFSO YOFSE YIWGTO YIWGTE Regular size (horizontal TV size: 640 pixels, offset ±10 pixels) 255 −4 35 290 1833066 3254 2048 63 63 3673 601 255 −2 37 292 1833066 3254 2048 67 67 3673 601 255 0 39 294 1833066 3254 2048 71 71 3673 601 255 2 41 296 1833066 3254 2048 75 75 3673 601 255 4 43 298 1833066 3254 2048 79 79 3673 601 257 −4 34 291 1820638 3277 2048 61 61 3686 614 257 −2 36 293 1820638 3277 2048 65 65 3686 614 257 0 38 295 1820638 3277 2048 69 69 3686 614 257 2 40 297 1820638 3277 2048 72 72 3686 614 257 4 42 299 1820638 3277 2048 76 76 3686 614 259 −4 33 292 1805104 3305 2048 59 59 3698 626 259 −2 35 294 1805104 3305 2048 63 63 3698 626 259 0 37 296 1805104 3305 2048 66 66 3698 626 259 2 39 298 1805104 3305 2048 70 70 3698 626 259 4 41 300 1805104 3305 2048 74 74 3698 626 261 −4 32 293 1792676 3328 2048 57 57 3711 639 261 −2 34 295 1792676 3328 2048 60 60 3711 639 261 0 36 297 1792676 3328 2048 64 64 3711 639 261 2 38 299 1792676 3328 2048 68 68 3711 639 261 4 40 301 1792676 3328 2048 71 71 3711 639 263 −4 31 294 1777142 3354 2048 54 54 3724 652 263 −2 33 296 1777142 3354 2048 58 58 3724 652 263 0 35 298 1777142 3354 2048 61 61 3724 652 263 2 37 300 1777142 3354 2048 65 65 3724 652 263 4 39 302 1777142 3354 2048 69 69 3724 652 0 0 0 0 0 0 0 1870348 3108 1890 76 76 3600 607 Full size (horizontal size: 702 pixels) 288 0 0 0 Small size (horizontal size: 620 pixels) 250 2001 Sep 25 0 41 291 30 Philips Semiconductors Product specification Digital video encoder SAA7102; SAA7103 Table 20 Y scaler programming at PAL, input frame size: 640 × 480, no anti-flicker filter TV LINE OFFSET FAL LAL PCL YINC YSKIP YOFSO YOFSE YIWGTO YIWGTE Regular size (horizontal TV size: 640 pixels, offset ±10 pixels) 255 −4 35 290 1833066 4093 3630 64 64 4091 228 255 −2 37 292 1833066 4093 3630 67 67 4091 228 255 0 39 294 1833066 4093 3630 71 71 4091 228 255 2 41 296 1833066 4093 3630 75 75 4091 228 255 4 43 298 1833066 4093 3630 79 79 4091 228 257 −4 34 291 1820638 4090 3570 61 61 4091 258 257 −2 36 293 1820638 4090 3570 65 65 4091 258 257 0 38 295 1820638 4090 3570 69 69 4091 258 257 2 40 297 1820638 4090 3570 73 73 4091 258 257 4 42 299 1820638 4090 3570 76 76 4091 258 259 −4 33 292 1805104 4092 3510 59 59 4091 288 259 −2 35 294 1805104 4092 3510 63 63 4091 288 259 0 37 296 1805104 4092 3510 66 66 4091 288 259 2 39 298 1805104 4092 3510 70 70 4091 288 259 4 41 300 1805104 4092 3510 74 74 4091 288 261 −4 32 293 1792676 4088 3450 57 57 4091 318 261 −2 34 295 1792676 4088 3450 60 60 4091 318 261 0 36 297 1792676 4088 3450 64 64 4091 318 261 2 38 299 1792676 4088 3450 68 68 4091 318 261 4 40 301 1792676 4088 3450 71 71 4091 318 263 −4 31 294 1777142 4095 3400 54 54 4095 345 263 −2 33 296 1777142 4095 3400 58 58 4095 345 263 0 35 298 1777142 4095 3400 62 62 4095 345 263 2 37 300 1777142 4095 3400 65 65 4095 345 263 4 39 302 1777142 4095 3400 69 69 4095 345 0 0 0 0 0 0 0 1870348 4088 3780 76 76 4090 152 Full size (horizontal size: 702 pixels) 288 0 0 0 Small size (horizontal size: 620 pixels) 250 2001 Sep 25 0 41 291 31 Philips Semiconductors Product specification Digital video encoder SAA7102; SAA7103 Table 21 Y scaler programming at PAL, input frame size: 800 × 600, full anti-flicker filter TV LINE OFFSET FAL LAL PCL YINC YSKIP YOFSO YOFSE YIWGTO YIWGTE Regular size (horizontal TV size: 640 pixels, offset ±10 pixels) 255 −4 35 290 2930917 1736 0 79 79 2915 867 255 −2 37 292 2930917 1736 0 84 84 2915 867 255 0 39 294 2930917 1736 0 89 89 2915 867 255 2 41 296 2930917 1736 0 93 93 2915 867 255 4 43 298 2930917 1736 0 98 98 2915 867 257 −4 34 291 2911033 1749 0 77 77 2922 874 257 −2 36 293 2911033 1749 0 81 81 2922 874 257 0 38 295 2911033 1749 0 86 86 2922 874 257 2 40 297 2911033 1749 0 91 91 2922 874 257 4 42 299 2911033 1749 0 95 95 2922 874 259 −4 33 292 2887172 1763 0 73 73 2929 881 259 −2 35 294 2887172 1763 0 78 78 2929 881 259 0 37 296 2887172 1763 0 83 83 2929 881 259 2 39 298 2887172 1763 0 87 87 2929 881 259 4 41 300 2887172 1763 0 92 92 2929 881 261 −4 32 293 2863311 1778 0 71 71 2935 887 261 −2 34 295 2863311 1778 0 75 75 2935 887 261 0 36 297 2863311 1778 0 80 80 2935 887 261 2 38 299 2863311 1778 0 85 85 2935 887 261 4 40 301 2863311 1778 0 89 89 2935 887 263 −4 31 294 2843427 1790 0 68 68 2942 894 263 −2 33 296 2843427 1790 0 72 72 2942 894 263 0 35 298 2843427 1790 0 77 77 2942 894 263 2 37 300 2843427 1790 0 82 82 2942 894 263 4 39 302 2843427 1790 0 86 86 2942 894 2596864 1960 0 43 43 3027 979 1701 0 95 95 2898 850 Full size (horizontal size: 702 pixels) 288 0 22 310 Small size (horizontal size: 620 pixels) 250 2001 Sep 25 0 41 291 2990569 32 Philips Semiconductors Product specification Digital video encoder SAA7102; SAA7103 Table 22 Y scaler programming at PAL, input frame size: 800 × 600, half anti-flicker filter TV LINE OFFSET FAL LAL PCL YINC YSKIP YOFSO YOFSE YIWGTO YIWGTE Regular size (horizontal TV size: 640 pixels, offset ±10 pixels) 255 −4 35 290 2930917 2604 2048 80 80 3349 277 255 −2 37 292 2930917 2604 2048 84 84 3349 277 255 0 39 294 2930917 2604 2048 89 89 3349 277 255 2 41 296 2930917 2604 2048 94 94 3349 277 255 4 43 298 2930917 2604 2048 98 98 3349 277 257 −4 34 291 2911033 2625 2048 77 77 3359 287 257 −2 36 293 2911033 2625 2048 82 82 3359 287 257 0 38 295 2911033 2625 2048 86 86 3359 287 257 2 40 297 2911033 2625 2048 91 91 3359 287 257 4 42 299 2911033 2625 2048 96 96 3359 287 259 −4 33 292 2887172 2645 2048 74 74 3369 297 259 −2 35 294 2887172 2645 2048 79 79 3369 297 259 0 37 296 2887172 2645 2048 83 83 3369 297 259 2 39 298 2887172 2645 2048 88 88 3369 297 259 4 41 300 2887172 2645 2048 92 92 3369 297 261 −4 32 293 2863311 2666 2048 71 71 3379 307 261 −2 34 295 2863311 2666 2048 75 75 3379 307 261 0 36 297 2863311 2666 2048 80 80 3379 307 261 2 38 299 2863311 2666 2048 85 85 3379 307 261 4 40 301 2863311 2666 2048 89 89 3379 307 263 −4 31 294 2843427 2686 2048 68 68 3390 318 263 −2 33 296 2843427 2686 2048 73 73 3390 318 263 0 35 298 2843427 2686 2048 77 77 3390 318 263 2 37 300 2843427 2686 2048 82 82 3390 318 263 4 39 302 2843427 2686 2048 86 86 3390 318 2596864 2940 2048 43 43 3517 445 2553 2048 96 96 3323 251 Full size (horizontal size: 702 pixels) 288 0 22 310 Small size (horizontal size: 620 pixels) 250 2001 Sep 25 0 41 291 2990569 33 Philips Semiconductors Product specification Digital video encoder SAA7102; SAA7103 Table 23 Y scaler programming at PAL, input frame size: 800 × 600, no anti-flicker filter TV LINE OFFSET FAL LAL PCL YINC YSKIP YOFSO YOFSE YIWGTO YIWGTE Regular size (horizontal TV size: 640 pixels, offset ±10 pixels) 255 −4 35 290 2930917 3473 4095 80 81 3783 3161 255 −2 37 292 2930917 3473 4095 84 85 3783 3161 255 0 39 294 2930917 3473 4095 89 90 3783 3161 255 2 41 296 2930917 3473 4095 94 95 3783 3161 255 4 43 298 2930917 3473 4095 99 100 3783 3161 257 −4 34 291 2911033 3500 4095 77 78 3796 3202 257 −2 36 293 2911033 3500 4095 82 83 3796 3202 257 0 38 295 2911033 3500 4095 87 88 3796 3202 257 2 40 297 2911033 3500 4095 91 92 3796 3202 257 4 42 299 2911033 3500 4095 96 97 3796 3202 259 −4 33 292 2887172 3527 4095 74 75 3810 3242 259 −2 35 294 2887172 3527 4095 79 80 3810 3242 259 0 37 296 2887172 3527 4095 83 84 3810 3242 259 2 39 298 2887172 3527 4095 88 89 3810 3242 259 4 41 300 2887172 3527 4095 93 94 3810 3242 261 −4 32 293 2863311 3555 4095 71 72 3823 3284 261 −2 34 295 2863311 3555 4095 76 77 3823 3284 261 0 36 297 2863311 3555 4095 80 81 3823 3284 261 2 38 299 2863311 3555 4095 85 86 3823 3284 261 4 40 301 2863311 3555 4095 89 90 3823 3284 263 −4 31 294 2843427 3582 4095 68 69 3837 3324 263 −2 33 296 2843427 3582 4095 73 74 3837 3324 263 0 35 298 2843427 3582 4095 78 79 3837 3324 263 2 37 300 2843427 3582 4095 82 83 3837 3324 263 4 39 302 2843427 3582 4095 87 88 3837 3324 2596864 3923 4095 44 45 4007 3836 3405 4095 96 97 3748 3059 Full size (horizontal size: 702 pixels) 288 0 22 310 Small size (horizontal size: 620 pixels) 250 2001 Sep 25 0 41 291 2990569 34 Philips Semiconductors Product specification Digital video encoder SAA7102; SAA7103 Table 24 “ITU-R BT.601” signal component levels Table 26 Pin assignment for input format 1 and 2 SIGNALS(1) 5 + 5 + 5 (5 + 6 + 5) BIT 4 : 4 : 4 NON-INTERLACED RGB COLOUR Y CB CR R G B White 235 128 128 235 235 235 Yellow 210 16 146 235 235 16 Cyan 170 166 16 16 235 235 Green 145 54 34 16 235 16 Magenta 106 202 222 235 16 235 Red 81 90 240 235 16 16 Blue 41 240 110 16 16 235 Black 16 128 128 16 16 16 FALLING CLOCK EDGE PIN Note RISING CLOCK EDGE PD7 G2(G2) R4(X) PD6 G1(G1) R3(R4) PD5 G0(G0) R2(R3) PD4 B4(B4) R1(R2) PD3 B3(B3) R0(R1) PD2 B2(B2) G5(R0) PD1 B1(B1) G4(G4) PD0 B0(B0) G3(G3) 1. Transformation: a) R = Y + 1.3707 × (CR − 128) Table 27 Pin assignment for input format 3 b) G = Y − 0.3365 × (CB − 128) − 0.6982 × (CR − 128) 8 + 8 + 8-BIT 4 : 2 : 2 NON-INTERLACED CB-Y-CR c) B = Y + 1.7324 × (CB − 128). PIN Table 25 Pin assignment for input format 0 8 + 8 + 8-BIT 4 : 4 : 4 NON-INTERLACED RGB/CB-Y-CR FALLING CLOCK EDGE n RISING CLOCK EDGE n FALLING CLOCK EDGE n+1 RISING CLOCK EDGE n+1 PD7 CB7(0) Y7(0) CR7(0) Y7(1) CB6(0) Y6(0) CR6(0) Y6(1) FALLING CLOCK EDGE RISING CLOCK EDGE PD6 PD5 CB5(0) Y5(0) CR5(0) Y5(1) PD11 G3/Y3 R7/CR7 PD4 CB4(0) Y4(0) CR4(0) Y4(1) PD10 G2/Y2 R6/CR6 PD3 CB3(0) Y3(0) CR3(0) Y3(1) PD9 G1/Y1 R5/CR5 PD2 CB2(0) Y2(0) CR2(0) Y2(1) PD8 G0/Y0 R4/CR4 PD1 CB1(0) Y1(0) CR1(0) Y1(1) PD7 B7/CB7 R3/CR3 PD0 CB0(0) Y0(0) CR0(0) Y0(1) PD6 B6/CB6 R2/CR2 PD5 B5/CB5 R1/CR1 PD4 B4/CB4 R0/CR0 PD3 B3/CB3 G7/Y7 PD2 B2/CB2 G6/Y6 PD1 B1/CB1 G5/Y5 PD0 B0/CB0 G4/Y4 PIN 2001 Sep 25 35 Philips Semiconductors Product specification Digital video encoder SAA7102; SAA7103 Table 28 Pin assignment for input format 4 Table 30 Pin assignment for input format 6 8 + 8 + 8-BIT 4 : 2 : 2 INTERLACED CB-Y-CR (ITU-R BT.656, 27 MHz CLOCK) PIN RISING CLOCK EDGE n RISING CLOCK EDGE n+1 RISING CLOCK EDGE n+2 RISING CLOCK EDGE n+3 PD7 CB7(0) Y7(0) CR7(0) Y7(1) PD6 CB6(0) Y6(0) CR6(0) Y6(1) PD5 CB5(0) Y5(0) CR5(0) Y5(1) PD4 CB4(0) Y4(0) CR4(0) Y4(1) PD3 CB3(0) Y3(0) CR3(0) Y3(1) PD2 CB2(0) Y2(0) CR2(0) Y2(1) PD1 CB1(0) Y1(0) CR1(0) Y1(1) PD0 CB0(0) Y0(0) CR0(0) Y0(1) 8 + 8 + 8-BIT 4 : 4 : 4 NON-INTERLACED RGB/CB-Y-CR PIN Table 29 Pin assignment for input format 5; note 1 8-BIT NON-INTERLACED INDEX COLOUR FALLING CLOCK EDGE RISING CLOCK EDGE PD11 X X PD10 X X PD9 X X PD8 X X PD7 INDEX7 X PD6 INDEX6 X PD5 INDEX5 X PD4 INDEX4 X PD3 INDEX3 X PD2 INDEX2 X PD1 INDEX1 X PD0 INDEX0 X PIN Note 1. X = don’t care. 2001 Sep 25 36 FALLING CLOCK EDGE RISING CLOCK EDGE PD11 G4/Y4 R7/CR7 PD10 G3/Y3 R6/CR6 PD9 G2/Y2 R5/CR5 PD8 B7/CB7 R4/CR4 PD7 B6/CB6 R3/CR3 PD6 B5/CB5 G7/Y7 PD5 B4/CB4 G6/Y6 PD4 B3/CB3 G5/Y5 PD3 G0/Y0 R2/CR2 PD2 B2/CB2 R1/CR1 PD1 B1/CB1 R0/CR0 PD0 B0/CB0 G1/Y1 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Table 31 Slave receiver (slave address 88H) REGISTER FUNCTION Status byte (read only) Null Common DAC adjust fine R DAC adjust coarse G DAC adjust coarse 37 D6 D5 D4 D3 D2 D1 D0 00 01 to 15 16 17 18 VER2 VER1 VER0 CCRDO CCRDE (1) FSEQ O_E (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) RDACC4 DACF3 RDACC3 DACF2 RDACC2 DACF1 RDACC1 DACF0 RDACC0 (1) (1) (1) 19 1A 1B 1C 26 27 28 29 2A 2B 2C 2D 2E to 37 38 39 3A 54 (1) (1) (1) MSMT7 MSM CID7 WSS7 WSSON MSMT6 MSMT5 GDACC4 BDACC4 MSMT4 GDACC3 BDACC3 MSMT3 (1) (1) (1) (1) CID6 WSS6 (1) (1) SRES CG07 CG15 CGEN VBSEN (1) CG06 CG14 CID5 WSS5 WSS13 BS5 BE5 CG05 CG13 CID4 WSS4 WSS12 BS4 BE4 CG04 CG12 (1) (1) (1) GDACC1 BDACC1 MSMT1 GCOMP CID1 WSS1 WSS9 BS1 BE1 CG01 CG09 CG17 GDACC0 BDACC0 MSMT0 BCOMP CID0 WSS0 WSS8 BS0 BE0 CG00 CG08 CG16 CVBSEN1 CVBSEN0 CEN CID3 WSS3 WSS11 BS3 BE3 CG03 CG11 CG19 ENCOFF GDACC2 BDACC2 MSMT2 RCOMP CID2 WSS2 WSS10 BS2 BE2 CG02 CG10 CG18 CLK2EN (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) CBENB VPSEN (1) (1) GY4 GCD4 SYMP GY3 GCD3 DEMOFF GY2 GCD2 CSYNC GY1 GCD1 Y2C GY0 GCD0 UV2C (1) (1) (1) (1) (1) VPS57 VPS117 VPS127 VPS137 VPS147 CHPS7 GAINU7 VPS56 VPS116 VPS126 VPS136 VPS146 CHPS6 GAINU6 VPS55 VPS115 VPS125 VPS135 VPS145 CHPS5 GAINU5 VPS54 VPS114 VPS124 VPS134 VPS144 CHPS4 GAINU4 VPS53 VPS113 VPS123 VPS133 VPS143 CHPS3 GAINU3 VPS52 VPS112 VPS122 VPS132 VPS142 CHPS2 GAINU2 EDGE2 VPS51 VPS111 VPS121 VPS131 VPS141 CHPS1 GAINU1 EDGE1 VPS50 VPS110 VPS120 VPS130 VPS140 CHPS0 GAINU0 55 56 57 58 59 5A 5B (1) Product specification VPS byte 5 VPS byte 11 VPS byte 12 VPS byte 13 VPS byte 14 Chrominance phase Gain U D7 SAA7102; SAA7103 B DAC adjust coarse MSM threshold Monitor sense mode Chip ID (02B or 03B, read only) Wide screen signal Wide screen signal Real-time control, burst start Sync reset enable, burst end Copy generation 0 Copy generation 1 CG enable, copy generation 2 Output port control Null Gain luminance for RGB Gain colour difference for RGB Input port control 1 VPS enable, input control 2 SUB ADDR. (HEX) Philips Semiconductors Bit allocation map Digital video encoder 2001 Sep 25 7.19 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... D7 D6 D5 D4 D3 D2 D1 D0 GAINV4 BLCKL4 BLNNL4 BLNVB4 GAINV3 BLCKL3 BLNNL3 BLNVB3 GAINV2 BLCKL2 BLNNL2 BLNVB2 GAINV1 BLCKL1 BLNNL1 BLNVB1 GAINV0 BLCKL0 BLNNL0 BLNVB0 38 GAINV7 GAINV6 5D 5E 5F 60 61 62 63 64 65 GAINU8 GAINV8 CCRS1 (1) CCRS0 GAINV5 BLCKL5 BLNNL5 BLNVB5 (1) (1) (1) (1) (1) (1) (1) (1) DOWND (1) BSTA5 FSC05 FSC13 FSC21 YGS BSTA4 FSC04 FSC12 FSC20 (1) FSC07 FSC15 FSC23 DOWNA BSTA6 FSC06 FSC14 FSC22 BSTA3 FSC03 FSC11 FSC19 SCBW BSTA2 FSC02 FSC10 FSC18 PAL BSTA1 FSC01 FSC09 FSC17 FISE BSTA0 FSC00 FSC08 FSC16 Subcarrier 3 Line 21 odd 0 Line 21 odd 1 Line 21 even 0 Line 21 even 1 Null Trigger control Trigger control Multi control Closed Caption, teletext enable Active display window horizontal start Active display window horizontal end MSBs ADWH TTX request horizontal start TTX request horizontal delay 66 67 68 69 6A 6B 6C 6D 6E 6F 70 FSC31 L21O07 L21O17 L21E07 L21E17 FSC30 L21O06 L21O16 L21E06 L21E16 FSC29 L21O05 L21O15 L21E05 L21E15 FSC28 L21O04 L21O14 L21E04 L21E14 FSC27 L21O03 L21O13 L21E03 L21E13 FSC26 L21O02 L21O12 L21E02 L21E12 FSC25 L21O01 L21O11 L21E01 L21E11 FSC24 L21O00 L21O10 L21E00 L21E10 (1) (1) (1) (1) (1) (1) (1) (1) HTRIG7 HTRIG10 CCEN1 ADWHS7 HTRIG6 HTRIG9 BLCKON CCEN0 ADWHS6 HTRIG5 HTRIG8 PHRES1 TTXEN ADWHS5 HTRIG4 VTRIG4 PHRES0 SCCLN4 ADWHS4 HTRIG3 VTRIG3 LDEL1 SCCLN3 ADWHS3 HTRIG2 VTRIG2 LDEL0 SCCLN2 ADWHS2 HTRIG1 VTRIG1 FLC1 SCCLN1 ADWHS1 HTRIG0 VTRIG0 FLC0 SCCLN0 ADWHS0 71 ADWHE7 ADWHE6 ADWHE5 ADWHE4 ADWHE3 ADWHE2 ADWHE1 ADWHE0 72 73 74 (1) ADWHE9 TTXHS5 ADWHE8 TTXHS4 (1) TTXHS7 ADWHE10 TTXHS6 (1) (1) (1) (1) ADWHS10 TTXHS2 TTXHD2 ADWHS9 TTXHS1 TTXHD1 ADWHS8 TTXHS0 TTXHD0 CSYNC advance TTX odd request vertical start TTX odd request vertical end TTX even request vertical start TTX even request vertical end 75 76 77 78 79 CSYNCA4 TTXOVS7 TTXOVE7 TTXEVS7 TTXEVE7 (1) (1) (1) TTXOVS2 TTXOVE2 TTXEVS2 TTXEVE2 TTXOVS1 TTXOVE1 TTXEVS1 TTXEVE1 TTXOVS0 TTXOVE0 TTXEVS0 TTXEVE0 (1) (1) (1) CSYNCA3 CSYNCA2 CSYNCA1 TTXOVS6 TTXOVS5 TTXOVS4 TTXOVE6 TTXOVE5 TTXOVE4 TTXEVS6 TTXEVS5 TTXEVS4 TTXEVE6 TTXEVE5 TTXEVE4 TTXHS3 TTXHD3 CSYNCA0 TTXOVS3 TTXOVE3 TTXEVS3 TTXEVE3 Product specification 5C Gain U MSB, black level Gain V MSB, blanking level CCR, blanking level VBI Null Standard control Burst amplitude Subcarrier 0 Subcarrier 1 Subcarrier 2 SAA7102; SAA7103 Gain V Philips Semiconductors SUB ADDR. (HEX) Digital video encoder 2001 Sep 25 REGISTER FUNCTION This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... D7 D6 D5 D4 D3 D2 D1 D0 39 7A FAL7 FAL6 FAL5 FAL4 FAL3 FAL2 FAL1 FAL0 Last active line TTX mode, MSB vertical Null Disable TTX line Disable TTX line FIFO status (read only) Pixel clock 0 Pixel clock 1 Pixel clock 2 7B 7C 7D 7E 7F 80 81 82 83 LAL7 TTX60 LAL6 LAL8 LAL5 (1) LAL4 FAL8 LAL3 TTXEVE8 LAL2 TTXOVE8 LAL1 TTXEVS8 LAL0 TTXOVS8 (1) (1) (1) (1) (1) (1) (1) (1) LINE12 LINE20 LINE11 LINE19 LINE10 LINE18 LINE9 LINE17 LINE8 LINE16 LINE7 LINE15 (1) (1) (1) (1) (1) (1) PCL07 PCL15 PCL23 PCL06 PCL14 PCL22 PCL05 PCL13 PCL21 PCL04 PCL12 PCL20 PCL03 PCL11 PCL19 PCL02 PCL10 PCL18 LINE6 LINE14 OVFL PCL01 PCL09 PCL17 LINE5 LINE13 UDFL PCL00 PCL08 PCL16 (1) (1) (1) (1) (1) (1) (1) (1) XOFS7 XPIX7 YOFSO7 YOFSE7 YOFSE9 YPIX7 EFS HFS HLEN7 IDEL3 XINC7 YINC7 YINC11 XOFS6 XPIX6 YOFSO6 YOFSE6 YOFSE8 YPIX6 PCBN VFS HLEN6 IDEL2 XINC6 YINC6 YINC10 XOFS5 XPIX5 YOFSO5 YOFSE5 YOFSO9 YPIX5 SLAVE OFS HLEN5 IDEL1 XINC5 YINC5 YINC9 XOFS4 XPIX4 YOFSO4 YOFSE4 YOFSO8 YPIX4 ILC PFS HLEN4 IDEL0 XINC4 YINC4 YINC8 XOFS3 XPIX3 YOFSO3 YOFSE3 XPIX9 YPIX3 YFIL OVS HLEN3 XOFS2 XPIX2 YOFSO2 YOFSE2 XPIX8 YPIX2 HSL PVS HLEN2 HLEN10 XINC2 YINC2 XINC10 XOFS1 XPIX1 YOFSO1 YOFSE1 XOFS9 YPIX1 YPIX9 OHS HLEN1 HLEN9 XINC1 YINC1 XINC9 XOFS0 XPIX0 YOFSO0 YOFSE0 XOFS8 YPIX0 YPIX8 PHS HLEN0 HLEN8 XINC0 YINC0 XINC8 Border colour Y 84 to 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 YIWGTO7 YIWGTO6 YIWGTO5 YIWGTE7 YIWGTE6 YIWGTE5 YIWGTE11 YIWGTE10 YIWGTE9 YSKIP7 YSKIP6 YSKIP5 (1) (1) BLEN BCY7 BCY6 BCY5 (1) XINC3 YINC3 XINC11 YIWGTO4 YIWGTO3 YIWGTO2 YIWGTO1 YIWGTE4 YIWGTE3 YIWGTE2 YIWGTE1 YIWGTE8 YIWGTO11 YIWGTO10 YIWGTO9 YSKIP4 YSKIP3 YSKIP2 YSKIP1 (1) YSKIP11 YSKIP10 YSKIP9 BCY4 BCY3 BCY2 BCY1 YIWGTO0 YIWGTE0 YIWGTO8 YSKIP0 YSKIP8 BCY0 Product specification Null Horizontal offset Pixel number Vertical offset odd Vertical offset even MSBs Line number Scaler CTRL, MCB YPIX Sync control Line length Input delay, MSB line length Horizontal increment Vertical increment MSBs vertical and horizontal increment Weighting factor odd Weighting factor even Weighting factor MSB Vertical line skip Blank enable for NI-bypass, vertical line skip MSB SAA7102; SAA7103 First active line Philips Semiconductors SUB ADDR. (HEX) Digital video encoder 2001 Sep 25 REGISTER FUNCTION This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... D6 D5 D4 D3 D2 D1 D0 Border colour U A3 BCU7 BCU6 BCU5 BCU4 BCU3 BCU2 BCU1 BCU0 Border colour V Cursor colour 1 R Cursor colour 1 G A4 F0 F1 BCV7 CC1R7 CC1G7 BCV6 CC1R6 CC1G6 BCV5 CC1R5 CC1G5 BCV4 CC1R4 CC1G4 BCV3 CC1R3 CC1G3 BCV2 CC1R2 CC1G2 BCV1 CC1R1 CC1G1 BCV0 CC1R0 CC1G0 Cursor colour 1 B Cursor colour 2 R Cursor colour 2 G Cursor colour 2 B Auxiliary cursor colour R Auxiliary cursor colour G Auxiliary cursor colour B Horizontal cursor position Horizontal hot spot, MSB XCP Vertical cursor position Vertical hot spot, MSB YCP Input path control Cursor bit map Colour look-up table F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF CC1B7 CC2R7 CC2G7 CC2B7 AUXR7 AUXG7 AUXB7 XCP7 XHS4 YCP7 YHS4 LUTOFF CC1B6 CC2R6 CC2G6 CC2B6 AUXR6 AUXG6 AUXB6 XCP6 XHS3 YCP6 YHS3 CMODE CC1B5 CC2R5 CC2G5 CC2B5 AUXR5 AUXG5 AUXB5 XCP5 XHS2 YCP5 YHS2 LUTL CC1B2 CC2R2 CC2G2 CC2B2 AUXR2 AUXG2 AUXB2 XCP2 XCP10 YCP2 CC1B1 CC2R1 CC2G1 CC2B1 AUXR1 AUXG1 AUXB1 XCP1 XCP9 YCP1 YCP9 MATOFF CC1B0 CC2R0 CC2G0 CC2B0 AUXR0 AUXG0 AUXB0 XCP0 XCP8 YCP0 YCP8 DFOFF CC1B4 CC1B3 CC2R4 CC2R3 CC2G4 CC2G3 CC2B4 CC2B3 AUXR4 AUXR3 AUXG4 AUXG3 AUXB4 AUXB3 XCP4 XCP3 XHS1 XHS0 YCP4 YCP3 YHS1 YHS0 IF2 IF1 RAM address (see Table 105) RAM address (see Table 106) (1) IF0 Philips Semiconductors 40 D7 Digital video encoder 2001 Sep 25 SUB ADDR. (HEX) REGISTER FUNCTION Note 1. All unused control bits must be programmed with logic 0 to ensure compatibility to future enhancements. Product specification SAA7102; SAA7103 Philips Semiconductors Product specification Digital video encoder 7.20 SAA7102; SAA7103 I2C-bus format Table 32 I2C-bus write access to control registers; see Table 37 S 1 0 0 0 1 0 0 0 A SUBADDRESS A DATA 0 A -------- DATA n A P -------- DATA n A P Table 33 I2C-bus write access to cursor bit map (subaddress FEH); see Table 37 S 1 0 0 0 1 0 0 0 A FEH A RAM ADDRESS A DATA 0 A Table 34 I2C-bus write access to colour look-up table (subaddress FFH); see Table 37 S 1 0 0 0 1 0 0 0 A FFH A RAM ADDRESS A DATA 0R A DATA 0G A DATA 0B A -------- P Am P Table 35 I2C-bus read access to control registers; see Table 37 S 1 0 0 0 1 0 0 0 A SUBADDRESS A Sr 1 0 0 0 1 0 0 1 A DATA 0 Am -------- DATA n Table 36 I2C-bus read access to cursor bit map or colour LUT; see Table 37 S 1 0 0 0 1 0 0 0 A FEH or FFH A RAM ADDRESS A Sr 1 0 0 0 1 0 0 1 A DATA 0 Am -------- DATA n Am P Table 37 Explanations of Tables 32 to 36 CODE S DESCRIPTION START condition Sr repeated START condition 1 0 0 0 1 0 0 X; note 1 slave address A acknowledge generated by the slave Am acknowledge generated by the master SUBADDRESS; note 2 subaddress byte DATA data byte -------- continued data bytes and acknowledges P STOP condition RAM ADDRESS start address for RAM access Notes 1. X is the read/write control bit; X = logic 0 is order to write; X = logic 1 is order to read. 2. If more than 1 byte of DATA is transmitted, then auto-increment of the subaddress is performed. 2001 Sep 25 41 Philips Semiconductors Product specification Digital video encoder 7.21 SAA7102; SAA7103 Slave receiver Table 38 Subaddress 16H DATA BYTE DACF DESCRIPTION output level adjustment fine in 1% steps for all DACs; default after reset is 00H; see Table 39 Table 39 Fine adjustment of DAC output voltage BINARY GAIN (%) 0111 7 0110 6 0101 5 0100 4 0011 3 0010 2 0001 1 0000 0 1000 0 1001 −1 1010 −2 1011 −3 1100 −4 1101 −5 1110 −6 1111 −7 Table 40 Subaddresses 17H to 19H DATA BYTE DESCRIPTION RDACC output level coarse adjustment for RED DAC; default after reset is 1BH for output of C signal 00000b ≡ 0.585 V to 11111b ≡ 1.240 V at 37.5 Ω nominal for full-scale conversion GDACC output level coarse adjustment for GREEN DAC; default after reset is 1BH for output of VBS signal 00000b ≡ 0.585 V to 11111b ≡ 1.240 V at 37.5 Ω nominal for full-scale conversion BDACC output level coarse adjustment for BLUE DAC; default after reset is 1FH for output of CVBS signal 00000b ≡ 0.585 V to 11111b ≡ 1.240 V at 37.5 Ω nominal for full-scale conversion Table 41 Subaddress 1AH DATA BYTE MSMT 2001 Sep 25 DESCRIPTION monitor sense mode threshold for DAC output voltage, should be set to 70 42 Philips Semiconductors Product specification Digital video encoder SAA7102; SAA7103 Table 42 Subaddress 1BH LOGIC LEVEL DESCRIPTION 0 monitor sense mode off; RCOMP, GCOMP and BCOMP bits are not valid; default after reset 1 monitor sense mode on RCOMP (read only) 0 check comparator at DAC on pin 27 is active, output is loaded 1 check comparator at DAC on pin 27 is inactive, output is not loaded GCOMP (read only) 0 check comparator at DAC on pin 28 is active, output is loaded 1 check comparator at DAC on pin 28 is inactive, output is not loaded BCOMP (read only) 0 check comparator at DAC on pin 30 is active, output is loaded 1 check comparator at DAC on pin 30 is inactive, output is not loaded DATA BYTE MSM Table 43 Subaddresses 26H and 27H DATA BYTE WSS LOGIC LEVEL − DESCRIPTION wide screen signalling bits 3 to 0 = aspect ratio 7 to 4 = enhanced services 10 to 8 = subtitles 13 to 11 = reserved WSSON 0 wide screen signalling output is disabled; default after reset 1 wide screen signalling output is enabled Table 44 Subaddress 28H DATA BYTE BS LOGIC LEVEL − DESCRIPTION REMARKS starting point of burst in clock cycles PAL: BS = 33 (21H); default after reset if strapping pin 13 tied to HIGH NTSC: BS = 25 (19H); default after reset if strapping pin 13 tied to LOW Table 45 Subaddress 29H DATA BYTE SRES BE LOGIC LEVEL DESCRIPTION REMARKS 0 pin 23 accepts a teletext bit stream (TTX) default after reset 1 pin 23 accepts a sync reset input (SRES) a HIGH impulse resets synchronization of the encoder (first field, first line) − ending point of burst in clock cycles PAL: BE = 29 (1DH); default after reset if strapping pin 13 tied to HIGH NTSC: BE = 29 (1DH); default after reset if strapping pin 13 tied to LOW 2001 Sep 25 43 Philips Semiconductors Product specification Digital video encoder SAA7102; SAA7103 Table 46 Subaddresses 2AH to 2CH DATA BYTE LOGIC LEVEL DESCRIPTION CG − LSB of the respective bytes are encoded immediately after run-in, the MSBs of the respective bytes have to carry the CRCC bits, in accordance with the definition of copy generation management system encoding format. CGEN 0 copy generation data output is disabled; default after reset 1 copy generation data output is enabled Table 47 Subaddress 2DH DATA BYTE LOGIC LEVEL VBSEN CVBSEN1 CVBSEN0 CEN ENCOFF CLK2EN DESCRIPTION 0 pin 28 provides a component GREEN signal (CVBSEN1 = 0) or CVBS signal (CVBSEN1 = 1) 1 pin 28 provides a luminance (VBS) signal; default after reset 0 pin 28 provides a component GREEN (G) or luminance (VBS) signal; default after reset 1 pin 28 provides a CVBS signal 0 pin 30 provides a component BLUE (B) or colour difference BLUE (CB) signal 1 pin 30 provides a CVBS signal; default after reset 0 pin 27 provides a component RED (R) or colour difference RED (CR) signal 1 pin 27 provides a chrominance signal (C) as modulated subcarrier for S-video; default after reset 0 encoder is active; default after reset 1 encoder bypass, DACs are provided with RGB signal after cursor insertion block 0 pin 24 provides a teletext request signal (TTXRQ) 1 pin 24 provides the buffered crystal clock divided by two (13.5 MHz); default after reset Table 48 Subaddresses 38H and 39H DATA BYTE DESCRIPTION GY4 to GY0 Gain luminance of RGB (CR, Y and CB) output, ranging from (1 − 16⁄32) to (1 + 15⁄32). Suggested nominal value = 0, depending on external application. GCD4 to GCD0 Gain colour difference of RGB (CR, Y and CB) output, ranging from (1 − 16⁄32) to (1 + 15⁄32). Suggested nominal value = 0, depending on external application. 2001 Sep 25 44 Philips Semiconductors Product specification Digital video encoder SAA7102; SAA7103 Table 49 Subaddress 3AH DATA BYTE CBENB SYMP DEMOFF CSYNC Y2C UV2C LOGIC LEVEL DESCRIPTION 0 data from input ports is encoded 1 colour bar with fixed colours is encoded 0 horizontal and vertical trigger is taken from FSVGC or both VSVGC and HSVGC; default after reset 1 horizontal and vertical trigger is decoded out of “ITU-R BT.656” compatible data at PD port 0 Y-CB-CR to RGB dematrix is active; default after reset 1 Y-CB-CR to RGB dematrix is bypassed 0 pin 26 provides a horizontal sync for non-interlaced VGA components output (at PIXCLK) 1 pin 26 provides a composite sync for interlaced components output (at XTAL clock) 0 input luminance data is twos complement from PD input port 1 input luminance data is straight binary from PD input port; default after reset 0 input colour difference data is twos complement from PD input port 1 input colour difference data is straight binary from PD input port; default after reset Table 50 Subaddress 54H DATA BYTE VPSEN CCIRS EDGE2 EDGE1 LOGIC LEVEL DESCRIPTION 0 video programming system data insertion is disabled; default after reset 1 video programming system data insertion in line 16 is enabled 0 If SYMP = 1, horizontal and vertical trigger is decoded out of “ITU-R BT.656” compatible data at MP2 port; default after reset. 1 If SYMP = 1, horizontal and vertical trigger is decoded out of “ITU-R BT.656” compatible data at MP1 port. 0 internal PPD2 data is sampled on the rising clock edge 1 internal PPD2 data is sampled on the falling clock edge; see Tables 25 to 29; default after reset 0 internal PPD1 data is sampled on the rising clock edge; see Tables 25 to 29; default after reset 1 internal PPD1 data is sampled on the falling clock edge Table 51 Subaddresses 55H to 59H DATA BYTE DESCRIPTION REMARKS VPS5 fifth byte of video programming system data VPS11 eleventh byte of video programming system data VPS12 twelfth byte of video programming system data VPS13 thirteenth byte of video programming system data VPS14 fourteenth byte of video programming system data 2001 Sep 25 45 in line 16; LSB first; all other bytes are not relevant for VPS Philips Semiconductors Product specification Digital video encoder SAA7102; SAA7103 Table 52 Subaddress 5AH; note 1 DATA BYTE CHPS DESCRIPTION VALUE RESULT phase of encoded colour subcarrier (including burst) relative to horizontal sync; can be adjusted in steps of 360/256 degrees 6BH PAL B/G and data from input ports in master mode 16H PAL B/G and data from look-up table 25H NTSC M and data from input ports in master mode 46H NTSC M and data from look-up table Note 1. The default after reset is 00H. Table 53 Subaddresses 5BH and 5DH DATA BYTE GAINU DESCRIPTION variable gain for CB signal; input representation in accordance with “ITU-R BT.601” CONDITIONS REMARKS white-to-black = 92.5 IRE GAINU = −2.17 × nominal to +2.16 × nominal GAINU = 0 output subcarrier of U contribution = 0 GAINU = 118 (76H) output subcarrier of U contribution = nominal white-to-black = 100 IRE GAINU = −2.05 × nominal to +2.04 × nominal GAINU = 0 output subcarrier of U contribution = 0 GAINU = 125 (7DH) output subcarrier of U contribution = nominal Table 54 Subaddresses 5CH and 5EH DATA BYTE GAINV DESCRIPTION variable gain for CR signal; input representation in accordance with “ITU-R BT.601” CONDITIONS REMARKS white-to-black = 92.5 IRE GAINV = −1.55 × nominal to +1.55 × nominal GAINV = 0 output subcarrier of V contribution = 0 GAINV = 165 (A5H) output subcarrier of V contribution = nominal white-to-black = 100 IRE GAINV = −1.46 × nominal to +1.46 × nominal GAINV = 0 output subcarrier of V contribution = 0 GAINV = 175 (AFH) output subcarrier of V contribution = nominal Table 55 Subaddress 5DH DATA BYTE BLCKL DESCRIPTION variable black level; input representation in accordance with “ITU-R BT.601” CONDITIONS REMARKS white-to-sync = 140 IRE; note 1 recommended value: BLCKL = 58 (3AH) BLCKL = 0; note 1 output black level = 29 IRE BLCKL = 63 (3FH); note 1 output black level = 49 IRE white-to-sync = 143 IRE; note 2 recommended value: BLCKL = 51 (33H) BLCKL = 0; note 2 output black level = 27 IRE BLCKL = 63 (3FH); note 2 output black level = 47 IRE Notes 1. Output black level/IRE = BLCKL × 2/6.29 + 28.9. 2. Output black level/IRE = BLCKL × 2/6.18 + 26.5. 2001 Sep 25 46 Philips Semiconductors Product specification Digital video encoder SAA7102; SAA7103 Table 56 Subaddress 5EH DATA BYTE BLNNL DESCRIPTION variable blanking level CONDITIONS REMARKS white-to-sync = 140 IRE; note 1 recommended value: BLNNL = 46 (2EH) BLNNL = 0; note 1 output blanking level = 25 IRE BLNNL = 63 (3FH); note 1 output blanking level = 45 IRE white-to-sync = 143 IRE; note 2 recommended value: BLNNL = 53 (35H) BLNNL = 0; note 2 output blanking level = 26 IRE BLNNL = 63 (3FH); note 2 output blanking level = 46 IRE Notes 1. Output black level/IRE = BLNNL × 2/6.29 + 25.4. 2. Output black level/IRE = BLNNL × 2/6.18 + 25.9; default after reset: 35H. Table 57 Subaddress 5FH DATA BYTE DESCRIPTION CCRS select cross-colour reduction filter in luminance; see Table 58 BLNVB variable blanking level during vertical blanking interval is typically identical to value of BLNNL Table 58 Logic levels and function of CCRS CCRS1 CCRS0 DESCRIPTION 0 0 no cross-colour reduction; for overall transfer characteristic of luminance see Fig.6 0 1 cross-colour reduction #1 active; for overall transfer characteristic see Fig.6 1 0 cross-colour reduction #2 active; for overall transfer characteristic see Fig.6 1 1 cross-colour reduction #3 active; for overall transfer characteristic see Fig.6 Table 59 Subaddress 61H DATA BYTE DOWND LOGIC LEVEL DESCRIPTION 0 digital core in normal operational mode; default after reset 1 digital core in sleep mode and is reactivated with an I2C-bus address DOWNA 0 DACs in normal operational mode; default after reset YGS 1 0 1 DACs in Power-down mode luminance gain for white − black 100 IRE luminance gain for white − black 92.5 IRE including 7.5 IRE set-up of black SCBW 0 PAL 0 1 enlarged bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see Figs 4 and 5) standard bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see Figs 4 and 5); default after reset NTSC encoding (non-alternating V component) PAL encoding (alternating V component) FISE 0 1 864 total pixel clocks per line 858 total pixel clocks per line 1 2001 Sep 25 47 Philips Semiconductors Product specification Digital video encoder SAA7102; SAA7103 Table 60 Subaddress 62H DATA BYTE BSTA DESCRIPTION amplitude of colour burst; input representation in accordance with “ITU-R BT.601” CONDITIONS REMARKS white-to-black = 92.5 IRE; burst = 40 IRE; NTSC encoding recommended value: BSTA = 63 (3FH) BSTA = 0 to 2.02 × nominal white-to-black = 92.5 IRE; burst = 40 IRE; PAL encoding recommended value: BSTA = 45 (2DH) BSTA = 0 to 2.82 × nominal white-to-black = 100 IRE; burst = 43 IRE; NTSC encoding BSTA = 0 to 1.90 × nominal white-to-black = 100 IRE; burst = 43 IRE; PAL encoding BSTA = 0 to 3.02 × nominal recommended value: BSTA = 67 (43H) recommended value: BSTA = 47 (2FH); default after reset Table 61 Subaddresses 63H to 66H (four bytes to program subcarrier frequency) DATA BYTE DESCRIPTION FSC0 to FSC3 ffsc = subcarrier frequency (in multiples of line frequency); fllc = clock frequency (in multiples of line frequency) CONDITIONS REMARKS FSC3 = most significant byte; f fsc 32 FSC = round -------- × 2 ; note 1 FSC0 = least significant byte f llc Note 1. Examples: a) NTSC M: ffsc = 227.5, fllc = 1716 → FSC = 569408543 (21F07C1FH). b) PAL B/G: ffsc = 283.7516, fllc = 1728 → FSC = 705268427 (2A098ACBH). Table 62 Subaddresses 67H to 6AH DATA BYTE DESCRIPTION L21O0 first byte of captioning data, odd field L21O1 second byte of captioning data, odd field L21E0 first byte of extended data, even field L21E1 second byte of extended data, even field REMARKS LSBs of the respective bytes are encoded immediately after run-in and framing code, the MSBs of the respective bytes have to carry the parity bit, in accordance with the definition of line 21 encoding format. Table 63 Subaddresses 6CH and 6DH DATA BYTE HTRIG DESCRIPTION sets the horizontal trigger phase related to chip-internal horizontal input values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed; increasing HTRIG decreases delays of all internally generated timing signals; the default value is 0 2001 Sep 25 48 Philips Semiconductors Product specification Digital video encoder SAA7102; SAA7103 Table 64 Subaddress 6DH DATA BYTE VTRIG DESCRIPTION sets the vertical trigger phase related to chip-internal vertical input increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines; variation range of VTRIG = 0 to 31 (1FH); the default value is 0 Table 65 Subaddress 6EH DATA BYTE LOGIC LEVEL BLCKON DESCRIPTION 0 encoder in normal operation mode; default after reset 1 output signal is forced to blanking level PHRES − selects the phase reset mode of the colour subcarrier generator; see Table 66 LDEL − selects the delay on luminance path with reference to chrominance path; see Table 67 FLC − field length control; see Table 68 Table 66 Logic levels and function of PHRES DATA BYTE DESCRIPTION PHRES1 PHRES0 0 0 no subcarrier reset 0 1 subcarrier reset every two lines 1 0 subcarrier reset every eight fields 1 1 subcarrier reset every four fields Table 67 Logic levels and function of LDEL DATA BYTE DESCRIPTION LDEL1 LDEL0 0 0 no luminance delay; default after reset 0 1 1 LLC luminance delay 1 0 2 LLC luminance delay 1 1 3 LLC luminance delay Table 68 Logic levels and function of FLC DATA BYTE DESCRIPTION FLC1 FLC0 0 0 interlaced 312.5 lines/field at 50 Hz, 262.5 lines/field at 60 Hz; default after reset 0 1 non-interlaced 312 lines/field at 50 Hz, 262 lines/field at 60 Hz 1 0 non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz 1 1 non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz 2001 Sep 25 49 Philips Semiconductors Product specification Digital video encoder SAA7102; SAA7103 Table 69 Subaddress 6FH DATA BYTE LOGIC LEVEL DESCRIPTION CCEN − enables individual line 21 encoding; see Table 70 TTXEN 0 disables teletext insertion; default after reset 1 enables teletext insertion − selects the actual line, where Closed Caption or extended data are encoded; line = (SCCLN + 4) for M-systems; line = (SCCLN + 1) for other systems SCCLN Table 70 Logic levels and function of CCEN DATA BYTE DESCRIPTION CCEN1 CCEN0 0 0 line 21 encoding off; default after reset 0 1 enables encoding in field 1 (odd) 1 0 enables encoding in field 2 (even) 1 1 enables encoding in both fields Table 71 Subaddresses 70H to 72H DATA BYTE ADWHS DESCRIPTION active display window horizontal start; defines the start of the active TV display portion after the border colour values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed ADWHE active display window horizontal end; defines the end of the active TV display portion before the border colour values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed Table 72 Subaddress 73H DATA BYTE TTXHS DESCRIPTION REMARKS start of signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0); see Fig.14 TTXHS = 42H; is default after reset if strapped to PAL TTXHS = 54H; is default after reset if strapped to NTSC Table 73 Subaddress 74H DATA BYTE TTXHD DESCRIPTION REMARKS indicates the delay in clock cycles between rising edge of TTXRQ output signal on pin TTXRQ_XCLKO2 (CLK2EN = 0) and valid data at pin TTX_SRES minimum value: TTXHD = 2; is default after reset Table 74 Subaddress 75H DATA BYTE CSYNCA 2001 Sep 25 DESCRIPTION advanced composite sync against RGB output from 0 XTAL clocks to 31 XTAL clocks 50 Philips Semiconductors Product specification Digital video encoder SAA7102; SAA7103 Table 75 Subaddresses 76H, 77H and 7CH DATA BYTE TTXOVS DESCRIPTION REMARKS first line of occurrence of signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0) in odd field line = (TTXOVS + 4) for M-systems line = (TTXOVS + 1) for other systems TTXOVE last line of occurrence of signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0) in odd field line = (TTXOVE + 3) for M-systems line = TTXOVE for other systems TTXOVS = 05H; is default after reset if strapped to PAL TTXOVS = 06H; is default after reset if strapped to NTSC TTXOVE = 16H; is default after reset if strapped to PAL TTXOVE = 10H; is default after reset if strapped to NTSC Table 76 Subaddresses 78H, 79H and 7CH DATA BYTE TTXEVS DESCRIPTION REMARKS first line of occurrence of signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0) in even field line = (TTXEVS + 4) for M-systems line = (TTXEVS + 1) for other systems TTXEVE last line of occurrence of signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0) in even field line = (TTXEVE + 3) for M-systems line = TTXEVE for other systems TTXEVS = 04H; is default after reset if strapped to PAL TTXEVS = 05H; is default after reset if strapped to NTSC TTXEVE = 16H; is default after reset if strapped to PAL TTXEVE = 10H; is default after reset if strapped to NTSC Table 77 Subaddresses 7AH to 7CH DATA BYTE DESCRIPTION FAL first active line = FAL + 4 for M-systems and FAL + 1 for other systems, measured in lines LAL last active line = LAL + 3 for M-systems and LAL for other system, measured in lines FAL = 0 coincides with the first field synchronization pulse LAL = 0 coincides with the first field synchronization pulse Table 78 Subaddress 7CH DATA BYTE TTX60 LOGIC LEVEL DESCRIPTION 0 enables NABTS (FISE = 1) or European TTX (FISE = 0); default after reset 1 enables world standard teletext 60 Hz (FISE = 1) Table 79 Subaddresses 7EH and 7FH DATA BYTE LINE DESCRIPTION individual lines in both fields (PAL counting) can be disabled for insertion of teletext by the respective bits, disabled line = LINExx (50 Hz field rate) this bit mask is effective only if the lines are enabled by TTXOVS/TTXOVE and TTXEVS/TTXEVE 2001 Sep 25 51 Philips Semiconductors Product specification Digital video encoder SAA7102; SAA7103 Table 80 Subaddresses 81H to 83H DATA BYTE PCL DESCRIPTION defines the frequency of the synthesized pixel clock PIXCLKO; PCL ×8;f f PIXCLK = ---------×f XTAL = 27 MHz nominal, e.g. 640 × 480 to NTSC M: PCL = 20F63BH; 24- XTAL 2 640 × 480 to PAL B/G: PCL = 1B5A73H (as by strapping pins) Table 81 Subaddresses 90H and 94H DATA BYTE XOFS DESCRIPTION horizontal offset; defines the number of PIXCLKs from horizontal sync (HSVGC) output to composite blanking (CBO) output Table 82 Subaddresses 91H and 94H DATA BYTE XPIX DESCRIPTION pixel in X direction; defines half the number of active pixels per input line (identical to the length of CBO pulses) Table 83 Subaddresses 92H and 94H DATA BYTE YOFSO DESCRIPTION vertical offset in odd field; defines (in the odd field) the number of lines from VSVGC to first line with active CBO; if no LUT data is requested, the first active CBO will be output at YOFSO + 2; usually, YOFSO = YOFSE with the exception of extreme vertical downscaling and interlacing Table 84 Subaddresses 93H and 94H DATA BYTE YOFSE DESCRIPTION vertical offset in even field; defines (in the even field) the number of lines from VSVGC to first line with active CBO; if no LUT data is requested, the first active CBO will be output at YOFSE + 2; usually, YOFSE = YOFSO with the exception of extreme vertical downscaling and interlacing Table 85 Subaddresses 95H and 96H DATA BYTE YPIX 2001 Sep 25 DESCRIPTION defines the number of requested input lines from the feeding device; number of requested lines = YPIX + YOFSE − YOFSO 52 Philips Semiconductors Product specification Digital video encoder SAA7102; SAA7103 Table 86 Subaddress 96H DATA BYTE EFS PCBN SLAVE ILC YFIL HSL LOGIC LEVEL DESCRIPTION 0 frame sync signal at pin FSVGC ignored in slave mode 1 frame sync signal at pin FSVGC accepted in slave mode 0 normal polarity of CBO signal (HIGH during active video) 1 inverted polarity of CBO signal (LOW during active video) 0 the SAA7102; SAA7103 is timing master to the graphics controller 1 the SAA7102; SAA7103 is timing slave to the graphics controller 0 if hardware cursor insertion is active, set LOW for non-interlaced input signals 1 if hardware cursor insertion is active, set HIGH for interlaced input signals 0 luminance sharpness booster disabled 1 luminance sharpness booster enabled 0 normal trigger event handling of the horizontal state machine, if the SAA7102; SAA7103 is slave to HSVGC input 1 trigger event for horizontal state machine is shifted 128 PIXCLKs in advance, adapted to a late HSVGC in slave mode Table 87 Subaddress 97H DATA BYTE HFS VFS OFS PFS OVS PVS 2001 Sep 25 LOGIC LEVEL DESCRIPTION 0 horizontal sync is directly derived from input signal (slave mode) at pin HSVGC 1 horizontal sync is derived from a frame sync signal (slave mode) at pin FSVGC (only if EFS is set HIGH) 0 vertical sync (field sync) is directly derived from input signal (slave mode) at pin VSVGC 1 vertical sync (field sync) is derived from a frame sync signal (slave mode) at pin FSVGC (only if EFS is set HIGH) 0 pin FSVGC is switched to input 1 pin FSVGC is switched to active output 0 polarity of signal on FSVGC in output mode (master mode) is active HIGH; rising edge of the input signal is used in slave mode 1 polarity of signal on FSVGC in output mode (master mode) is active LOW; falling edge of the input signal is used in slave mode 0 pin VSVGC is switched to input 1 pin VSVGC is switched to active output 0 polarity of signal on VSVGC in output mode (master mode) is active HIGH; rising edge of the input signal is used in slave mode 1 polarity of signal on VSVGC in output mode (master mode) is active LOW; falling edge of the input signal is used in slave mode 53 Philips Semiconductors Product specification Digital video encoder DATA BYTE OHS PHS SAA7102; SAA7103 LOGIC LEVEL DESCRIPTION 0 pin HSVGC is switched to input 1 pin HSVGC is switched to active output 0 polarity of signal on HSVGC in output mode (master mode) is active HIGH; rising edge of the input signal is used in slave mode 1 polarity of signal on HSVGC in output mode (master mode) is active LOW; falling edge of the input signal is used in slave mode Table 88 Subaddresses 98H and 99H DATA BYTE HLEN DESCRIPTION number of PIXCLKs horizontal length; HLEN = ----------------------------------------------------- – 1 line Table 89 Subaddress 99H DATA BYTE IDEL DESCRIPTION input delay; defines the distance in PIXCLKs between the active edge of CBO and the first received valid pixel Table 90 Subaddresses 9AH and 9CH DATA BYTE XINC DESCRIPTION number of output pixels -------------------------------------------------------------line incremental fraction of the horizontal scaling engine; XINC = -------------------------------------------------------------- × 4096 number of input pixels ---------------------------------------------------------line Table 91 Subaddresses 9BH and 9CH DATA BYTE YINC DESCRIPTION number of active output lines incremental fraction of the vertical scaling engine; YINC = ---------------------------------------------------------------------------- × 4096 number of active input lines Table 92 Subaddresses 9DH and 9FH DATA BYTE YIWGTO DESCRIPTION YINC weighting factor for the first line of the odd field; YIWGTO = -------------- + 2048 2 Table 93 Subaddresses 9EH and 9FH DATA BYTE YIWGTE 2001 Sep 25 DESCRIPTION YINC – YSKIP weighting factor for the first line of the even field; YIWGTE = -------------------------------------2 54 Philips Semiconductors Product specification Digital video encoder SAA7102; SAA7103 Table 94 Subaddresses A0H and A1H DATA BYTE YSKIP DESCRIPTION vertical line skip; defines the effectiveness of the anti-flicker filter; YSKIP = 0: most effective; YSKIP = 4095: anti-flicker filter switched off Table 95 Subaddress A1H DATA BYTE BLEN LOGIC LEVEL DESCRIPTION 0 no internal blanking for non-interlaced graphics in bypass mode; default after reset 1 forced internal blanking for non-interlaced graphics in bypass mode Table 96 Subaddresses A2H to A4H DATA BYTE BCY, BCU and BCV DESCRIPTION luminance and colour difference portion of border colour in underscan area Table 97 Subaddresses F0H to F2H DATA BYTE CC1R, CC1G and CC1B DESCRIPTION RED, GREEN and BLUE portion of first cursor colour Table 98 Subaddresses F3H to F5H DATA BYTE CC2R, CC2G and CC2B DESCRIPTION RED, GREEN and BLUE portion of second cursor colour Table 99 Subaddresses F6H to F8H DATA BYTE DESCRIPTION AUXR, AUXG and AUXB RED, GREEN and BLUE portion of auxiliary cursor colour Table 100 Subaddresses F9H and FAH DATA BYTE XCP DESCRIPTION horizontal cursor position Table 101 Subaddress FAH DATA BYTE XHS DESCRIPTION horizontal hot spot of cursor Table 102 Subaddresses FBH and FCH DATA BYTE YCP 2001 Sep 25 DESCRIPTION vertical cursor position 55 Philips Semiconductors Product specification Digital video encoder SAA7102; SAA7103 Table 103 Subaddress FCH DATA BYTE YHS DESCRIPTION vertical hot spot of cursor Table 104 Subaddress FDH DATA BYTE LUTOFF CMODE LUTL IF MATOFF DFOFF LOGIC LEVEL DESCRIPTION 0 colour look-up table is active 1 colour look-up table is bypassed 0 cursor mode; input colour will be inverted 1 auxiliary cursor colour will be inserted 0 LUT loading via input data stream is inactive 1 colour and cursor LUTs are loaded via input data stream 0 input format is 8 + 8 + 8 bit 4 : 4 : 4 non-interlaced RGB or CB-Y-CR 1 input format is 5 + 5 + 5 bit 4 : 4 : 4 non-interlaced RGB 2 input format is 5 + 6 + 5 bit 4 : 4 : 4 non-interlaced RGB 3 input format is 8 + 8 + 8 bit 4 : 2 : 2 non-interlaced CB-Y-CR 4 input format is 8 + 8 + 8 bit 4 : 2 : 2 interlaced CB-Y-CR (ITU-R BT.656, 27 MHz clock) (in subaddresses 91H and 94H set XPIX = number of active pixels/line) 5 input format is 8-bit non-interlaced index colour 6 input format is 8 + 8 + 8 bit 4 : 4 : 4 non-interlaced RGB or CB-Y-CR (special bit ordering) 0 RGB to CR-Y-CB matrix is active 1 RGB to CR-Y-CB matrix is bypassed 0 down formatter (4 : 4 : 4 to 4 : 2 : 2) in input path is active 1 down formatter is bypassed Table 105 Subaddress FEH DATA BYTE CURSA DESCRIPTION RAM start address for cursor bit map; the byte following subaddress FEH points to the first cell to be loaded with the next transmitted byte; succeeding cells are loaded by auto-incrementing until stop condition Table 106 Subaddress FFH DATA BYTE COLSA DESCRIPTION RAM start address for colour LUT; the byte following subaddress FFH points to the first cell to be loaded with the next transmitted byte; succeeding cells are loaded by auto-incrementing until stop condition In subaddresses 5BH, 5CH, 5DH, 5EH and 62H all IRE values are rounded up. 2001 Sep 25 56 Philips Semiconductors Product specification Digital video encoder 7.22 SAA7102; SAA7103 Slave transmitter Table 107 Slave transmitter (slave address 89H) REGISTER FUNCTION DATA BYTE SUBADDRESS D7 D6 D5 D4 D3 D2 D1 D0 Status byte 00H VER2 VER1 VER0 CCRDO CCRDE 0 FSEQ O_E Chip ID 1CH CID7 CID6 CID5 CID4 CID3 CID2 CID1 CID0 FIFO status 80H 0 0 0 0 0 0 OVFL UDFL Table 108 Subaddress 00H DATA BYTE LOGIC LEVEL DESCRIPTION VER − version identification of the device: it will be changed with all versions of the IC that have different programming models; current version is 010 binary CCRDO 1 Closed Caption bytes of the odd field have been encoded 0 the bit is reset after information has been written to the subaddresses 67H and 68H; it is set immediately after the data has been encoded 1 Closed Caption bytes of the even field have been encoded 0 the bit is reset after information has been written to the subaddresses 69H and 6AH; it is set immediately after the data has been encoded 1 during first field of a sequence (repetition rate: NTSC = 4 fields, PAL = 8 fields) 0 not first field of a sequence 1 during even field 0 during odd field CCRDE FSEQ O_E Table 109 Subaddress 1CH DATA BYTE CID DESCRIPTION chip ID of SAA7102 = 02H; chip ID of SAA7103 = 03H Table 110 Subaddress 80H DATA BYTE OVFL UDFL 2001 Sep 25 LOGIC LEVEL DESCRIPTION 0 no FIFO overflow 1 FIFO overflow has occurred; this bit is reset after this subaddress has been read 0 no FIFO underflow 1 FIFO underflow has occurred; this bit is reset after this subaddress has been read 57 Philips Semiconductors Product specification Digital video encoder SAA7102; SAA7103 MBE737 handbook, full 6 pagewidth Gv (dB) 0 −6 −12 −18 −24 (1) (2) −30 −36 −42 −48 −54 0 2 4 6 8 10 (1) SCBW = 1. (2) SCBW = 0. Fig.4 Chrominance transfer characteristic 1. MBE735 handbook, halfpage 2 Gv (dB) 0 (1) (2) −2 −4 −6 0 0.4 0.8 1.2 f (MHz) 1.6 (1) SCBW = 1. (2) SCBW = 0. Fig.5 Chrominance transfer characteristic 2. 2001 Sep 25 58 12 f (MHz) 14 Philips Semiconductors Product specification Digital video encoder SAA7102; SAA7103 MGD672 6 Gv full pagewidth handbook, (dB) (4) 0 (2) (3) −6 (1) −12 −18 −24 −30 −36 −42 −48 −54 0 2 4 6 8 10 12 14 f (MHz) (1) (2) (3) (4) CCRS1 = 0; CCRS0 = 1. CCRS1 = 1; CCRS0 = 0. CCRS1 = 1; CCRS0 = 1. CCRS1 = 0; CCRS0 = 0. Fig.6 Luminance transfer characteristic 1 (excluding scaler). MBE736 handbook, halfpage 1 Gv (dB) (1) 0 −1 −2 −3 −4 −5 0 2 4 f (MHz) 6 (1) CCRS1 = 0; CCRS0 = 0. Fig.7 Luminance transfer characteristic 2 (excluding scaler). 2001 Sep 25 59 Philips Semiconductors Product specification Digital video encoder SAA7102; SAA7103 MGB708 handbook, full pagewidth Gv 6 (dB) 0 −6 −12 −18 −24 −30 −36 −42 −48 −54 0 2 4 6 8 10 12 f (MHz) 14 Fig.8 Luminance transfer characteristic in RGB (excluding scaler). MGB706 handbook, full pagewidth Gv 6 (dB) 0 −6 −12 −18 −24 −30 −36 −42 −48 −54 0 2 4 6 8 10 12 Fig.9 Colour difference transfer characteristic in RGB (excluding scaler). 2001 Sep 25 60 f (MHz) 14 Philips Semiconductors Product specification Digital video encoder 8 SAA7102; SAA7103 BOUNDARY SCAN TEST The Boundary Scan Test (BST) functions BYPASS, EXTEST, INTEST, SAMPLE, CLAMP and IDCODE are all supported; see Table 111. Details about the JTAG BST-TEST can be found in the specification “IEEE Std. 1149.1”. A file containing the detailed Boundary Scan Description Language (BSDL) of the SAA7102; SAA7103 is available on request. The SAA7102; SAA7103 has built-in logic and 5 dedicated pins to support boundary scan testing which allows board testing without special hardware (nails). The SAA7102; SAA7103 follows the “IEEE Std. 1149.1 - Standard Test Access Port and Boundary-Scan Architecture” set by the Joint Test Action Group (JTAG) chaired by Philips. The 5 special pins are Test Mode Select (TMS), Test Clock (TCLK), Test Reset (TRST), Test Data Input (TDI) and Test Data Output (TDO). Table 111 BST instructions supported by the SAA7102; SAA7103 INSTRUCTION 8.1 DESCRIPTION BYPASS This mandatory instruction provides a minimum length serial path (1 bit) between TDI and TDO when no test operation of the component is required. EXTEST This mandatory instruction allows testing of off-chip circuitry and board level interconnections. SAMPLE This mandatory instruction can be used to take a sample of the inputs during normal operation of the component. It can also be used to preload data values into the latched outputs of the boundary scan register. CLAMP This optional instruction is useful for testing when not all ICs have BST. This instruction addresses the bypass register while the boundary scan register is in external test mode. IDCODE This optional instruction will provide information on the components manufacturer, part number and version number. INTEST This optional instruction allows testing of the internal logic (no support for customer available). USER1 This private instruction allows testing by the manufacturer (no support for customer available). Initialization of boundary scan circuit When the IDCODE instruction is loaded into the BST instruction register, the identification register will be connected between TDI and TDO of the IC. The identification register will load a component specific code during the CAPTURE_DATA_REGISTER state of the TAP controller, this code can subsequently be shifted out. At board level this code can be used to verify component manufacturer, type and version number. The device identification register contains 32 bits, numbered 31 to 0, where bit 31 is the most significant bit (nearest to TDI) and bit 0 is the least significant bit (nearest to TDO); see Fig.10. The Test Access Port (TAP) controller of an IC should be in the reset state (TEST_LOGIC_RESET) when the IC is in functional mode. This reset state also forces the instruction register into a functional instruction such as IDCODE or BYPASS. To solve the power-up reset, the standard specifies that the TAP controller will be forced asynchronously to the TEST_LOGIC_RESET state by setting the TRST pin LOW. 8.2 Device identification codes A device identification register is specified in “IEEE Std. 1149.1b-1994”. It is a 32-bit register which contains fields for the specification of the IC manufacturer, the IC part number and the IC version number. Its biggest advantage is the possibility to check for the correct ICs mounted after production and to determine the version number of the ICs during field service. 2001 Sep 25 61 Philips Semiconductors Product specification Digital video encoder SAA7102; SAA7103 MSB handbook, full pagewidth 31 TDI LSB 28 27 12 11 1 0010 0111000100000010 00000010101 4-bit version code 16-bit part number 11-bit manufacturer identification 0 TDO 1 MHB909 a. SAA7102. MSB handbook, full pagewidth 31 TDI LSB 28 27 12 11 1 0010 0111000100000011 00000010101 4-bit version code 16-bit part number 11-bit manufacturer identification b. SAA7103. Fig.10 32 bits of identification code. 2001 Sep 25 62 0 1 TDO MHB910 Philips Semiconductors Product specification Digital video encoder SAA7102; SAA7103 9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); all ground pins connected together and all supply pins connected together. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDDD digital supply voltage −0.5 +4.6 V VDDA analog supply voltage −0.5 +4.6 V Vo(A) output voltage at analog outputs Vi(D) input voltage at digital inputs and outputs outputs in 3-state; −0.5 note 1 Vo(D) output voltage at digital outputs outputs active ∆VSS voltage difference between VSSA(n) and VSSD(n) − 100 mV Tstg storage temperature −65 +150 °C Tamb ambient temperature 0 70 °C Vesd electrostatic discharge voltage all pins −0.5 note 2 −0.5 VDDA + 0.5 V +5.5 V VDDD + 0.5 V −2000 +2000 V Notes 1. Except pin XTALI. 2. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ resistor. 10 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER CONDITIONS thermal resistance from junction to ambient 2001 Sep 25 in free air 63 VALUE UNIT 64 K/W Philips Semiconductors Product specification Digital video encoder SAA7102; SAA7103 11 CHARACTERISTICS VDDD = 3.0 to 3.6 V; Tamb = 0 to 70 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDDA analog supply voltage VDDD digital supply voltage IDDA analog supply current note 1 IDDD digital supply current VDDD = 3.3 V; note 2 3.15 3.3 3.45 V 3.0 3.3 3.6 V 1 110 140 mA 1 70 90 mA Inputs VIL LOW-level input voltage at all digital input pins except pins SDA and SCL −0.5 − +0.8 V VIH HIGH-level input voltage at all digital input pins except pins SDA and SCL 2.0 − VDDD + 0.3 V ILI input leakage current Ci input capacitance − − 10 µA clocks − − 10 pF data − − 8 pF I/Os at high-impedance − − 8 pF Outputs; all digital output pins except pin SDA VOL LOW-level output voltage IOL = 2 mA − − 0.4 V VOH HIGH-level output voltage IOH = −2 mA 2.4 − − V −0.5 − 0.3VDDD V I2C-bus; pins SDA and SCL VIL LOW-level input voltage VIH HIGH-level input voltage 0.7VDDD − VDDD + 0.3 V Ii input current Vi = LOW or HIGH −10 − +10 µA VOL LOW-level output voltage (pin SDA) IOL = 3 mA − − 0.4 V Io output current during acknowledge 3 − − mA note 3 22.5 − 100 ns Clock timing; pins PIXCLKI and PIXCLKO) TPIXCLK cycle time td(CLKD) delay from PIXCLKO to PIXCLKI note 4 − − − ns δ duty factor tHIGH/TPIXCLK note 3 40 50 60 % duty factor tHIGH/TCLKO2 output 40 50 60 % tr rise time note 3 − − 3 ns tf fall time note 3 − − 3 ns Input timing tSU;DAT input data set-up time 5 − − ns tHD;DAT input data hold time 0 − − ns − 27 − MHz −50 − +50 10−6 Crystal oscillator fnom nominal frequency ∆f/fnom permissible deviation of nominal frequency 2001 Sep 25 note 5 64 Philips Semiconductors Product specification Digital video encoder SYMBOL PARAMETER SAA7102; SAA7103 CONDITIONS MIN. TYP. MAX. UNIT CRYSTAL SPECIFICATION Tamb ambient temperature 0 − 70 °C CL load capacitance 8 − − pF RS series resistance − − 80 Ω C1 motional capacitance (typical) 1.2 1.5 1.8 fF C0 parallel capacitance (typical) 2.8 3.5 4.2 pF Data and reference signal output timing Co(L) output load capacitance 8 − 40 pF to(h) output hold time 2 − − ns to(d) output delay time − − 16 ns see Table 112 − 1.23 − V CVBS and RGB outputs Vo(CVBS)(p-p) output voltage CVBS (peak-to-peak value) Vo(VBS)(p-p) output voltage VBS (S-video) (peak-to-peak value) see Table 112 − 1.0 − V Vo(C)(p-p) output voltage C (S-video) (peak-to-peak value) see Table 112 − 0.89 − V Vo(RGB)(p-p) output voltage R, G, B (peak-to-peak value) see Table 112 − 0.7 − V ∆Vo inequality of output signal voltages − 2 − % Ro(L) output load resistance − 37.5 − Ω BDAC output signal bandwidth of DACs 15 − − MHz ILElf(DAC) low frequency integral linearity error of DACs − − ±3 LSB DLElf(DAC) low frequency differential linearity error of DACs − − ±1 LSB −3 dB Notes 1. Minimum value for I2C-bus bit DOWNA = 1. 2. Minimum value for I2C-bus bit DOWND = 1. 3. The data is for both input and output direction. 4. This parameter is arbitrary, if PIXCLKI is looped through the VGC. 5. If an internal oscillator is used, crystal deviation of nominal frequency is directly proportional to the deviation of subcarrier frequency and line/field frequency. 2001 Sep 25 65 Philips Semiconductors Product specification Digital video encoder SAA7102; SAA7103 TPIXCLK handbook, full pagewidth tHIGH 2.4 V PIXCLKO 1.5 V 0.4 V tf td(CLKD) tr 2.0 V PIXCLKI 1.5 V 0.8 V tHD;DAT tHD;DAT tSU;DAT tSU;DAT 2.0 V PDn 0.8 V to(d) to(h) 2.4 V any output 0.4 V MHB904 Fig.11 Input/output timing specification. handbook, full pagewidth HSVGC CBO PD XOFS IDEL XPIX HLEN MHB905 Fig.12 Horizontal input timing. 2001 Sep 25 66 Philips Semiconductors Product specification Digital video encoder handbook, full pagewidth SAA7102; SAA7103 HSVGC VSVGC CBO YOFS YPIX Fig.13 Vertical input timing. 2001 Sep 25 67 MHB906 Philips Semiconductors Product specification Digital video encoder 11.1 SAA7102; SAA7103 Time ti(TTXW) is the internally used insertion window for TTX data; it has a constant length that allows insertion of 360 teletext bits at a text data rate of 6.9375 Mbits/s (PAL), 296 teletext bits at a text data rate of 5.7272 Mbits/s (world standard TTX) or 288 teletext bits at a text data rate of 5.7272 Mbits/s (NABTS). The insertion window is not opened if the control bit TTXEN is zero. Teletext timing Time tFD is the time needed to interpolate input data TTX and insert it into the CVBS and VBS output signal, such that it appears at tTTX = 9.78 µs (PAL) or tTTX = 10.5 µs (NTSC) after the leading edge of the horizontal synchronization pulse. Time tPD is the pipeline delay time introduced by the source that is gated by TTXRQ_XCLKO2 in order to deliver TTX data. This delay is programmable by register TTXHD. For every active HIGH state at output pin TTXRQ_XCLKO2, a new teletext bit must be provided by the source. Using appropriate programming, all suitable lines of the odd field (TTXOVS and TTXOVE) plus all suitable lines of the even field (TTXEVS and TTXEVE) can be used for teletext insertion. It is essential to note that the two pins used for teletext insertion must be configured for this purpose by the correct I2C-bus register settings. Since the beginning of the pulses representing the TTXRQ signal and the delay between the rising edge of TTXRQ and valid teletext input data are fully programmable (TTXHS and TTXHD), the TTX data is always inserted at the correct position after the leading edge of the outgoing horizontal synchronization pulse. handbook, full pagewidth CVBS/Y t TTX text bit #: 1 t i(TTXW) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 TTX_SRES t PD t FD TTXRQ_XCLKO2 MHB891 Fig.14 Teletext timing. 2001 Sep 25 68 24 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... TP5 HSVGC TP4 CBO PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 BST2 SCL AGND R11 75 Ω AGND R12 75 Ω FLTR [0:2] RED_CR_C GREEN_VBS_CVBS BLUE_CB_CVBS VSM SAA7102H SAA7103H HSM_CSYNC 27 FLTR0 28 FLTR1 30 FLTR2 25 VSM 26 HSM_CSYNC Y1 XTALO HSVGC VSVGC XTALI 13 FSVGC 21 CBO FSVGC CBO R10 75 Ω 11 12 SDA TCLK 37 TRST TDI TDO TMS 6 38 7 8 SCL SDA AGND 34 L1 27 MHz 35 VDD3_0 C8 10 pF 10 µH C7 10 pF C9 1 nF R2 TTX_SRES TTXRQ_XCLKO2 33 AGND C2 100 nF 12 Ω R8 C3 100 nF RESET PIXCLKO PIXCLKI RSET 22 µF JP9 RESET DGND RESET R7 JP10 CLK SHORT 1 kΩ AGND 0Ω 5 R9 R3 AGND 20 DGND VDD3_2 C4 100 nF 15 DGND Fig.15 Application circuit. PIXCLKO 22 Ω R6 22 Ω PIXCLKI MHB913 Product specification C1 100 nF VDD3_1 32 31 CP1 SAA7102; SAA7103 VDDA3_1 VDDA3_2 39 9 DGND RESET S1 DUMP TP3 XCLKO2 4.7 kΩ VSSD1 TTX_SRES TTXRQ_XCLKO2 VSSD2 23 24 VSSA1 69 22 14 HSVGC VSVGC VDDA1 4 3 2 1 44 43 42 41 16 17 18 19 36 29 VDDA2 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 VDDD2 PD [0:11] VDDD1 10 40 BST1 BST0 VDD3_1 Philips Semiconductors VDD3_2 TDI TDO Digital video encoder VDDA3_1 BST [0:2] 12 APPLICATION INFORMATION dbook, full pagewidth 2001 Sep 25 VDDA3_2 Philips Semiconductors Product specification Digital video encoder SAA7102; SAA7103 C16 handbook, halfpage 120 pF L2 L3 2.7 µH 2.7 µH C13 560 pF C10 390 pF AGND JP11 JP12 FIN FOUT FILTER 1 = byp. ll act. MHB912 Fig.16 FLTR0, FLTR1 and FLTR2 of Fig.15. 12.1 Analog output voltages By setting the reference currents of the DACs as shown in Table 112, standard compliant amplitudes can be achieved for all signal combinations; it is assumed that in subaddress 16H, parameter DACF = 0000b, that means the fine adjustment for all DACs in common is set to 0%. The analog output voltages are dependent on the total load (typical value 37.5 Ω), the digital gain parameters and the I2C-bus settings of the DAC reference currents (analog settings). If S-video output is desired, the adjustment for the C (chrominance subcarrier) output should be identical to the one for VBS (luminance plus sync) output. The digital output signals in front of the DACs under nominal (nominal here stands for the settings given in Tables 53 to 60 for example a standard PAL or NTSC signal) conditions occupy different conversion ranges, as indicated in Table 112 for a 100⁄100 colour bar signal. Table 112 Digital output signals conversion range SET/OUT Digital settings Digital output Analog settings Analog output 12.2 CVBS, SYNC TIP-TO-WHITE VBS, SYNC TIP-TO-WHITE see Tables 53 to 60 see Tables 53 to 60 see Table 48 1014 881 876 e.g. B DAC = 1FH e.g. G DAC = 1BH e.g. R DAC = G DAC = B DAC = 0BH 1.23 V (p-p) 1.00 V (p-p) 0.70 V (p-p) Suggestions for a board layout Place the analog coupling (clamp) capacitors close to the analog input pins. Place the analog termination resistors close to the coupling capacitors. Use separate ground planes for analog and digital ground. Connect these planes only at one point directly under the device, by using a 0 Ω resistor directly at the supply stage. Use separate supply lines for the analog and digital supply. Place the supply decoupling capacitors close to the supply pins. Be careful of hidden layout capacitors around the crystal application. Use serial resistors in clock, sync and data lines, to avoid clock or data reflection effects and to soften data energy. Use Lbead (ferrite coil) in each digital supply line close to the decoupling capacitors to minimize radiation energy (EMC). 2001 Sep 25 RGB, BLACK-TO-WHITE 70 Philips Semiconductors Product specification Digital video encoder SAA7102; SAA7103 13 PACKAGE OUTLINES BGA156: plastic ball grid array package; 156 balls; body 15 x 15 x 1.15 mm SOT472-1 B D A D1 ball A1 index area A2 A E1 E A1 detail X k k e1 C v M B b e y1 C ∅w M v M A P N M L K J H G F E D C B A y e e1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0 X 10 mm 5 scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 b D D1 E E1 e e1 k v w y y1 mm 1.75 0.5 0.3 1.25 1.05 0.6 0.4 15.2 14.8 13.7 13.0 15.2 14.8 13.7 13.0 1.0 13.0 1.65 1.10 0.3 0.1 0.15 0.35 OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 99-12-02 00-03-04 SOT472-1 2001 Sep 25 EUROPEAN PROJECTION 71 Philips Semiconductors Product specification Digital video encoder SAA7102; SAA7103 QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2 c y X A 33 23 34 22 ZE e E HE A A2 wM (A 3) A1 θ bp Lp pin 1 index L 12 44 1 detail X 11 wM bp e ZD v M A D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 2.10 0.25 0.05 1.85 1.65 0.25 0.40 0.20 0.25 0.14 10.1 9.9 10.1 9.9 0.8 12.9 12.3 12.9 12.3 1.3 0.95 0.55 0.15 0.15 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 θ o 10 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 95-02-04 97-08-01 SOT307-2 2001 Sep 25 EUROPEAN PROJECTION 72 Philips Semiconductors Product specification Digital video encoder SAA7102; SAA7103 • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. 14 SOLDERING 14.1 Introduction to soldering surface mount packages • For packages with leads on two sides and a pitch (e): This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 14.2 The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 220 °C for thick/large packages, and below 235 °C for small/thin packages. 14.3 14.4 Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: 2001 Sep 25 Manual soldering 73 Philips Semiconductors Product specification Digital video encoder 14.5 SAA7102; SAA7103 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, HBGA, LFBGA, SQFP, TFBGA not suitable suitable(2) HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS not PLCC(3), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO REFLOW(1) suitable suitable suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 15 DATA SHEET STATUS DATA SHEET STATUS(1) PRODUCT STATUS(2) DEFINITIONS Objective specification Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Preliminary specification Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. Product specification Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 2001 Sep 25 74 Philips Semiconductors Product specification Digital video encoder SAA7102; SAA7103 16 DEFINITIONS 17 DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 18 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 2001 Sep 25 75 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: [email protected]. © Koninklijke Philips Electronics N.V. 2001 SCA73 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 753505/01/pp76 Date of release: 2001 Sep 25 Document order number: 9397 750 08371