TCM8230MD (A) Ver. 1.20
TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
TCM8230MD (A)
TENTATIVE
VGA CAMERA MODULE
The TCM8230MD(A) is a camera module which includes area color image sensor embedded with camera signal
processor that meets with VGA format. In the sensor area 492 vertical and 660 horizontal signal pixels, and the image
size meets with 1/6 inch optical Format. Use of the CMOS process enables low power consumption operations. It
also provides excellent color reproduction through its primary color filter, and embedded camera signal processor
enables small and simple camera system. And this module can be assembled by the socket which is suitable for the
reflow soldering. So it is fit to use as an image input device for digital still cameras, PC cameras and mobile devices.
Features
1. General
•
•
•
•
Module size : 6(W) x 6(D) x 4.5(H) mm
2
I C BUS I/F
2
Sleep mode operation (It can be controlled by the I C Bus command)
Power supply : 2.8+/-0.2V or 2.5+/-0.2V (Sensor(photo diode), I/O) and 1.5+/-0.1V(Sensor(A/D converter), Digital)
2. Sensor
•
•
•
•
•
•
•
•
Optical size
: 1/6 inch optical format
Total pixel numbers : 698(H)x502(V)
Signal pixel numbers : 660(H)x492(V)
Pixel pitch
: 3.75um(H)x3.75um(V) (square pixel)
Color filter
: RGB color filter, Bayer arrangement (GR line and GB line are arranged alternately.)
Frame rate
: Max 30fps
Raw data bit precision : 10bit
Feed back clamp
3. Camera signal processing
• Maximum exposure time can be adjust from 1V to 15V
• Digital outputs
YUV=4:2:2 or RGB=5:6:5 ( 8bit parallel output )
• Picture size
VGA, QVGA, QQVGA, CIF, QCIF, subQCIF ( Sub-sampling , Windowing )
• Readout internal parameters
Sensor gain setting, Electrical shutter exposure period, ALC and AWB reference value
• Auto electrical shutter control (AES), auto gain control (AGC) and auto white balance (AWB) circuit
• Flickerless auto luminance control (ALC=AES+AGC) and auto flicker detection circuit for AC 50Hz / 60Hz fluorescent light
• Automatically blemish correction
• Vertical and Horizontal flip mode
● TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or
jail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to
observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or
damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating range as set forth in the most
recent products specif ications. Also, please keep in mind the precautions and conditions setf orth in the TOSHIBA Semiconductor Reliability Handbook.
● The products described in this document are subject to f oreign exchange and f oreign trade control laws.
● The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA
CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by
implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others.
● The inf ormation contained herein is subject to change without notice.
04/01/05
1/27
TCM8230MD (A) Ver. 1.20
UPDATE INFORMATION
Ver. 1.20
Ver. 1.10
Ver. 1.09
Ver. 1.08
Ver. 1.07
Ver. 1.06
Ver. 1.05
Ver. 1.04
Ver. 1.03
Ver. 1.02
Ver. 1.01
Ver. 1.00
04/01/05
Jan-05, 2004
Dec-23, 2003
Dec-16, 2003
Oct-29, 2003
Oct-07, 2003
Sep-19, 2003
Sep-08, 2003
Aug-11, 2003
Jul-31, 2003
Jul-16, 2003
Jul-03, 2003
Jun-25, 2003
2/27
TCM8230MD (A) Ver. 1.20
BLOCK DIAGRAM
TCM8230MD
Double Lens
VGA CMOS Sensor
CDS / AGC
ADC
Signal
Processing
Image
Area
TG / SG
AWB
ALC
I2C bus I/F
Connecting terminals
PVDD IOVSS
IOVDD
(2.8V)
SDA
SCL
HD
DVSS DOUT0
RESET
DVDD AVSS
to
VD EXTCLK
(1.5V)
DOUT7
DCLK
Host system
CDS : Correlated Double Sampling
AGC : Automatic Gain Control
ADC : Analog to Degital Converter
TG : Timing pulse Generator
SG : Sync pulse Generator
AWB : Auto White Balance
ALC : Auto Luminance Control
04/01/05
3/27
TCM8230MD (A) Ver. 1.20
6
DVDD
7
DVSS
8
VD
9
HD
5
4
3
2
1
SDA
SCL
RESET
EXTCLK
PVDD
PIN LAYOUT
TCM8230MD
TOP (Lens side) view
DOUT7
20
DOUT6
19
DOUT5
18
DOUT4
17
IOVDD
16
Orientation
04/01/05
DOUT1
DOUT2
DOUT3
IOVSS
DCLK
DOUT0
10
11
12
13
14
15
4/27
TCM8230MD (A) Ver. 1.20
PIN FUNCTIONS
No.
1
2
3
4
5
NAME
PVDD
EXTCLK
RESET
SCL
SDA
I/O
I
I
I
I/O
6
DVDD
-
7
DVSS
-
8
9
10
11
12
13
14
15
16
17
18
19
20
VD
HD
DCLK
DOUT0
DOUT1
DOUT2
DOUT3
IOVSS
IOVDD
DOUT4
DOUT5
DOUT6
DOUT7
O
O
O
O
O
O
O
O
O
O
O
04/01/05
FUNCTION
VDD for sensor (photo diode) ( 2.8V )
Clock for external input
RESET terminal ("L" active)
Clock for I2C-bus command
Data for I2C-bus command
VDD for digital circuits, (1.5V )
VDD for sensor (A/D converter) (1.5V )
GND for digital circuits
GND for sensor (A/D converter)
GND for sensor (photo diode)
Vertical syncronization pulse output
Holizontal syncronization pulse output
Clock for output data
Data output (LSB)
Data output
Data output
Data output
GND for I/O
VDD for I/O ( 2.8V )
Data output
Data output
Data output
Data output (MSB)
5/27
TCM8230MD (A) Ver. 1.20
INTERFACE CIRCUITS
PIN No.
NAME
I/O
INTERFACE CIRCUIT
IOVDD
2
EXTCLK
IOVDD
IOVDD
GND
GND
I
IOVDD
GND
GND
IOVDD
IOVDD
IOVDD
3
RESET
("L" active)
GND
I
GND
GND
IOVDD
4
SCL
I
GND
GND
IOVDD
5
SDA
I/O
GND
GND
8-14,
17-20
04/01/05
DOUT0 to DOUT7,
HD, VD, DCLK
GND
IOVDD
IOVDD
GND
GND
O
6/27
TCM8230MD (A) Ver. 1.20
PIXEL ARRANGEMENT
1. V_INV=0
Dummy pixels
OB 44pixels
Light shielded pixels
2pixels
Signal pixels 660pixels
B Gb B Gb B Gb B Gb B Gb
B Gb B Gb B Gb B Gb B Gb
Gr R Gr R Gr R Gr R Gr R
Gr R Gr R Gr R Gr R Gr R
492
B Gb B Gb B Gb B Gb B Gb
B Gb B Gb B Gb B Gb B Gb
491
Gr R Gr R Gr R Gr R Gr R
Gr R Gr R Gr R Gr R Gr R
Signal pixels 494pixels
490
489
488
Vertical
487
6
5
4
B Gb B Gb B Gb B Gb B Gb
B Gb B Gb B Gb B Gb B Gb
3
Gr R Gr R Gr R Gr R Gr R
Gr R Gr R Gr R Gr R Gr R
R: Red pixels
Gr,Gb: Green pixels
660
659
658
657
Horizontal
656
Start pixel
OB: Optical Black
655
6
5
4
Gr R Gr R Gr R Gr R Gr R
3
B Gb B Gb B Gb B Gb B Gb
Gr R Gr R Gr R Gr R Gr R
2
B Gb B Gb B Gb B Gb B Gb
1
1
2
B: Blue pixels
2. V_INV =1 (Vertical flip mode)
Start pixel
Dummy pixels
OB 44pixels
Light shielded pixels
2pixels
Signal pixels 660pixels
1
B Gb B Gb B Gb B Gb B Gb
B Gb B Gb B Gb B Gb B Gb
2
Gr R Gr R Gr R Gr R Gr R
Gr R Gr R Gr R Gr R Gr R
3
B Gb B Gb B Gb B Gb B Gb
B Gb B Gb B Gb B Gb B Gb
4
Gr R Gr R Gr R Gr R Gr R
Gr R Gr R Gr R Gr R Gr R
Signal pixels 494pixels
5
Vertical
6
487
488
489
490
491
B Gb B Gb B Gb B Gb B Gb
B Gb B Gb B Gb B Gb B Gb
492
Gr R Gr R Gr R Gr R Gr R
Gr R Gr R Gr R Gr R Gr R
OB: Optical Black
04/01/05
R: Red pixels
Gr,Gb: Green pixels
660
659
658
657
656
Horizontal
655
6
5
4
3
2
B Gb B Gb B Gb B Gb B Gb
Gr R Gr R Gr R Gr R Gr R
1
B Gb B Gb B Gb B Gb B Gb
Gr R Gr R Gr R Gr R Gr R
B: Blue pixels
7/27
TCM8230MD (A) Ver. 1.20
CONTROL I/F
TCM8230MD(A) control interface configuration is based on fast mode I2C bus.
Register setting can be changed via I2C bus.
All register settings are able to read via I2C bus.
Write mode
S Slave Address
0 A
Sub Address
MSB 7bit
A
Data 1
8bit
A
Data n
8bit
A P
8bit
Read mode
S Slave Address
0 A
Sub Address
MSB 7bit
A S Slave Address
8bit
MSB 7bit
: Host Command
S
: Start condition
: TCM8230MD(A)
P
: End condition
A
: Acknowledge
Start condition, End condition
A
8bit
Data n
A P
8bit
SDA
S
SCL
P
Start condition
End conditon
Acknowledge
data line stable ;
data valid
change of data allowed
Slave address
HiZ
SDA
from trancemitter
SDA
from reciver
SCL
from master
Data 1
Bit Transfer
SDA
SCL
1
A6 A5 A4 A3 A2 A1 A0 R/W
0 1 1 1 1 0 0 1/0
HiZ
* TCM8230MD(A) use 7bit Slave address
S
1
8
9
Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Rights to use these
components in an I2C system, provided that the system conforms to the I2C Standard Specification as
defined by Philips.
04/01/05
8/27
TCM8230MD (A) Ver. 1.20
INTERNAL REGISTER
DEC
ADDRESS
BIN
fast
last
HEX
BIT7(MSB)
0 00000000
1 00000001
00
01
Test Mode
2 00000010
02
3 00000011
03
4 00000100
04
5 00000101
05
ESRLIM[1:0]
0:AUTO
1:MANUAL
6 00000110
7 00000111
06
07
ESRSPD[7:0]
AG[7:0]
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
default(ROM data)
BIT0(LSB) B7B6B5B4 B3B2B1B0 HEX
0 1 1 1 0 0 0 0
0 0 0 1 0 0 0 0
70
10
0 0 0 0
40
1 0 0 0
0 0 0 0
80
0 0 0 0
1 1 1 1
0F
0 0 0 0
0 0 1 0
02
0 0 0 0
1 1 0 1
1 1 0 0 0 0 0 0
0D
C0
0 0 1 1
1 0 0 0
38
0 1 0 0
0 0 0 0
40
0 0 0 0
00
FPS
ACF
DCLKP
ACFDET
0:30fps
1:15fps
0:50Hz
1:60Hz
0 : normal
1: reverse
1 1 0 0
0 : AUTO
1: MANUAL
DOUTSW DATAHZ
0:ON
1:0FF
0:OUT
1:Hi-Z
V_INV
H_INV
0:normal
1:invert
0:normal
1:invert
PICSIZ[3:0] 0h:VGA 1h:QVGA(f) 2h:QVGA(z)
PICFMT
3h:QQVGA(f) 4h:QQVGA(z) 5h:CIF(f)
0:YUV422
6h:QCIF(f) 7h:QCIF(z) 8h:subQCIF(f)
1:RGB565
9h:subQCIF(z)
ESRLSW[1:0]
0h : Short
1h :
2h & 3h :
Long
CM
0:COLOR
1:B/W
V_LENGTH[3:0]
ALCSW
ESRSPD[12:8]
ALCMODE[1:0]
8 00001000
08
9 00001001
09
0h:Centaer Weight
1h:Average
2h:Center only
3h:Backlight
ALCH[3:0]
ALCL[7:0]
AWBSW
10 00001010
0A
0:AUTO
1:MANUAL
0 0 0 0
11 00001011
12 00001100
0B
0C
MRG[7:0]
MBG[7:0]
0 1 0 0
0 0 0 0
0 1 0 0
0 0 0 0
40
40
13 00001101
0D
0:ON
1:OFF
0 0 0 0
0 0 0 0
00
14 00001110
0E
HDTG[7:0]
0 0 1 0
1 1 1 1
15 00001111
16 00010000
17 00010001
0F
10
11
VDTG[7:0]
HDTCORE[3:0]
0 0 0 0
0 1 0 0
0 0 1 0
0 0 1 0
CONT[7:0]
1 0 0 1
1 0 1 0
18 00010010
19 00010011
12
13
BRIGHT[7:0]
VHUE[6:0]
0 0 0 0 1 1 0 0
0 0 0 0 1 0 1 0
20 00010100
21 00010101
14
15
UHUE[6:0]
22 00010110
23 00010111
16
17
24 00011000
18
25 00011001
19
GAMSW
0 0 1 1
1 0 0 0
UGAIN[5:0]
0 0 1 1
1 0 0 0
0 0 0 0
0 0 0 1
0 0 1 0
0 1 1 1
0 0 0 0 0 1 0 0
04
0 0 1 0 0 0 0 0
20
0 1 0 0 0 1 1 0
46
1 0 0 1
1 1 1 0
1 0 0 0
0 0 1 1
9E
83
0 1 1 0 1 0 0 0
68
0 0 0 0 0 0 0 0
00
VDTCORE[3:0]
0 0 0 0 1 0 0 0
UVCORE[3:0]
SATU[6:0]
MHMODE MHLPFSE
0:
L
0: YMODE[1:0]
1:
26 00011010
VGAIN[5:0]
2F
04
22
9A
0C
0A
08
38
38
01
27
MIXHG[2:0]
1:
LENS[5:0]
1A
LENSRPO
L 0:Gain
27 00011011
1B
AGLIM[2:0]
28 00011100
29 00011101
1C
1D
ES100S[7:0]
ES120S[7:0]
30 00011110
1E
D_MASK[1:0]
31 00011111
1F
SLEEPSW
0:ACTIVE
1:SLEEP
up
1:Gain
down
CODESW
0:OFF
1:OUT
LENSRGAIN[3:0]
CODESEL HSYNCSEL TESPIC
0 : original 0 : normal 0:Not out
1 : ITU656 1 :
1:Out
PICSEL[1:0]
0h:Colorbar 1h:Ramp1
2h :Ramp2
SRST
0:OFF
1:reset
The registers of gray mesh (unassigned registers) are not defined. Input data of the registers of gray mesh
must input “0”. The registers of testmode must input default data.
04/01/05
9/27
TCM8230MD (A) Ver. 1.20
DEC
ADDRESS
BIN
fast
HEX
last
BIT7(MSB)
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
default
BIT0(LSB) B7B6B5B4 B3B2B1B0 HEX
0 0 1 0 0 0 1 1
00
01
26
40
27
5F
00
16
23
FSSTBPH[3:0]
0 0 0 0 1 0 0 0
08
FSSTBW[3:0]
0 0 0 0 1 0 0 0
0 0 0 0 0 1 0 0
0 0 0 0 0 0 0 0
08
04
00
00
32 00100000
20
HNUM[7:0]
0 0 0 0 0 0 0 0
33 00100001
34 00100010
21
22
HPPH[7:0]
35 00100011
23
VRRPH[6:0]
HPPH[8]
HDSPPH[7:0]
0 0 0 0 0 0 0 1
0 0 1 0 0 1 1 0
36 00100100
24
HDSPPH[8] VDSPPH[6:0]
0 0 1 0 0 1 1 1
37 00100101
38 00100110
25
26
HAPRPH[7:0]
0 1 0 1 1 1 1 1
0 0 0 0 0 0 0 0
39 00100111
27
HOUTPH[7:0]
40 00101000
28
41 00101001
29
42 00101010
43 00101011
2A
2B
HOUTPH[8]
FSSTBSW
0 : NOT
OUT
1 : OUT
44 00101100
2C
SCMD[15:8]
45 00101101
2D
SCMD[7:0]
0 1 0 0 0 0 0 0
HAPRPH[8]
0 0 0 1 0 1 1 0
VOUTPH[6:0]
FSSTBPOL
0 : normal
1 : invert
SCMD[19:16]
TCSB1L
0:
1:
TCRAMS
0:
1:
0 0 0 0 0 0 0 0
TCPEROSW [2:0]
TCSBIN
0:
1:
TCRAM
0:
1:
TROM[1:0]
0 0 0 0 0 0 0 0
00
TWBS
TWBG
TACDET[1:0]
0 0 0 0 0 0 0 0
00
0 0 0 0 0 0 0 0
00
0 0 0 0 0 0 0 0
00
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
00
00
00
00
00
00
00
8C
CF
80
00
46 00101110
2E
47 00101111
2F
48 00110000
30
49 00110001
31
50 00110010
32
51 00110011
33
ESROUT[7:0]
52 00110100
53 00110101
34
35
AGOUT[7:0]
54 00110110
36
ALCDATA[7:0]
0 0 0 0 0 0 0 0
55 00110111
56 00111000
37
38
AWBRYDA[7:0]
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
TSPCHK
TCPERAGC TALCRST
0:
1:
TGAMROM
0:
1:
TCSB[3:0]
TALCDISP
0:
1:
TALCOSW[2:0]
PBDISP[1:0]
TDISP[1:0]
ESROUT[14:8]
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
DGOUT[5:0]
AWBBYDA[7:0]
57 00111001
39
AGSLOW1[1:0]
58 00111010
59 00111011
3A
3B
DETSEL[3:0]
60 00111100
3C
61 00111101
3D
62 00111110
3E
63 00111111
3F
REJHLEV[7:0]
FPSLNKS
ALCLOCK
W
ALCSPD[1:0]
0:
0:
1:
1:
SHESRSW ESLIMSEL
0:Disable
0:
SHESRSPD[1:0]
1:Enable
1:
AGMIN[7:0]
AGSLOW2[1:0]
FLLSMODE[1:0]
FLLSLIM[3:0]
1 0 0 0 1 1 0 0
ACDETNC[3:0]
1 1 0 0 1 1 1 1
1 0 0 0 0 0 0 0
DG[5:0]
ALCSTEP[1:0]
REJH[1:0]
0 0 0 1 0 1 1 1
17
ELSTEP[1:0]
ELSTART[1:0]
1 0 0 0 0 1 0 1
85
1 1 0 0 0 0 0 0
C0
The registers of gray mesh (unassigned registers) are not defined. Input data of the registers of gray mesh must
input “0”. The registers of testmode must input default data.
04/01/05
10/27
TCM8230MD (A) Ver. 1.20
DEC
64
ADDRESS
BIN
0100000
0
fast
HEX
40
BIT7(MSB)
LI1POL
0:
1:
JAMP
0:
1:
default
last
BIT6
CS1POL
0:
1:
BIT5
LI3POL
0:
1:
BIT4
CS3POL
0:
1:
BIT3
BIT2
BIT1
BIT0(LSB) B7B6B5B4 B3B2B1B0 HEX
DINCKSW
0:
1:
JAMG[6:0]
0 0 0 0
0 0 0 0
00
0 0 0 0
0 0 0 0
00
65 01000001
41
66 01000010
42
PREGRG[5:0]
0 0 0 0 0 0 0 0
00
67 01000011
43
PREGBG[5:0]
0 0 0 0 0 0 0 0
00
68 01000100
44
PRERG[5:0]
0 0 0 1 0 1 0 1
15
69 01000101
45
PREBG[5:0]
0 0 0 1 1 1 1 1
1F
70 01000110
46
0 0 0 0
0 0 0 0
00
71 01000111
72 01001000
73 01001001
47
48
49
MSKBR[6:0]
0 1 0 0
0 1 0 0
MSKGR[6:0]
0 1 0 0
0 1 0 0
MSKRB[6:0]
0 0 1 0
0 0 0 0
44
44
20
74 01001010
4A
MSKGB[6:0]
0 1 0 0
0 1 0 1
45
75 01001011
4B
MSKRG[6:0]
0 1 1 0
0 1 1 0
66
76 01001100
4C
MSKBG[6:0]
0 0 1 1
0 0 0 0
30
DTCYLV[5:0]
1 1 1 0 0 0 0 0
E0
DTCGAIN[5:0]
0 0 1 0 0 0 0 0
20
0 0 0 0 1 0 0 1
09
YLCUTL[5:0]
0 0 0 0 0 1 1 1
07
YLCUTH[5:0]
0 0 1 0 1 1 1 1
2F
0 0 1 0 1 0 1 1
0 1 1 0 0 0 0 0
02
00
2B
60
0 1 0 0 0 0 0 0
40
0 0 0 0 0 1 1 0
06
0 0 1 0
0 0 1 0
22
0 0 1 0
0 0 1 1
23
08
04
08
08
08
HDTCSW
0:
1:
HDTPSW
0:
1:
LI12POL
0:
1:
YLCUTLMS
K 0:
1:
YLCUTHM
SK 0:
1:
VDTCSW
0:
1:
VDTPSW
0:
1:
CS12POL
0:
1:
77 01001101
4D
78 01001110
4E
79 01001111
4F
80 01010000
50
81 01010001
51
82 01010010
52
UVSKNC[6:0]
0 0 0 0 0 0 1 0
83 01010011
53
UVLJ[6:0]
0 0 0 0 0 0 0 0
84 01010100
85 01010101
54
55
86 01010110
56
87 01010111
57
DTLLIMSW
DTLYLIM [3:0]
0:
1:
WBGMIN[7:0]
WBGMAX[7:0]
AWBCSPO
WBDIVCLP
LE
WBNOLJ[1:0]
0:
0:
1:
1:
ALLAREA
0:
1:
WBLOCK
0:
1:
WBNOLJS WB2IM1
0: 0:
C
1:
1:
WBSPDUP[1:0]
WBDIVSC[2:0]
WB2SP [3:0]
88 01011000
58
89 01011001
59
90 01011010
91 01011011
5A
5B
PBDLV[7:0]
0 0 0 0
1 0 0 0
PBC1LV[7:0]
0 0 0 0
0 1 0 0
92 01011100
5C
PBC2LV[7:0]
93 01011101
94 01011110
5D
5E
PBC3LV[7:0]
0 0 0 0 1 0 0 0
0 0 0 0 1 0 0 0
0 0 0 0 1 0 0 0
KIZUSW
0:OFF
1:ON
PBC4LV[7:0]
PBRDSW
ABCSW[1:0]
The registers of gray mesh (unassigned registers) are not defined. Input data of the registers of gray mesh
must input “0”. The registers of testmode must input default data.
04/01/05
11/27
TCM8230MD (A) Ver. 1.20
OUTLINE OF INTERNAL REGISTER
* Frame rate setting (30fps, 15fps )
* Picture size setting of digital output ( VGA, QVGA, QQVGA, CIF, QCIF, subQCIF )
* Selection of digital data output format (8bit YUV422, RGB565)
* Sync. code setting ( ON/OFF, 2 mode )
* Color signal adjustment ( Masking, color axis correction, saturation, etc. )
* Luminance signal adjustment ( Contrast, Brightness, Gamma, H,V edge enhancement )
* ALC ON/OFF
* ALC mode setting ( area selection, speed selection, flicker reduction mode setting )
* AWB ON/OFF
* Vertical and Horizontal flip
* Sleep mode setting
* Some kinds of correction setting ( Lens shading correction etc. )
8bit parallel image data
DOUT0
DOUT1
DOUT2
DOUT3
DOUT4
DOUT5
DOUT6
DOUT7
1st
U0(n)
U1(n)
U2(n)
U3(n)
U4(n)
U5(n)
U6(n)
U7(n)
YUV mode
2nd
3rd
Y0(n)
V0(n)
Y1(n)
V1(n)
Y2(n)
V2(n)
Y3(n)
V3(n)
Y4(n)
V4(n)
Y5(n)
V5(n)
Y6(n)
V6(n)
Y7(n)
V7(n)
4th
Y0(n+1)
Y1(n+1)
Y2(n+1)
Y3(n+1)
Y4(n+1)
Y5(n+1)
Y6(n+1)
Y7(n+1)
RGB mode
1st
2nd
B0
G3
B1
G4
B2
G5
B3
R0
B4
R1
G0
R2
G1
R3
G2
R4
Image size format
Image size Display mode
VGA
QVGA
QQVGA
CIF
QCIF
subQCIF
Full
Full
Zoom x 2
Full
Zoom x 2
Full
Full
Zoom x 2
Full
Zoom x 2
Pixels
per H
640
Effective
H lines
480
320
240
160
120
352
288
176
144
128
96
Start point
(H, V)
(1, 1)
(1, 1)
(161, 121)
(1, 1)
(161, 121)
(21, 1)
(21, 1)
(173, 121)
(1, 1)
End point
(H, V)
(640 ,480)
(639, 479)
(480 ,360)
(637, 477)
(479, 359)
(608, 478)
(608, 478)
(466, 360)
(636, 476)
(161, 121)
(479, 359)
DCLK
mode
1
1/2
1
Operation
mode
Normal
Low power
Normal
1/2
Low power
1
1/2
1
Normal
Low power
Normal
1/2
Low Power
Resizing method
Sub-sampling from VGA
Windowing from VGA
Sub-sampling from QVGA(f)
Sub-sampling from VGA
3/5 filtering from VGA
3/5 filtering from QVGA(f)
Windowing from CIF
4/5 filtering from QQVGA(f)
1st: 3/5 filtering from QVGA(f)
2nd: Sub-sampling from "1st"
QVGA(f) means QVGA full.
QQVGA(f) means QVGA full.
VGA
QVGA
QQVGA
CIF
QCIF
04/01/05
Video Graphics Array
Quarter VGA
Quarter QVGA
Common Intermediate Format
Quarter CIF
12/27
TCM8230MD (A) Ver. 1.20
SYNCHRONIZATION CODE
Synchronization code output format
CODESW=1
DCLK
00h
FFh
DOUT7∼0
00h
Code
CODESW(Address=1Eh, Bit5) is able to add synchronization codes. “Code“ part is changed Mode1 or Mode2
by CODESEL(Address=1Eh, Bit4).
Mode1 （Original format, CODESEL=0）
These codes only exists in active lines
Frame
Start
Code
Active Line 1
Line
End
Line
Start
Code
Code
Active Line 2
Line
End
Line
Start
Code
Code
Code
Picture
Code
02
00
00
00
Blanking
Blanking
Line 1
Line 2
Line 3
Line 4
01
01
01
01
00
00
Active Line 480
(VGA)
Frame
End
Code
01
Line 480 (VGA)
Line 240 (QVGA)
Line 120 (QQVGA)
Line 288 (CIF)
Line 144 (QCIF)
Line 96 (subQCIF)
03
Blanking
Blanking
640 pixels (VGA)
320 pixels (QVGA)
160 pixels (QQVGA)
352 pixels (CIF)
176 pixels (QCIF)
128 pixels (subQCIF)
Line start code : FFh 00h 00h 00h
Line end code : FFh 00h 00h 01h
Frame start code : FFh 00h 00h 02h
Frame end code : FFh 00h 00h 03h
04/01/05
13/27
TCM8230MD (A) Ver. 1.20
Mode2 (ITU656 format, CODESEL=1)
These codes exists in every lines
Code
1
0
V
H
V : 1:Blanking
0
0
0
0
0:Active Line
H : 1:End of Active Pixel
0:Start of Active Pixel
Code
Picture
Code
A0
A0
80
80
80
80
Blanking
Blanking
Line 1
Line 2
Line 3
Line 4
B0
B0
90
90
90
90
80
90
80
Line 480 (VGA)
Line 240 (QVGA)
Line 120 (QQVGA)
Line 288 (CIF)
Line 144 (QCIF)
Line 96 (subQCIF)
90
A0
A0
Blanking
Blanking
B0
B0
640 pixels (VGA)
320 pixels (QVGA)
160 pixels (QQVGA)
352 pixels (CIF)
176 pixels (QCIF)
128 pixels (subQCIF)
Blanking and start active pixel code
Blanking and endactive pixel code
Active line and start active pixel code
Active line and end active pixel code
04/01/05
: FFh 00h 00h A0h
: FFh 00h 00h B0h
: FFh 00h 00h 80h
: FFh 00h 00h 90h
14/27
TCM8230MD (A) Ver. 1.20
DATA OUTPUT TIMING CHART
TCM8230MD supports 2 HD pulses, one is “Blanking pulse”, and another one is “Normal pulse”.
You can choose HD pulse by HSYNCSEL (Address=1Eh Bit3).
Pixel Size mode (HD=Blanking pulse)
1. Vertical timing (HSYNCSEL=1)
Normal operation mode
(VGA, CIF(full), QVGA(zoom), QCIF(zoom))
1 frame
18 lines
VD
507 lines
HD
VGA
full
1
2
CIF
full
1
2
QVGA
zoom
1
2
QCIF
zoom
1
2
3
4
5
3
3
4
5
3
6
7
4
5
6
7
4
5
6
478 479 480
1
2
288
1
2
238 239 240
1
2
144
1
2
7
6
286 287
143 143
7
Low power operation mode
(QVGA(full), QQVGA(full), QQVGA(zoom), QCIF(full), subQCIF(full), subQCIF(zoom))
1 frame
9 lines
VD
254 lines
HD
QVGA
full
1
2
QCIF
full
1
2
QQVGA
full
1
QQVGA
zoom
1
subQCIF
full
1
subQCIF
zoom
1
04/01/05
3
4
3
2
2
3
3
6
7
4
5
3
4
5
4
238
142
4
6
3
2
2
5
7
119
4
5
6
239
1
240
143
144
1
119
120
1
1
120
96
1
96
1
15/27
TCM8230MD (A) Ver. 1.20
2. Horizontal timing (HSYNCSEL=1)
Normal operation mode
(VGA, CIF (full), QVGA (zoom), QCIF (zoom))
DCLK
(DCLKP=0)
VD
156.5 cycles
of DCLK
1 line
280 cycles of DCLK
VGA
full
1280 cycles of DCLK (640 PIXEL)
HD
Data
blanking
1
2
3
638
639
640
blanking
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
856 cycles of DCLK
CIF
full
704 cycles of DCLK (352 PIXEL)
HD
Data
blanking
1
2
3
350
351
blanking
352
920 cycles of DCLK
QVGA
zoom
640 cycles of DCLK (320 PIXEL)
HD
Data
blanking
1
2
3
318
319
blanking
320
1208 cycles of DCLK
QCIF
zoom
HD
Data
352 cycles of DCLK
(176 PIXEL)
blanking
1
2
3
174
175
blanking
176
Blanking Y=0x00, UV=0x80
HNUM=0
Low power operation mode
(QVGA(full), QQVGA(full), QQVGA(zoom), QCIF(full), subQCIF(full), subQCIF(zoom))
DCLK
(DCLKP=0)
VD
156.5 cycles
of DCLK
QVGA
full
920 cycles of DCLK
1
2
3
4
318
319
320
blanking
1
2
3
1
2
3
1
2
3
1
2
3
1208 cycles of DCLK
352 cycles of DCLK (176 PIXEL)
blanking
1
2
175
176
blanking
1240 cycles of DCLK
320 cycles of DCLK
(160 PIXEL)
HD
Data
subQCIF
full/zoom
blanking
HD
Data
QQVGA
full/zoom
640 cycles of DCLK (320 PIXEL)
HD
Data
QCIF
full
1 line
blanking
1
159
160
blanking
1304 cycles of DCLK
256 cycles of DCLK
(128 PIXEL)
HD
Data
blanking
1
128
blanking
Blanking Y=0x00, UV=0x80
04/01/05
16/27
TCM8230MD (A) Ver. 1.20
Pixel Size mode (HD=Normal pulse)
1. Vertical timing (HSYNCSEL=0)
Normal operation mode
(VGA, CIF(full), QVGA(zoom), QCIF(zoom))
1 frame
18 lines
VD
507 lines
HD
VGA
full
1
2
CIF
full
1
2
QVGA
zoom
1
2
QCIF
zoom
1
2
4
3
5
3
4
3
5
3
6
7
4
5
6
7
4
5
6
478 479 480
1
2
288
1
2
238 239 240
1
2
144
1
2
286 287
7
6
7
143 143
Low power operation mode
(QVGA(full), QQVGA(full), QQVGA(zoom), QCIF(full), subQCIF(full), subQCIF(zoom))
1 frame
9 lines
VD
254 lines
HD
QVGA
full
1
2
QCIF
full
1
2
QQVGA
full
1
QQVGA
zoom
1
subQCIF
full
1
subQCIF
zoom
1
04/01/05
3
4
3
2
2
3
3
6
7
4
5
3
4
2
2
5
5
142
4
6
3
4
238
7
119
6
1
240
143
144
1
119
120
1
120
1
96
4
5
239
1
1
96
17/27
TCM8230MD (A) Ver. 1.20
2. Horizontal timing (HSYNCSEL=0)
Normal operation mode
(VGA, CIF (full), QVGA (zoom), QCIF (zoom))
DCLK
(DCLKP=0)
VD
156.5 cycles
of DCLK
1 line
156 cycles of
DCLK
VGA
full
HD
DOUT
blanking
156 cycles of
DCLK
1404 cycles of DCLK
1
2
3
638
639
640
156 cycles of
DCLK
CIF
full
DOUT
blanking
1
2
3
350
156 cycles of
DCLK
QVGA
zoom
blanking
blanking
352
1
2
3
318
319
blanking
320
156 cycles of
DCLK
QCIF
zoom
DOUT
blanking
1
2
3
174
175
blanking
176
3
4
1
2
3
4
1
2
3
4
1
2
3
4
156 cycles of
DCLK
1404 cycles of DCLK
HD
2
156 cycles of
DCLK
1404 cycles of DCLK
HD
DOUT
351
1
156 cycles of
DCLK
1404 cycles of DCLK
HD
blanking
Blanking Y=0x00, UV=0x80
HNUM=0
Low power operation mode
(QVGA(full), QQVGA(full), QQVGA(zoom), QCIF(full), subQCIF(full), subQCIF(zoom))
DCLK
(DCLKP=0)
VD
156.5 cycles
of DCLK
QVGA
full
1
2
3
4
318
319
320
blanking
2
3
1
2
3
1
2
3
1
2
3
1404 cycles of DCLK
blanking
1
2
175
156 cycles of
DCLK
blanking
176
blanking
156 cycles of
DCLK
1404 cycles of DCLK
HD
1
159
160
blanking
156 cycles of
DCLK
156 cycles of
DCLK
1404 cycles of DCLK
HD
DOUT
1
156 cycles of
DCLK
HD
DOUT
subQCIF
full/zoom
blanking
156 cycles of
DCLK
DOUT
QQVGA
full/zoom
156 cycles of
DCLK
1404 cycles of DCLK
HD
DOUT
QCIF
full
1 line
156 cycles of
DCLK
blanking
1
128
blanking
Blanking Y=0x00, UV=0x80
HNUM=0
04/01/05
18/27
TCM8230MD (A) Ver. 1.20
Exposure mode
TCM8230MD supports long exposure time mode (ESRLSW (Address=04h, Bit5,4)= 1) and extra-long exposure time
mode (ESRLSW (Address=04h Bit5,4)= 2, 3).
Vertical timing
Normal mode
VD
ESRLSW=0
Data
Long exp.
mode
ESRLSW=1
1st frame 2nd frame 3rd frame
VD
blanking
Data
Extra-long
exp. mode
VD
ESRLSW=2,3
V_LENGTH=3
Data
blanking
1st frame
1st frame
blanking
blanking
2nd frame
2nd frame
blanking
blanking
3rd frame
blanking
When use these modes, you should be sent below I2C commands before entry these modes.
ESRLSW (Address=04h Bit5,4)= 1, 2 or 3
Address=22h, Data=10h (Default Data=26h)
Address=24h, Data=0Fh (Default Data=27h)
Address=28h, Data=06h (Default Data=23h)
04/01/05
19/27
TCM8230MD (A) Ver. 1.20
POWER ON SEQUENCE
EXTCLK
(V p-p = 2.8V)
DVDD
(1.5V)
100ms>x>=0ns
PVDD
(2.8V)
100ms>x>=0ns
IOVDD
(2.8V)
>0ns
>=100 cycles of EXTCLK
RESET
(from Outside)
>=2000 cycles of EXTCLK
SCL/SDA
Commands are available
*
VD
> 1V
DOUT
x
*
1st picture
2nd picture
((VOUTPH + 3) - VRRPH) + 4
In default case: VOUTPH=35dec, VRRPH=38dec, ((35 + 3) - 38) + 4 = 4H
D_MASK=1
TCM8230MD cannot output pictures after power on immediately. You should be sent some I2C commands
after power on as below.
Address=03h, Data=00h (Default Data=80h)
POWER OFF SEQUENCE
EXTCLK
(V p-p = 2.8V)
IOVDD
(2.8V)
100ms>x>0ns
PVDD
(2.8V)
DVDD
100ms>x>=0ns
(1.5V)
100ms>x>=0ns
04/01/05
20/27
TCM8230MD (A) Ver. 1.20
SLEEP MODE SEQUENCE
1. From normal operation to sleep mode
2 frames
VD
*
SCL/SDA
Sleep Command
DOUT
Picture
Operation
Mode
Normal operation
Sleep mode
EXTCLK
*
((VOUTPH + 3) - VRRPH) + 4
In default case: VOUTPH=35dec, VRRPH=38dec, ((35 + 3) - 38) + 4 = 4H
2. From sleep mode to normal operation
VD
3H
1 frame
SCL/SDA
Wake up Command
> 1 frame
DOUT
x
Operation
Mode
Sleep mode
Picture
Normal operation
EXTCLK
D_MASK=1
Some registers data, AWB calculated data and ALC calculated data are kept the last values during sleep mode.
04/01/05
21/27
TCM8230MD (A) Ver. 1.20
MAXIMUM RATING
Power supply voltage
Storage tempature
RATING
1.5V
-0.3 to 3.0
-30 to 85
2.8V
-0.3 to 3.6
UNITS
V
Degree C
RECOMMENDED OPERATING CONDITION
Power supply IOVDD, PVDD*
voltage
DVDD
Operational tempature
MIN
2.6
2.3
1.4
-20
TYP
2.8
2.5
1.5
-
MAX
3.0
2.7
1.6
60
UNITS
V
Degree C
*If using 2.5V, must input setting command. (Default setting is 2.8V.)
04/01/05
22/27
TCM8230MD (A) Ver. 1.20
ELECTRICAL CHARACTERISTICS
DC Characteristic ( Ta=25 degree C, DVDD(=AVDD) =1.5V, PVDD= IOVDD =2.8V )
1. POWER
ITEM
POWER
VGA(15fps)
CONDITION
(Normal operation mode)
Sleep mode
MIN
-
TYP
40
-
MAX
TBD
TBD
UNITS
mA
uA
* Measurement condition : Machbeth chart (full)
*Peak current = 180mA
2. EXTCLK
Rectangular
shape
ITEM
LOW level input voltage
SYMBOL
VIL;EXTCLK
CONDITION
-
MIN
-0.3
TYP
-
MAX
IOVDD*0.2
HIGH level input voltage
VIH;EXTCLK
IOVDD
3.0
V
IIL;EXTCLK
VIN=GND
IOVDD*0.8
LOW level input current
-10
-
10
uA
HIGH level input current
DUTY
IIH;EXTCLK
-
VIN=IOVDD
-
-10
45/55
50/50
10
55/45
uA
%
UNITS
V
NOTES
*1
1) Duty referred to 50% level of input EXTCLK
3. SCL and SDA
ITEM
LOW level input voltage
SYMBOL
VIL;SCL
MIN
0.0
TYP
-
MAX
0.4
UNIT
V
HIGH level input voltage
VIH;SCL
IOVDD*0.7
IOVDD
3.0
V
LOW level input voltage
VIL;SDA
0.0
-
0.4
V
HIGH level input voltage
VIH;SDA
IOVDD*0.7
IOVDD
3.0
V
LOW level output voltage (IOL=4mA)
VOL;SDA
0.0
-
0.4
V
SCL
SDA
NOTES
4. DOUT0 to DOUT7, DCLK, HD and VD
ITEM
SYMBOL
DOUT0 to DOUT7, LOW level output voltage (IOL=2mA) VOL;DATA
DCLK, HD and VD HIGH level output voltage (IOH=-2mA) VOH;DATA
MIN
0.0
TYP
-
MAX
0.4
UNIT
V
2.4
IOVDD
-
V
NOTES
5. RESET
ITEM
SYMBOL CONDITION
LOW level input voltage VIL;RESET
HIGH level input voltage VIH;RESET
-
MIN
-0.3
TYP
-
MAX
IOVDD*0.2
UNIT
V
IOVDD*0.8
IOVDD
3.0
V
LOW level input current
IIL;RESET
VIN=GND
-10
-
10
uA
HIGH level input current
IIH;RESET
VIN=IOVDD
-10
-
10
uA
04/01/05
NOTES
23/27
TCM8230MD (A) Ver. 1.20
AC Characteristic ( Ta=25 degree C, DVDD(=AVDD) =1.5V, PVDD= IOVDD =2.8V )
1. EXTCLK
ITEM
SYMBOL
Clock frequency
fEXTCLK
Rise time
tr;EXTCLK
Fall time
tf;EXTCLK
FPS
0
MIN
TYP
11.90
24.54
-
-
-
5
ns
-
-
-
5
ns
1
MAX
25.00
27.00
UNITS
NOTES
MHz
*1
*2
1) FPS : Address=02h, Bit7
2) All values referred to VIHmin and VILmax levels
fEXTCLK
VIH
VIL
Tr;EXTCLK
Tf;EXTCLK
2. EXTCLK input circuit
EXTCLK
2.8V
0V
TCM8230MD
Duty 50:50
04/01/05
24/27
TCM8230MD (A) Ver. 1.20
3. SCL and SDA
ITEM
Clock frequency
SCL
SDA
SYMBOL
fSCL
MIN
-
MAX
400
UNITS
KHz
Low period
tLOW;SCL
1.3
-
us
High period
tHIGH;SCL
0.6
-
us
Rise time
tr;SCL
-
300
ns
Fall time
tf;SCL
-
300
ns
Rise time
tr;SDA
-
300
ns
tf;SDA
-
300
ns
Fall time
Hold time(repeated) START condition
After this period, the first clock pulse is
Setup time for a repeated START condition
tHD;STA
0.6
-
us
tSU;STA
0.6
-
us
Data hold time
tHD;DAT
0
-
ns
Data setup time
tSU;DAT
100
-
ns
Setup time for STOP condition
tSU;STO
0.6
-
us
Normal
tSP1
0
50
ns
Wake-up from sleep mode
tSP2
0
20
ns
Width of spike pulse
NOTES
*1
1) All values referred to VIHmin and VILmax levels
tBUF
SDA
tf
SCL
tr
tLOW
tHD;STA
START
04/01/05
tSU;DAT
tHD;DAT
tf
tHIGH
tHD;STA
tSU;STA
tSP
tr
tSU;STO
RE-START
STOP
START
25/27
TCM8230MD (A) Ver. 1.20
4. DOUT0 to DOUT7, DCLK, HD and VD
ITEM
Rise time
SYMBOL
tr;DCLK
MIN
-
MAX
6
UNITS
ns
Fall time
tf;DCLK
-
6
ns
Rise time
tr;DATA
-
6
ns
Fall time
tf;DATA
-
6
ns
Setup time of data
tpd;SU
10
-
ns
Hold time of data
tpd;HD
10
-
ns
DCLK
DOUT0 to DOUT7,
HD, and VD
NOTES
*1
1) All values referred to VOHmin and VOLmax levels
tf;DCLK
tr;DCLK
VOH;DCLK
DCLK
VOL;DCLK
tpd;SU
tpd;HD
VOH;DATA
Data
Out
VOL;DATA
tr;DATA, tf;DATA
DCLKP=0
CHARACTERISTICS OF LENS
ITEM
Optical format
Holizontal
Field of view
Vertical
Diagonal
F number
TV distotion
Focal length
Focusing area
Manual focusing
Structure
04/01/05
VALUE
1/6
57.4
44.5
69.1
F2.8
-0.4
TBD
TBD
Not avairable
Double lens
UNITS
inch
degree
degree
degree
%
mm
cm
-
26/27
TCM8230MD (A) Ver. 1.20
Appendix 1:
04/01/05
Module Drawing
27/27