PHILIPS TJA1080

TJA1080
FlexRay transceiver
Rev. 02 — 12 July 2007
Product data sheet
1. General description
The TJA1080 is a FlexRay transceiver, which is in line with the FlexRay electrical physical
layer specification V2.1 Rev. A (see Ref. 1). It is primarily intended for communication
systems from 1 Mbit/s to 10 Mbit/s, and provides an advanced interface between the
protocol controller and the physical bus in a FlexRay network.
The TJA1080 can be configured to be used as an active star transceiver or as a node
transceiver.
The TJA1080 provides differential transmit capability to the network and differential
receive capability to the FlexRay controller. It offers excellent EMC performance as well as
high ESD protection.
The TJA1080 actively monitors the system performance using dedicated error and status
information (readable by any microcontroller), as well as internal voltage and temperature
monitoring.
The TJA1080 supports the mode control as used in NXP Semiconductors TJA1054
(see Ref. 2) and TJA1041 (see Ref. 3) CAN transceivers.
2. Features
2.1 Optimized for time triggered communication systems
n
n
n
n
n
n
n
n
Data transfer up to 10 Mbit/s
Usable for 14 V and 42 V powered systems
Very low ElectroMagnetic Emission (EME) to support unshielded cable
Differential receiver with high common-mode range for ElectroMagnetic Immunity
(EMI)
Transceiver can be used for linear passive bus topologies as well as active star
topologies
Auto I/O level adaptation to host controller supply voltage VIO
Bus guardian interface included
Automotive product qualification in accordance with AEC-Q100
TJA1080
NXP Semiconductors
FlexRay transceiver
2.2 Low power management
n Low power management including two inhibit switches
n Very low current in Sleep and Standby mode
n Wake-up via wake-up symbol on the bus lines (remote), negative edge on pin WAKE
(local), and a positive edge on pin STBN if VIO is present
n Wake-up source recognition
n Automatic power-down (in Star-sleep mode) in star configuration
2.3 Diagnosis (detection and signalling)
n
n
n
n
n
n
Overtemperature detection
Short-circuit on bus lines
VBAT power-on flag (first battery connection and cold start)
Pin TXEN and pin BGE clamping
Undervoltage detection on pins VBAT, VCC and VIO
Wake source indication
2.4 Protections
n Bus pins protected against 8 kV HBM ESD pulses
n Bus pins protected against transients in automotive environment (ISO 7637 class C
compliant)
n Bus pins short-circuit proof to battery voltage (14 V and 42 V) and ground
n Fail-safe mode in case of an undervoltage on pins VBAT, VCC or VIO
n Passive behavior of bus lines in the event that transceiver is not powered
3. Quick reference data
Table 1.
Quick reference data
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VBAT
supply voltage on pin VBAT
no time limit
−0.3
-
+60
V
operating range
6.5
-
60
V
VCC
supply voltage
no time limit
−0.3
-
+5.5
V
operating range
4.75
-
5.25
V
VBUF
supply voltage on pin VBUF
no time limit
−0.3
-
+5.5
V
operating range
4.75
-
5.25
V
no time limit
−0.3
-
+5.5
V
operating range
VIO
supply voltage on pin VIO
2.2
-
5.25
V
VTRXD0
voltage on pin TRXD0
−0.3
-
+5.5
V
VTRXD1
voltage on pin TRXD1
−0.3
-
+5.5
V
VBP
voltage on pin BP
−60
-
+60
V
VBM
voltage on pin BM
IBAT
supply current on pin VBAT
−60
-
+60
V
low power modes in
node configuration
-
-
50
µA
normal power modes
-
-
1
mA
TJA1080_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 12 July 2007
2 of 48
TJA1080
NXP Semiconductors
FlexRay transceiver
Table 1.
Quick reference data …continued
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ICC
supply current
low power modes
−1
0
+5
µA
Normal mode; VBGE =
0 V; VTXEN = VIO;
Receive-only mode;
Star-idle mode
-
-
15
mA
-
-
35
mA
-
-
15
mA
Normal mode; VBGE =
VIO; VTXEN = 0 V; VBUF
open
[1]
Normal mode;
VBGE = VIO; VTXEN = 0 V;
Rbus = ∞ Ω
supply current on pin VIO
IIO
Star-transmit mode
-
-
62
mA
Star-receive mode
-
-
42
mA
low power modes
−1
+1
+5
µA
Normal and
Receive-only mode;
VTXD = VIO
-
-
1000
µA
VOH(dif)
differential HIGH-level output voltage on pins BP and BM;
40 Ω < Rbus < 55 Ω;
VCC = VBUF = 5 V
600
800
1200
mV
VOL(dif)
differential LOW-level output voltage
on pins BP and BM;
40 Ω < Rbus < 55 Ω;
VCC = VBUF = 5 V
−1200
−800
−600
mV
VIH(dif)
differential HIGH-level input voltage
on pins BP and BM;
normal power modes;
−10 V < VBP < +15 V;
−10 V < VBM < +15 V
150
225
300
mV
VIL(dif)
differential LOW-level input voltage
on pins BP and BM;
normal power modes;
−10 V < VBP < +15 V;
−10 V < VBM < +15 V
−300
−225
−150
mV
Tvj
virtual junction temperature
−40
-
+150
°C
[2]
[1]
Current flows from VCC to VBUF. This means that the maximum sum current ICC + IBUF is 35 mA.
[2]
In accordance with IEC 60747-1. An alternative definition of virtual junction temperature Tvj is: Tvj = Tamb + TD x Rth(j-a), where Rth(j-a) is
a fixed value to be used for the calculation of Tvj. The rating for Tvj limits the allowable combinations of power dissipation (P) and
ambient temperature (Tamb).
4. Ordering information
Table 2.
Ordering information
Type number
TJA1080TS
Package
Name
Description
Version
SSOP20
plastic shrink small outline package; 20 leads; body with 5.3 mm
SOT339-1
TJA1080TS/N
TJA1080_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 12 July 2007
3 of 48
TJA1080
NXP Semiconductors
FlexRay transceiver
5. Block diagram
VIO
VCC
4
VBUF
19
VBAT
20
14
1
2
INH2
INH1
TJA1080
TRXD0
11
18
SIGNAL
ROUTER
TRXD1
TRANSMITTER
17
BP
BM
10
VIO
TXD
TXEN
BGE
STBN
EN
RXD
ERRN
RXEN
5
6
INPUT
VOLTAGE
ADAPTATION
8
9
3
7
13
12
OUTPUT
VOLTAGE
ADAPTATION
VBAT
WAKE
BUS
FAILURE
DETECTION
15
RXDINT
STATE
MACHINE
RXDINT
NORMAL
RECEIVER
OVERTEMPERATURE
DETECTION
WAKE-UP
DETECTION
OSCILLATOR
LOWPOWER
RECEIVER
UNDERVOLTAGE
DETECTION
16
001aae436
GND
Fig 1. Block diagram
TJA1080_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 12 July 2007
4 of 48
TJA1080
NXP Semiconductors
FlexRay transceiver
6. Pinning information
6.1 Pinning
INH2
1
20 VBUF
INH1
2
19 VCC
EN
3
18 BP
VIO
4
17 BM
TXD
5
TXEN
6
RXD
7
14 VBAT
BGE
8
13 ERRN
STBN
9
12 RXEN
TJA1080TS
TRXD1 10
16 GND
15 WAKE
11 TRXD0
001aae437
Fig 2. Pin configuration
6.2 Pin description
Table 3.
Pin description
Symbol Pin
Type
Description
INH2
1
O
inhibit 2 output for switching external voltage regulator
INH1
2
O
inhibit 1 output for switching external voltage regulator
EN
3
I
enable input; when HIGH enabled; internal pull-down
VIO
4
P
supply voltage for VIO voltage level adaptation
TXD
5
I
transmit data input; internal pull-down
TXEN
6
I
transmitter enable input; when HIGH transmitter disabled; internal
pull-up
RXD
7
O
receive data output
BGE
8
I
bus guardian enable input; when LOW transmitter disabled; internal
pull-down
STBN
9
I
standby input; when LOW low power mode; internal pull-down
TRXD1
10
I/O
data bus line 1 for inner star connection
TRXD0
11
I/O
data bus line 0 for inner star connection
RXEN
12
O
receive data enable output; when LOW bus activity detected
ERRN
13
O
error diagnoses output; when LOW error detected
VBAT
14
P
battery supply voltage
WAKE
15
I
local wake-up input; internal pull-up or pull-down (depends on
voltage at pin WAKE)
GND
16
P
ground
BM
17
I/O
bus line minus
BP
18
I/O
bus line plus
VCC
19
P
supply voltage (+5 V)
VBUF
20
P
buffer supply voltage
TJA1080_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 12 July 2007
5 of 48
TJA1080
NXP Semiconductors
FlexRay transceiver
7. Functional description
The block diagram of the total transceiver is illustrated in Figure 1.
7.1 Operating configurations
7.1.1 Node configuration
In node configuration the transceiver operates as a stand-alone transceiver.
The transceiver can be configured as node by connecting pins TRXD0 and TRXD1 to
ground during a power-on situation (PWON flag is set). The configuration will be latched
when the PWON flag is reset, see Section 7.7.4 “Power-on flag”.
The following operating modes are selectable:
•
•
•
•
•
Normal (normal power mode)
Receive-only (normal power mode)
Standby (low power mode)
Go-to-sleep (low power mode)
Sleep (low power mode)
7.1.2 Star configuration
In star configuration the transceiver operates as a branch of a FlexRay active star.
The transceiver can be configured as star by connecting pin TRXD0 or TRXD1 to VBUF
during a PWON situation (PWON flag is set). The configuration will be latched when the
PWON flag is reset, see Section 7.7.4 “Power-on flag”.
It is possible to redirect data from one branch to other branches via the inner bus. It is also
possible to send data to all branches via pin TXD, if pins TXEN and BGE have the correct
polarity.
The following operating modes are available:
•
•
•
•
•
•
Star-idle (normal power mode)
Star-transmit (normal power mode)
Star-receive (normal power mode)
Star-sleep (low power mode)
Star-standby (low power mode)
Star-locked (normal power mode)
In the star configuration all modes are autonomously controlled by the transceiver, except
in the case of a wake-up.
TJA1080_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 12 July 2007
6 of 48
TJA1080
NXP Semiconductors
FlexRay transceiver
7.1.3 Bus activity and idle detection
The following mechanisms for activity and idle detection are valid for node and star
configurations in normal power modes:
• If the absolute differential voltage on the bus lines is higher than Vi(dif)det(act) for
tdet(act)(bus), then activity is detected on the bus lines and pin RXEN is switched to LOW
which results in pin RXD being released:
– If, after bus activity detection, the differential voltage on the bus lines is higher than
VIH(dif), pin RXD will go HIGH
– If, after bus activity detection, the differential voltage on the bus lines is lower than
VIL(dif), pin RXD will go LOW
• If the absolute differential voltage on the bus lines is lower than Vi(dif)det(act) for
tdet(idle)(bus), then idle is detected on the bus lines and pin RXEN is switched to HIGH.
This results in pin RXD being blocked (pin RXD is switched to HIGH or stays HIGH)
Additionally, in star configuration, activity and idle can be detected (see Figure 5 for state
transitions due to activity/idle detection in star configuration):
• If pin TXEN is LOW for longer than tdet(act)(TXEN), activity is detected on pin TXEN
• If pin TXEN is HIGH for longer than tdet(idle)(TXEN), idle is detected on pin TXEN
• If pin TRXD0 or TRXD1 is LOW for longer than tdet(act)(TRXD), activity is detected on
pins TRXD0 and TRXD1
• If pin TRXD0 and TRXD1 is HIGH for longer than tdet(idle)(TRXD), idle is detected on
pins TRXD0 and TRXD1
7.2 Operating modes in node configuration
The TJA1080 provides two control pins STBN and EN in order to select one of the modes
of operation in node configuration. See Table 4 for a detailed description of the pin
signalling in node configuration, and Figure 3 for the timing diagram.
All modes are directly controlled via pins EN and STBN unless an undervoltage situation
is present.
If VIO and (VBUF or VBAT) are within their operating range, pin ERRN indicates error flag.
Table 4.
Pin signalling in node configuration
Mode
STBN EN
ERRN[1]
LOW
RXEN
HIGH
RXD
LOW
HIGH
LOW
HIGH
HIGH error flag error flag
reset
LOW set
bus
activity
bus
idle
bus
DATA_0
bus
enabled
DATA_1 disabled
or idle
wake flag wake
set[2]
flag
reset
wake flag
set[3]
wake
flag
reset
Normal
HIGH
Receive-only
HIGH
Go-to-sleep
LOW
Standby
LOW
HIGH error flag error flag
[2]
reset
LOW set
Sleep
LOW
X
[1]
Pin ERRN provides a serial interface for retrieving diagnostic information.
[2]
Valid if VIO and VBUF or VBAT are present.
[3]
Valid if VIO and VBUF are present.
[4]
If wake flag is not set.
TJA1080_2
Product data sheet
Transmitter INH1 INH2
HIGH HIGH
float[4]
float
float
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 12 July 2007
7 of 48
TJA1080
NXP Semiconductors
FlexRay transceiver
TXD
BGE
TXEN
BP
BM
RXEN
RXD
001aae439
Fig 3. Timing diagram in Normal mode node configuration
The state diagram in node configuration is illustrated in Figure 4.
TJA1080_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 12 July 2007
8 of 48
TJA1080
NXP Semiconductors
FlexRay transceiver
1
RECEIVE ONLY
NORMAL
STBN = HIGH
EN = LOW
STBN = HIGH
EN = HIGH
4
3, 30
15, 25, 42, 43
8, 17, 39
5
6, 33
31, 32
10, 20
11, 21
2
14, 24, 40, 41
7, 16, 38
28, 29
12, 22
19
STANDBY(1)
GO-TO-SLEEP
STBN = LOW
EN = LOW
STBN = LOW
EN = HIGH
23
9, 18
36, 37
13, 34, 35
26, 44
27, 45
SLEEP
STBN = LOW
EN = X
001aae438
(1) At the first battery connection the transceiver will enter the Standby mode.
Fig 4. State diagram in node configuration
The state transitions are represented with numbers, which correspond with the numbers
in the last column of Table 5 to Table 8.
TJA1080_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 12 July 2007
9 of 48
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NXP Semiconductors
TJA1080_2
Product data sheet
Table 5.
State transitions forced by EN and STBN (node configuration)
→ indicates the action that initiates a transaction; →1 and →2 are the consequences of a transaction.
Transition
from mode
Direction to
mode
Normal
Go-to-sleep
Rev. 02 — 12 July 2007
Sleep
Pin
Flag
Note
STBN
EN
UVVIO
UVVBAT
UVVCC
PWON
Wake
Receive-only 1
H
→L
cleared
cleared
cleared
cleared
cleared
Go-to-sleep
2
→L
H
cleared
cleared
cleared
cleared
cleared
Standby
3
→L
→L
cleared
cleared
cleared
cleared
cleared
4
H
→H
cleared
cleared
cleared
X
X
Go-to-sleep
5
→L
→H
cleared
cleared
cleared
X
X
Standby
6
→L
L
cleared
cleared
cleared
X
X
Normal
7
→H
→H
cleared
cleared
2 → cleared
X
1 → cleared
[2][3]
Receive-only 8
→H
L
cleared
cleared
2 → cleared
X
1 → set
[2][3]
Go-to-sleep
9
L
→H
cleared
cleared
X
X
X
Normal
10
→H
H
cleared
cleared
cleared
X
1 → cleared
[2][4]
Receive-only 11
→H
→L
cleared
cleared
cleared
X
1 → set
[2][4]
Standby
12
L
→L
cleared
cleared
X
X
X
[4]
Sleep
13
L
H
cleared
cleared
X
X
cleared
[5]
Normal
14
→H
H
2 → cleared
2 → cleared
2 → cleared
X
1 → cleared
[2][3]
Receive-only 15
→H
L
2 → cleared
2 → cleared
2 → cleared
X
1 → set
[2][3]
Receive-only Normal
Standby
Transition
number
[1]
STBN must be set to LOW 60 µs after EN.
[2]
Positive edge on pin STBN sets the wake flag. In the case of a transition to Normal mode the wake flag is immediately cleared.
[3]
Setting the wake flag clears the UVVIO, UVVBAT and UVVCC flag.
[4]
Hold time of go-to-sleep is less than the minimum hold time.
[5]
Hold time of go-to-sleep becomes greater than the minimum hold time.
[1]
TJA1080
FlexRay transceiver
10 of 48
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NXP Semiconductors
TJA1080_2
Product data sheet
Table 6.
State transitions forced by a wake-up (node configuration)
→ indicates the action that initiates a transaction; →1 and →2 are the consequences of a transaction.
Transition
from mode
Direction to
mode
Transition
number
Pin
STBN
EN
Wake
UVVIO
UVVBAT
UVVCC
PWON
Standby
Normal
16
H
H
→ set
cleared
cleared
1 → cleared
X
[1]
Receive-only
17
H
L
→ set
cleared
cleared
1 → cleared
X
[1]
Go-to-sleep
18
L
H
→ set
cleared
cleared
1 → cleared
X
[1]
Standby
19
L
L
→ set
cleared
cleared
1 → cleared
X
[1]
Normal
20
H
H
→ set
cleared
cleared
1 → cleared
X
[1]
Receive-only
21
H
L
→ set
cleared
cleared
1 → cleared
X
[1]
Standby
22
L
L
→ set
cleared
cleared
1 → cleared
X
[1]
Go-to-sleep
23
L
H
→ set
cleared
cleared
1 → cleared
X
[1]
Go-to-sleep
Sleep
Flag
Note
Rev. 02 — 12 July 2007
Normal
24
H
H
→ set
1 → cleared
1 → cleared
1 → cleared
X
[1][2]
Receive-only
25
H
L
→ set
1 → cleared
1 → cleared
1 → cleared
X
[1][2]
Standby
26
L
L
→ set
1 → cleared
1 → cleared
1 → cleared
X
[1]
Go-to-sleep
27
L
H
→ set
1 → cleared
1 → cleared
1 → cleared
X
[1][2]
[1]
Setting the wake flag clears the UVVIO, UVVBAT and UVVCC flag.
[2]
Transition via Standby mode.
TJA1080
FlexRay transceiver
11 of 48
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NXP Semiconductors
TJA1080_2
Product data sheet
Table 7.
State transitions forced by an undervoltage condition (node configuration)
→ indicates the action that initiates a transaction; →1 and →2 are the consequences of a transaction.
Transition from
mode
Direction to
mode
Transition
number
Flag
UVVIO
UVVBAT
UVVCC
PWON
Wake
Normal
Sleep
28
→ set
cleared
cleared
cleared
cleared
[1]
Sleep
29
cleared
→ set
cleared
cleared
cleared
[1]
Standby
30
cleared
cleared
→ set
cleared
cleared
[1]
Sleep
31
→ set
cleared
cleared
X
1 → cleared
[1]
Sleep
32
cleared
→ set
cleared
X
1 → cleared
[1]
Standby
33
cleared
cleared
→ set
X
1 → cleared
[1]
Sleep
34
→ set
cleared
cleared
X
1 → cleared
[1]
Sleep
35
cleared
→ set
cleared
X
1 → cleared
[1]
Sleep
36
→ set
cleared
X
X
1 → cleared
[1][2]
Sleep
37
cleared
→ set
X
X
1 → cleared
[1][3]
Receive-only
Go-to-sleep
Standby
Rev. 02 — 12 July 2007
[1]
UVVIO, UVVBAT or UVVCC detected clears the wake flag.
[2]
UVVIO overrules UVVCC.
[3]
UVVBAT overrules UVVCC.
Note
TJA1080
FlexRay transceiver
12 of 48
© NXP B.V. 2007. All rights reserved.
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
NXP Semiconductors
TJA1080_2
Product data sheet
Table 8.
State transitions forced by an undervoltage recovery (node configuration)
→ indicates the action that initiates a transaction; →1 and →2 are the consequences of a transaction.
Transition
from mode
Direction to
mode
Transition
number
Pin
STBN
EN
UVVIO
UVVBAT
UVVCC
PWON
Wake
Standby
Normal
38
H
H
cleared
cleared
→ cleared
X
X
[1]
Receive-only 39
H
L
cleared
cleared
→ cleared
X
X
[1]
Normal
40
H
H
cleared
→ cleared
cleared
X
1 → cleared
Normal
41
H
H
→ cleared
cleared
cleared
X
X
Sleep
Flag
Note
[2][3]
[4]
Receive-only 42
H
L
cleared
→ cleared
cleared
X
1 → set
Receive-only 43
H
L
→ cleared
cleared
cleared
X
X
Standby
44
L
L
cleared
→ cleared
cleared
X
1 → set
Sleep
45
L
X
→ cleared
cleared
cleared
X
cleared
[4]
[2][3]
[4]
[2][3]
Go-to-sleep
46
L
H
cleared
→ cleared
cleared
X
1 → set
[2][3]
Sleep
47
L
X
→ cleared
cleared
cleared
X
cleared
[4]
Rev. 02 — 12 July 2007
[1]
Recovery of UVVCC flag.
[2]
Recovery of UVVBAT flag.
[3]
Clearing the UVVBAT flag sets the wake flag. In the case of a transition to Normal mode the wake flag is immediately cleared.
[4]
Recovery of UVVIO flag.
TJA1080
FlexRay transceiver
13 of 48
© NXP B.V. 2007. All rights reserved.
TJA1080
NXP Semiconductors
FlexRay transceiver
7.2.1 Normal mode
In Normal mode the transceiver is able to transmit and receive data via the bus lines BP
and BM. The output of the normal receiver is directly connected to pin RXD.
The transmitter behavior in Normal mode of operation, with no time-out present on pins
TXEN and BGE and the temperature flag not set is given in Table 9.
In this mode pins INH1 and INH2 are set HIGH.
Table 9.
Transmitter function table
BGE
TXEN
TXD
Transmitter
L
X
X
transmitter is disabled
X
H
X
transmitter is disabled
H
L
H
transmitter is enabled; the bus lines are actively driven; BP is driven
HIGH and BM is driven LOW
H
L
L
transmitter is enabled; the bus lines are actively driven; BP is driven
LOW and BM is driven HIGH
7.2.2 Receive-only mode
In Receive-only mode the transceiver can only receive data. The transmitter is disabled,
regardless of the voltages on pins BGE and TXEN.
In this mode pins INH1 and INH2 are set HIGH.
7.2.3 Standby mode
In Standby mode the transceiver has entered a low power mode which means very low
current consumption. In the Standby mode the device is not able to transmit or receive
data and the low power receiver is activated to monitor for bus wake-up patterns.
Standby mode can be entered if the correct polarity is applied to pins EN and STBN (see
Figure 4 and Table 5) or an undervoltage is present on pin VCC; see Figure 4.
In this mode the transceiver can be switched to any other mode if no undervoltage is
present on pins VIO and VBAT.
Pin INH1 is set to HIGH. If the wake flag is set, pin INH2 is set to HIGH and pins RXEN
and RXD are set to LOW, otherwise pin INH2 is floating and pins RXEN and RXD are set
to HIGH; see Section 7.5.
7.2.4 Go-to-sleep mode
In this mode the transceiver behaves as in Standby mode. If this mode is selected for a
longer time than the go-to-sleep hold time parameter (minimum hold time) and the wake
flag has been previously cleared, the transceiver will enter Sleep mode, regardless of the
voltage on pin EN.
TJA1080_2
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TJA1080
NXP Semiconductors
FlexRay transceiver
7.2.5 Sleep mode
In Sleep mode the transceiver has entered a low power mode. The only difference with
Standby mode is that pin INH1 is also set floating. Sleep mode is also entered if the UVVIO
or UVVBAT flag is set.
In this mode the transceiver can be switched to any other mode if no undervoltage is
present on pins VIO, VCC and VBAT. In case of an undervoltage on pin VCC or VBAT while
VIO is present, the wake flag is set by a positive edge on pin STBN.
The undervoltage flags will be reset by setting the wake flag, and therefore the transceiver
will enter the mode indicated on pins EN and STBN if VIO is present.
A detailed description of the wake-up mechanism is given in Section 7.5.
7.3 Operating modes in star configuration
In star configuration mode control via pins EN and STBN is not possible. The transceiver
autonomously controls the operating modes except in the case of wake-up.
The timing diagram of a transceiver configured in star configuration is illustrated in
Figure 6. The state diagram in star configuration is illustrated in Figure 5. A detailed
description of the pin signalling in star configuration is given in Table 10.
If VIO and (VBUF or VBAT) are within their operating range, pin ERRN will indicate the error
flag.
Table 10.
Pin signalling in star configuration
Mode
TRXD0 /
TRXD1
ERRN[1]
Star-transmit
output[2]
error flag error flag bus
set
reset
activity
input[3]
Star-receive
output
Star-idle
input
Star-locked
input
Star-standby
input
Star-sleep
input
LOW
RXEN
HIGH
LOW
RXD
HIGH
LOW
HIGH
bus idle
bus
DATA_0
bus
DATA_1
or idle
error flag error flag wake flag wake flag wake flag wake flag
reset
set[4]
reset
set[5]
reset
set[4]
[1]
Pin ERRN provides a serial interface for retrieving diagnostic information.
[2]
TRXD lines switched as output if TXEN activity is the initiator for Star-transmit mode.
[3]
TRXD lines are switched as input if TRXD activity is the initiator for Star-transmit mode.
[4]
Valid if VIO and (VBUF or VBAT) are present.
[5]
Valid if VIO and VBUF are present.
Transmitter INH1
INH2
enabled
HIGH
HIGH
float
float
disabled
Pin BGE must be HIGH in order to enable the transmitter via pin TXEN. If pin BGE is
LOW, it is not possible to activate the transmitter via pin TXEN. If pin TXEN is not used (no
controller connected to the transceiver), it has to be connected to pin GND in order to
prevent TXEN activity detection.
In all normal modes pin RXD is connected to the output of the normal mode receiver and
therefore represents the data on the bus lines.
TJA1080_2
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FlexRay transceiver
STAR LOCKED
INH1 = HIGH
INH2 = HIGH
TXEN activity detected for
longer than tto(tx-locked)
bus activity detected for
longer than tto(rx-locked)
idle detected on
the bus lines
and TXEN for longer
than tto(locked-idle)
STAR TRANSMIT
idle detected on
TRXD0, TRXD1,
TXEN and the
bus lines
idle detected on
TRXD0, TRXD1,
TXEN and the
bus lines
STAR IDLE
INH1 = HIGH
INH2 = HIGH
INH1 = HIGH
INH2 = HIGH
INH1 = HIGH
INH2 = HIGH
TRXD0, TRXD1,
TXEN activity detected
bus activity
detected
wake
flag 1
time in star
locked longer
than tto(locked-sleep)
STAR RECEIVE
wake flag 1 or
UVVCC signal 0
no acivity on TRXD0,
TRXD1, TXEN and the
bus lines for longer
than tto(idle-sleep)
STAR SLEEP
STAR STANDBY(1)
INH1 = floating
INH2 = floating
INH1 = HIGH
INH2 = HIGH
from any mode if UVVCC
flag is set regardless PWON flag
from star idle, star
transmit or star receive if
wake flag set and under
voltage present on VCC
for longer than
t > tto(uv)(VCC)
001aae441
(1) At the first battery connection the transceiver will enter the Star-standby mode.
Fig 5. State diagram in star configuration
TJA1080_2
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16 of 48
TJA1080
NXP Semiconductors
FlexRay transceiver
star transmit
star idle
star receive
star idle
star transmit
star idle
TRXD0
TRXD1
TXEN
TXD
TRXDOUT
BP
BM
RXEN
RXD
001aae440
TRXDOUT is a virtual signal that indicates the state of the TRXD lines. TRXDOUT HIGH means TRXD lines switched as
output. TRXDOUT LOW means TRXD lines switched as input.
Fig 6. Timing diagram in star configuration
7.3.1 Star-idle mode
This mode is entered if one of the following events occurs:
• From Star-receive mode and Star-transmit mode if idle is detected on the bus lines, on
pin TXEN and on pins TRXD0 and TRXD1.
• If the transceiver is in Star-locked mode and idle is detected on the bus lines and pin
TXEN for longer than tto(locked-idle).
• If the transceiver is in Star-standby mode and the wake flag is set or no undervoltage
is present.
• If the transceiver is in Star-sleep mode and the wake flag is set, the transceiver enters
Star-idle mode in order to obtain a stable starting point (no glitches on the bus lines
etc.).
In Star-idle mode the transceiver monitors pins TXEN, TRXD0 and TRXD1 and the bus
lines for activity. In this mode the transmitter is disabled.
TJA1080_2
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TJA1080
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FlexRay transceiver
7.3.2 Star-transmit mode
This mode is entered if one of the following events occur:
• If the transceiver is in Star-idle mode and activity is detected on pin TXEN.
• If the transceiver is in Star-idle mode and activity is detected on pins TRXD0 and
TRXD1.
In Star-transmit mode the transmitter is enabled and the transceiver can transmit data on
the bus lines and on the TRXD lines. It transmits the data received on pins TXD or TRXD0
and TRXD1, depending on where activity is detected:
• If activity is detected on the TRXD lines, the transceiver transmits data from pins
TRXD0 and TRXD1 to the bus.
• If activity is detected on the TXEN, the transceiver transmits data from pin TXD to the
bus and to the TRXD lines.
7.3.3 Star-receive mode
This mode is entered if the transceiver is in Star-idle mode and activity has been detected
on the bus lines.
In Star-receive mode the transceiver transmits data received on the bus via the TRXD0
and TRXD1 lines to other transceivers connected to the TRXD lines. The transmitter is
always disabled. RXD, which represents the data on the bus lines, is output at TRXD0 and
TRXD1.
7.3.4 Star-standby mode
This mode is entered if one of the following events occur:
• From Star-idle, Star-transmit or Star-receive modes if the wake flag is set and an
undervoltage on pin VCC is present for longer than tto(uv)(VCC).
• If the PWON flag is set.
In Star-standby mode the transceiver has entered a low power mode. In this mode the
current consumption is as low as possible to prevent discharging the capacitor at pin
VBUF.
If pins VIO and VBUF are within their operating range, pins RXD and RXEN will indicate the
wake flag.
TJA1080_2
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Rev. 02 — 12 July 2007
18 of 48
TJA1080
NXP Semiconductors
FlexRay transceiver
7.3.5 Star-sleep mode
This mode is entered if one of the following events occur:
• From any mode if an undervoltage on pin VCC is present for longer than tdet(uv)(VCC).
• If the transceiver is in Star-idle mode and no activity is detected on the bus lines and
pins TXEN, TRXD0 and TRXD1 for longer than tto(idle-sleep).
• If Star-locked mode is active for longer than tto(locked-sleep).
In Star-sleep mode the transceiver has entered a low power mode. In this mode the
current consumption is as low as possible to prevent the car battery from discharging. The
inhibit switches are switched off.
In this mode the wake flag wakes the transceiver. A detailed description of the wake-up
mechanism is given in Section 7.5.
If pins VIO and VBUF are within their operating range, pins RXD and RXEN will indicate the
wake flag.
7.3.6 Star-locked mode
This mode is entered if one of the following events occur:
• If the transceiver is in Star-transmit mode and activity on pin TXEN is detected for
longer than tto(tx-locked).
• If the transceiver is in Star-receive mode and activity is detected on the bus lines for
longer than tto(rx-locked).
This mode is a fail-silent mode and in this mode the transmitter is disabled.
7.4 Start-up
At power-up VBAT should be supplied first. When VBAT reaches 6.5 V, VCC and VIO may be
switched on with a delay of at least 60 µs with respect to VBAT.
7.4.1 Node configuration
Node configuration can be selected by applying a voltage lower than 0.3VBUF to pins
TRXD0 and TRXD1 during power-on. Node configuration is latched by resetting the
PWON flag while the voltage on pins TRXD0 and TRXD1 is lower than 0.3VBUF; see
Section 7.7.4 for (re)setting the PWON flag.
7.4.2 Star configuration
Star configuration can be selected by applying a voltage higher than 0.7VBUF to pins
TRXD0 or TRXD1 during power-on. Star configuration is latched by resetting the PWON
flag while one of the voltages on pins TRXD0 or TRXD1 is higher than 0.7VBUF. See
Section 7.7.4 for (re)setting the PWON flag. In this case the transceiver goes from
Star-standby mode to Star-idle mode.
TJA1080_2
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19 of 48
TJA1080
NXP Semiconductors
FlexRay transceiver
7.5 Wake-up mechanism
7.5.1 Node configuration
In Sleep mode (pins INH1 and INH2 are switched off), the transceiver will enter Standby
mode or Go-to-sleep mode (depending on the value at pin EN), if the wake flag is set.
Consequently, pins INH1 and INH2 are switched on.
If no undervoltage is present on pins VIO and VBAT, the transceiver switches immediately
to the mode indicated on pins EN and STBN.
In Standby, Go-to-sleep and Sleep mode pins RXD and RXEN are driven LOW if the wake
flag is set.
7.5.2 Star configuration
In Star-sleep mode (pins INH1 and INH2 are switched off), the transceiver will enter
Star-idle mode (pins INH1 and INH2 are switched on) if the wake flag is set. After entering
Star-idle mode the transceiver monitors for activity to choose the appropriate mode
transition (see Figure 5).
7.5.3 Bus wake-up
Bus wake-up is detected if two consecutive DATA_0 of at least tdet(wake)DATA_0 separated by
an idle or DATA_1 of at least tdet(wake)idle, followed by an idle or DATA_1 of at least
tdet(wake)idle are present on the bus lines within tdet(wake)tot.
tdet(wake)tot
0V
Vdif
−425 mV
tdet(wake)Data_0
tdet(wake)idle
tdet(wake)Data_0
tdet(wake)idle
001aae442
Fig 7. Bus wake-up timing
TJA1080_2
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TJA1080
NXP Semiconductors
FlexRay transceiver
7.5.4 Local wake-up via pin WAKE
If the voltage on pin WAKE is lower than Vth(det)(WAKE) for longer than twake(WAKE) (falling
edge on pin WAKE) a local wake-up event on pin WAKE is detected. At the same time, the
biasing of this pin is switched to pull-down.
If the voltage on pin WAKE is higher than Vth(det)(WAKE) for longer than twake(WAKE), the
biasing of this pin is switched to pull-up, and no local wake-up will be detected.
pull-up
twake(WAKE)
pull-down
pull-up
twake(WAKE)
VBAT
WAKE
0V
RXD and
RXEN
VBAT
INH1 and
INH2
0V
001aae443
Sleep mode: VIO and (VBAT or VCC) still provided.
Fig 8. Local wake-up timing via pin WAKE
7.6 Fail silent behavior
In order to be fail silent, undervoltage detection and a reset mechanism for the digital state
machine is implemented.
If an undervoltage is detected on pins VCC, VIO and/or VBAT, the transceiver will enter a
low power mode. This ensures a passive and defined behavior of the transmitter and
receiver in case of an undervoltage detection.
In the region between the minimum operating voltage and the undervoltage detection
threshold, the principle function of the transmitter and receiver is maintained. However, in
this region parameters (e.g. thresholds and delays of the transmitter and receiver) may
deviate from the range specified for the operating range.
The digital state machine is supplied out of VCC, VIO or VBAT, dependent on which voltage
is available. Therefore, the digital state machine remains properly supplied as long as one
supply voltage (VCC, VIO or VBAT) is available.
If the voltage on all pins VCC, VIO and VBAT breaks down, a reset signal will be given to the
digital state machine as soon as the internal supply voltage for the digital state machine is
not sufficient for proper operation of the state machine. This ensures a passive and
defined behavior of the digital state machine in case of an overall supply voltage
breakdown.
TJA1080_2
Product data sheet
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Rev. 02 — 12 July 2007
21 of 48
TJA1080
NXP Semiconductors
FlexRay transceiver
7.6.1 VBAT undervoltage
• Node configuration: If the UVVBAT flag is set the transceiver will enter Sleep mode
(pins INH1 and INH2 are switched off) regardless of the voltage present on pins EN
and STBN. If the undervoltage recovers the wake flag will be set and the transceiver
will enter the mode determined by the voltages on pins EN and STBN.
• Star configuration: The TJA1080 in star configuration is able to transmit and receive
data as long as VCC and VIO are within their operating range, regardless of the
undervoltage on VBAT.
7.6.2 VCC undervoltage
• Node configuration: If the UVVCC flag is set the transceiver will enter the Standby
mode (pin INH2 is switched off) regardless of the voltage present on pins EN and
STBN. If the undervoltage recovers or the wake flag is set mode switching via pins EN
and STBN is possible.
• Star configuration: If the UVVCC flag is set the transceiver will enter the Star-sleep
mode.
7.6.3 VIO undervoltage
• Node configuration: If the voltage on pin VIO is lower than Vuvd(VIO) (even if the UVVIO
flag is reset) pins EN, STBN, TXD and BGE are set LOW (internally) and pin TXEN is
set HIGH (internally). If the UVVIO flag is set the transceiver will enter Sleep mode
(pins INH1 and INH2 are switched off). If the undervoltage recovers or the wake flag is
set, mode switching via pins EN and STBN is possible.
• Star configuration: If an undervoltage is present on pin VIO (even if the UVVIO flag is
reset) pins EN, STBN, TXD and BGE are set LOW (internally) and pin TXEN is set
HIGH (internally). If the VIO undervoltage flag is set, pin INH1 is switched off. If an
undervoltage is present on pin VIO and VCC is within the operating range, the TJA1080
will forward the received data on TRXD or bus lines to all other branches.
7.7 Flags
7.7.1 Local wake-up source flag
The local wake-up source flag can only be set in a low power mode. When a wake-up
event on pin WAKE is detected (see Section 7.5.4) it sets the local wake-up source flag.
The local wake-up source flag is reset by entering a low power mode.
7.7.2 Remote wake-up source flag
The remote wake-up source flag can only be set in a low power mode. When a bus
wake-up event is detected on the bus lines (see Section 7.5.3) it sets the remote wake-up
source flag. The remote wake-up source flag is reset by entering a low power mode.
TJA1080_2
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TJA1080
NXP Semiconductors
FlexRay transceiver
7.7.3 Wake flag
The wake flag is set if one of the following events occurs:
•
•
•
•
The local or remote wake-up source flag is set (edge sensitive)
A positive edge is detected on pin STBN if VIO is present
Recovery of the UVVBAT flag (only in node configuration)
By recognizing activity on pins TRXD0 and TRXD1 (only in star configuration)
In node configuration the wake flag is reset by entering Normal mode, a low power mode
or setting one of the undervoltage flags. In star configuration the wake flag is reset by
entering a low power mode or by recovery of the UVVCC signal (without trec(uv)(VCC)).
7.7.4 Power-on flag
The PWON flag is set if the internal supply voltage for the digital part becomes higher than
the lowest value it needs to operate. In node configuration, entering Normal mode resets
the PWON flag. In star configuration the PWON flag is reset when the UVVCC signal goes
LOW (no undervoltage detected).
7.7.5 Node configuration flag
Configuration flag set means node configuration.
7.7.6 Temperature medium flag
The temperature medium flag is set if the junction temperature exceeds Tj(warn)(medium) in a
normal power mode. The temperature medium flag is reset when the junction temperature
becomes lower than Tj(warn)(medium) in a normal power mode and after a read of the status
register in a low power mode. No action will be taken if this flag is set.
7.7.7 Temperature high flag
The temperature high flag is set if the junction temperature exceeds Tj(dis)(high) in a normal
power mode.
In node configuration the temperature high flag is reset if a negative edge is applied to pin
TXEN while the junction temperature is lower than Tj(dis)(high) in a normal power mode. In
star configuration the temperature high flag is reset by any activity detection (edge) while
the junction temperature is lower than Tj(dis)(high) in a normal power mode.
If the temperature high flag is set the transmitter is disabled and pins TRXD0 and TRXD1
are switched off.
7.7.8 TXEN_BGE clamped flag
The TXEN_BGE clamped flag is set if pin TXEN is LOW and pin BGE is HIGH for longer
than tdetCL(TXEN_BGE). The TXEN_BGE clamped flag is reset if pin TXEN is HIGH or pin
BGE is LOW. If the TXEN_BGE flag is set, the transmitter is disabled.
TJA1080_2
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23 of 48
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FlexRay transceiver
7.7.9 Bus error flag
The bus error flag is set if pin TXEN is LOW and pin BGE is HIGH and the data received
from the bus lines (pins BP and BM) is different to that received on pin TXD. Additionally in
star configuration the bus error flag is also set if the data received on the bus lines is
different to that received on pins TRXD0 and TRXD1. The TJA1080 also expects that a
data frame begins with a bit value other than the last bit of the previous data frame.
This is the case for a valid data frame which begins with the DATA_0 period of the
Transmission Start Sequence (TSS) and ends with the DATA_1 bit of the Frame End
Sequence (FES). Any violation of this frame format will be detected by the TJA1080.
Consequently, when transmitting a wake-up pattern, a bus error will be signalled. This
error indication should be ignored and the status register should be cleared by reading the
vector.
No action will be taken if the bus error flag is set.
7.7.10 UVVBAT flag
The UVVBAT flag is set if the voltage on pin VBAT is lower than Vuvd(VBAT). The UVVBAT flag
is reset if the voltage is higher than Vuvd(VBAT) or by setting the wake flag; see
Section 7.6.1.
7.7.11 UVVCC flag
The UVVCC flag is set if the voltage on pin VCC is lower than Vuvd(VCC) for longer than
tdet(uv)(VCC). The flag is reset if the voltage on pin VCC is higher than Vuvd(VCC) for longer
than trec(uv)(VCC) or the wake flag is set; see Section 7.6.2.
7.7.12 UVVIO flag
The UVVIO flag is set if the voltage on pin VIO is lower than Vuvd(VIO) for longer than
tdet(uv)(VIO). The flag is reset if the voltage on pin VIO is higher than Vuvd(VIO) or the wake
flag is set; see Section 7.6.3.
7.7.13 Error flag
The error flag is set if one of the status bits S4 to S12 is set. The error flag is reset if none
of the S4 to S12 status bits are set; see Table 11.
7.8 TRXD collision
A TRXD collision is detected when both TRXD lines are LOW in star configuration.
7.9 Status register
The status register can be read out on pin ERRN by using pin EN as clock; the status bits
are given in Table 11. The timing diagram is illustrated in Figure 9.
The status register is accessible if:
• UVVIO flag is not set and the voltage on pin VIO is between 4.75 V and 5.25 V
• UVVCC flag is not set and the voltage on pin VIO is between 2.2 V and 4.75 V
Pin ERRN is LOW if the corresponding status bit is set.
TJA1080_2
Product data sheet
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Rev. 02 — 12 July 2007
24 of 48
TJA1080
NXP Semiconductors
FlexRay transceiver
Table 11.
Status bits
Bit number Status bit
Description
S0
LOCAL WAKEUP
local wake-up source flag is redirected to this bit
S1
REMOTE WAKEUP
remote wake-up source flag is redirected to this bit
S2
NODE CONFIG
node configuration flag is redirected to this bit
S3
PWON
status bit set means PWON flag has been set previously
S4
BUS ERROR
status bit set means bus error flag has been set previously
S5
TEMP HIGH
status bit set means temperature high flag has been set previously
S6
TEMP MEDIUM
status bit set means temperature medium flag has been set previously
S7
TXEN_BGE CLAMPED
status bit set means TXEN_BGE clamped flag has been set previously
S8
UVVBAT
status bit set means UVVBAT flag has been set previously
S9
UVVCC
status bit set means UVVCC flag has been set previously
S10
UVVIO
status bit set means UVVIO flag has been set previously
S11
STAR LOCKED
status bit is set if Star-locked mode has been entered previously
S12
TRXD COLLISION
status bit is set if a TRXD collision has been detected previously
receive
only
normal
standby
receive
only
normal
0.7VIO
STBN
0.3VIO
tdet(EN)
tdet(EN)
td(stb)
td(stb)
0.7VIO
EN
0.3VIO
TEN
ERRN
td(EN-ERRN)
0.7VIO
0.3VIO
S0
S1
S2
001aae444
Fig 9. Timing diagram for status bits
TJA1080_2
Product data sheet
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Rev. 02 — 12 July 2007
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TJA1080
NXP Semiconductors
FlexRay transceiver
8. Limiting values
Table 12. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to GND.
Symbol
Parameter
Conditions
Min
Max
Unit
VBAT
supply voltage on pin VBAT
no time limit
−0.3
+60
V
operating range
6.5
60
V
VCC
supply voltage
no time limit
−0.3
+5.5
V
operating range
4.75
5.25
V
no time limit
−0.3
+5.5
V
VBUF
supply voltage on pin VBUF
VIO
supply voltage on pin VIO
operating range
4.75
5.25
V
no time limit
−0.3
+5.5
V
operating range
2.2
5.25
V
VINH1
voltage on pin INH1
−0.3
VBAT + 0.3
V
VINH2
voltage on pin INH2
−0.3
VBAT + 0.3
V
VWAKE
voltage on pin WAKE
−0.3
VBAT + 0.3
V
Io(WAKE)
output current on pin WAKE
pin GND not connected
−15
-
mA
VBGE
voltage on pin BGE
no time limit
−0.3
VIO + 0.3
V
VTXEN
voltage on pin TXEN
no time limit
−0.3
VIO + 0.3
V
VTXD
voltage on pin TXD
no time limit
−0.3
VIO + 0.3
V
VERRN
voltage on pin ERRN
no time limit
−0.3
VIO + 0.3
V
VRXD
voltage on pin RXD
no time limit
−0.3
VIO + 0.3
V
VRXEN
voltage on pin RXEN
no time limit
−0.3
VIO + 0.3
V
VEN
voltage on pin EN
no time limit
−0.3
+5.5
V
VSTBN
voltage on pin STBN
no time limit
−0.3
+5.5
V
VTRXD0
voltage on pin TRXD0
no time limit
−0.3
+5.5
V
VTRXD1
voltage on pin TRXD1
no time limit
−0.3
+5.5
V
VBP
voltage on pin BP
no time limit
−60
+60
V
VBM
voltage on pin BM
no time limit
transient voltage
Vtrt
−60
+60
V
on pins BP and BM
[1]
−200
+200
V
on pin VBAT
[2]
−200
+200
V
on pin VBAT
[3]
6.5
60
V
on pin VBAT
[4]
-
60
V
−55
+150
°C
[5]
−40
+150
°C
HBM on pins BP and BM to ground
[6]
−8.0
+8.0
kV
HBM at any other pin
[7]
−4.0
+4.0
kV
MM on all pins
[8]
−200
+200
V
CDM on all pins
[9]
−1000
+1000
V
storage temperature
Tstg
Tvj
virtual junction temperature
VESD
electrostatic discharge voltage
[1]
According to ISO 7637, part 3 test pulses a and b; Class C; see Figure 13; RL = 45 Ω; CL = 100 pF.
[2]
According to ISO 7637, part 2 test pulses 1, 2, 3a and 3b; Class C; see Figure 13; RL = 45 Ω; CL = 100 pF.
[3]
According to ISO 7637, part 2 test pulse 4; Class C; see Figure 13; RL = 45 Ω; CL = 100 pF.
[4]
According to ISO 7637, part 2 test pulse 5b; Class C; see Figure 13; RL = 45 Ω; CL = 100 pF; VBAT = 24 V.
TJA1080_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 12 July 2007
26 of 48
TJA1080
NXP Semiconductors
FlexRay transceiver
[5]
In accordance with IEC 60747-1. An alternative definition of virtual junction temperature Tvj is: Tvj = Tamb + TD x Rth(j-a), where Rth(j-a) is
a fixed value to be used for the calculation of Tvj. The rating for Tvj limits the allowable combinations of power dissipation (P) and
ambient temperature (Tamb).
[6]
HBM: C = 100 pF; R = 1.5 kΩ.
[7]
HBM: C = 100 pF; R = 1.5 kΩ.
[8]
MM: C = 200 pF; L = 0.75 µH; R = 10 Ω.
[9]
CDM: C = 330 pF; R = 150 Ω.
9. Thermal characteristics
Table 13.
Thermal characteristics
Symbol
Parameter
Conditions
Typ
Unit
Rth(j-a)
thermal resistance from junction to ambient
in free air
126
K/W
Rth(j-s)
thermal resistance from junction to substrate
in free air
-
K/W
10. Static characteristics
Table 14. Static characteristics
All parameters are guaranteed for VBAT = 6.5 V to 60 V; VCC = 4.75 V to 5.25 V; VBUF = 4.75 V to 5.25 V; VIO = 2.2 V to 5.25 V;
Tvj = −40 °C to + 150 °C; Rbus = 45 Ω; RTRXD = 200 Ω unless otherwise specified. All voltages are defined with respect to
ground; positive currents flow into the IC.[1][2]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
-
-
50
µA
Star-sleep mode
-
-
50
µA
Star-standby mode
-
-
150
µA
normal power modes
-
-
1
mA
2.75
-
4,5
V
low power modes
−1
0
+5
µA
Normal mode; VBGE = 0 V;
VTXEN = VIO; Receive-only
mode; Star-idle mode
-
-
15
mA
-
-
35
mA
Normal mode; VBGE = VIO;
VTXEN = 0 V; Rbus = ∞ Ω
-
-
15
mA
Star-transmit mode
-
-
62
mA
Star-receive mode
-
-
42
mA
2.75
-
4.5
V
low power modes
−1
+1
+5
µA
Normal and Receive-only
mode; VTXD = VIO
-
-
1000
µA
Pin VBAT
IBAT
Vuvd(VBAT)
supply current on pin VBAT low power modes in node
configuration
undervoltage detection
voltage on pin VBAT
Pin VCC
ICC
supply current
Normal mode; VBGE = VIO;
VTXEN = 0 V; VBUF open
Vuvd(VCC)
undervoltage detection
voltage on pin VCC
[3]
Pin VIO
IIO
supply current on pin VIO
TJA1080_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 12 July 2007
27 of 48
TJA1080
NXP Semiconductors
FlexRay transceiver
Table 14. Static characteristics …continued
All parameters are guaranteed for VBAT = 6.5 V to 60 V; VCC = 4.75 V to 5.25 V; VBUF = 4.75 V to 5.25 V; VIO = 2.2 V to 5.25 V;
Tvj = −40 °C to + 150 °C; Rbus = 45 Ω; RTRXD = 200 Ω unless otherwise specified. All voltages are defined with respect to
ground; positive currents flow into the IC.[1][2]
Symbol
Parameter
Vuvd(VIO)
Conditions
Min
Typ
Max
Unit
undervoltage detection
voltage on pin VIO
1
-
2
V
Vuvr(VIO)
undervoltage recovery
voltage on pin VIO
1
-
2.2
V
Vuvhys(VIO)
undervoltage hysteresis
voltage on pin VIO
25
-
200
mV
−1
0
+5
µA
−40
−20
+1
µA
−1
0
+10
µA
-
-
35
mA
Star-transmit mode
-
-
62
mA
Star-receive mode
-
-
42
mA
Normal mode; VBGE = 0 V;
VTXEN = VIO; Receive-only
mode; Star-idle mode
-
-
15
mA
Pin VBUF
IBUF
supply current on pin
VBUF
low power modes in node
configuration
low power modes in star
configuration
VBUF = 0 V; VCC = 0 V
VBUF = 5.25 V
Normal mode; VBGE = VIO;
VTXEN = 0 V; VBUF = VCC
[3]
VBUF(on)
on-state voltage on pin
VBUF
VCC switch is switched on;
Normal mode; VBGE = VIO;
VTXEN = 0 V; VCC > maximum
value of Vuvd(VCC)
VCC − 0.25 -
VCC
V
VBUF(off)
off-state voltage on pin
VBUF
VCC switch is switched off; low
power modes in star
configuration; VCC < minimum
value of Vuvd(VCC)
4.5
-
5.25
V
Pin EN
VIH(EN)
HIGH-level input voltage
on pin EN
0.7VIO
-
5.5
V
VIL(EN)
LOW-level input voltage
on pin EN
−0.3
-
0.3VIO
V
IIH(EN)
HIGH-level input current
on pin EN
VEN = 0.7VIO
3
-
11
µA
IIL(EN)
LOW-level input current
on pin EN
VEN = 0 V
−1
0
+1
µA
Pin STBN
VIH(STBN)
HIGH-level input voltage
on pin STBN
0.7VIO
-
5.5
V
VIL(STBN)
LOW-level input voltage
on pin STBN
−0.3
-
0.3VIO
V
IIH(STBN)
HIGH-level input current
on pin STBN
3
-
11
µA
VSTBN = 0.7VIO
TJA1080_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 12 July 2007
28 of 48
TJA1080
NXP Semiconductors
FlexRay transceiver
Table 14. Static characteristics …continued
All parameters are guaranteed for VBAT = 6.5 V to 60 V; VCC = 4.75 V to 5.25 V; VBUF = 4.75 V to 5.25 V; VIO = 2.2 V to 5.25 V;
Tvj = −40 °C to + 150 °C; Rbus = 45 Ω; RTRXD = 200 Ω unless otherwise specified. All voltages are defined with respect to
ground; positive currents flow into the IC.[1][2]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IIL(STBN)
LOW-level input current
on pin STBN
VSTBN = 0 V
−1
0
+1
µA
Pin TXEN
VIH(TXEN)
HIGH-level input voltage
on pin TXEN
0.7VIO
-
VIO + 0.3
V
VIL(TXEN)
LOW-level input voltage
on pin TXEN
−0.3
-
0.3VIO
V
IIH(TXEN)
HIGH-level input current
on pin TXEN
VTXEN = VIO
−1
0
+1
µA
IIL(TXEN)
LOW-level input current
on pin TXEN
VTXEN = 0.3VIO
−12
-
−3
µA
IL(TXEN)
leakage current on pin
TXEN
VTXEN = 5.25 V; VIO = 0 V
−1
0
+1
µA
Pin BGE
VIH(BGE)
HIGH-level input voltage
on pin BGE
0.7VIO
-
VIO + 0.3
V
VIL(BGE)
LOW-level input voltage
on pin BGE
−0.3
-
0.3VIO
V
IIH(BGE)
HIGH-level input current
on pin BGE
VBGE = 0.7VIO
3
-
11
µA
IIL(BGE)
LOW-level input current
on pin BGE
VBGE = 0 V
−1
0
+1
µA
VIH(TXD)
HIGH-level input voltage
on pin TXD
normal power modes
0.7VIO
-
VIO + 0.3
V
VIL(TXD)
LOW-level input voltage
on pin TXD
normal power modes
−0.3
-
0.3VIO
V
IIH(TXD)
HIGH-level input current
on pin TXD
VTXD = VIO
70
300
650
µA
IIL(TXD)
LOW-level input current
on pin TXD
normal power modes;
VTXD = 0 V
−5
0
+5
µA
low power modes
−1
0
+1
µA
VTXD = 5.25 V; VIO = 0 V
−1
0
+1
µA
Pin TXD
ILI(TXD)
input leakage current on
pin TXD
Pin RXD
IOH(RXD)
HIGH-level output current VRXD = VIO − 0.4 V; VIO = VCC
on pin RXD
−20
-
−2
mA
IOL(RXD)
LOW-level output current
on pin RXD
2
-
20
mA
VRXD = 0.4 V
TJA1080_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 12 July 2007
29 of 48
TJA1080
NXP Semiconductors
FlexRay transceiver
Table 14. Static characteristics …continued
All parameters are guaranteed for VBAT = 6.5 V to 60 V; VCC = 4.75 V to 5.25 V; VBUF = 4.75 V to 5.25 V; VIO = 2.2 V to 5.25 V;
Tvj = −40 °C to + 150 °C; Rbus = 45 Ω; RTRXD = 200 Ω unless otherwise specified. All voltages are defined with respect to
ground; positive currents flow into the IC.[1][2]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
−1500
−550
−100
µA
star configuration;
VERRN = VIO − 0.4 V;
VIO = VCC
−1
0
+1
µA
VERRN = 0.4 V
300
700
1500
µA
Pin ERRN
IOH(ERRN)
IOL(ERRN)
HIGH-level output current node configuration;
on pin ERRN
VERRN = VIO − 0.4 V;
VIO = VCC
LOW-level output current
on pin ERRN
Pin RXEN
IOH(RXEN)
HIGH-level output current VRXEN = VIO − 0.4 V;
on pin RXEN
VIO = VCC
−4
−1.5
−0.5
mA
IOL(RXEN)
LOW-level output current
on pin RXEN
VRXEN = 0.4 V
1
3
8
mA
Pins TRXD0 and TRXD1
VIH(TRXD0)
HIGH-level input voltage
on pin TRXD0
Star-idle and Star-transmit
mode
0.7VBUF
-
VBUF + 0.3 V
VIL(TRXD0)
LOW-level input voltage
on pin TRXD0
Star-idle and Star-transmit
mode
−0.3
-
0.3VBUF
V
VOL(TRXD0)
LOW-level output voltage
on pin TRXD0
Rpu = 200 Ω
−0.3
-
+0.8
V
VIH(TRXD1)
HIGH-level input voltage
on pin TRXD1
Star-idle and Star-transmit
mode
0.7VBUF
-
VBUF + 0.3 V
VIL(TRXD1)
LOW-level input voltage
on pin TRXD1
Star-idle and Star-transmit
mode
−0.3
-
0.3VBUF
V
VOL(TRXD1)
LOW-level output voltage
on pin TRXD1
Rpu = 200 Ω
−0.3
-
+0.8
V
Normal, Receive-only,
Star-idle, Star-transmit and
Star-receive mode; VTXEN =
VIO
0.4VBUF
0.5VBUF
0.6VBUF
V
Standby, Go-to-sleep, Sleep,
Star-standby and Star-sleep
mode
−0.1
0
+0.1
V
Normal, Receive-only,
Star-idle, Star-transmit and
Star-receive mode; VTXEN =
VIO
0.4VBUF
0.5VBUF
0.6VBUF
V
Standby, Go-to-sleep, Sleep,
Star-standby and Star-sleep
mode
−0.1
0
+0.1
V
−60 V < |VBP| < +60 V
1
-
7.5
mA
Pins BP and BM
Vo(idle)(BP)
Vo(idle)(BM)
Io(idle)BP
idle output voltage on pin
BP
idle output voltage on pin
BM
idle output current on pin
BP
TJA1080_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 12 July 2007
30 of 48
TJA1080
NXP Semiconductors
FlexRay transceiver
Table 14. Static characteristics …continued
All parameters are guaranteed for VBAT = 6.5 V to 60 V; VCC = 4.75 V to 5.25 V; VBUF = 4.75 V to 5.25 V; VIO = 2.2 V to 5.25 V;
Tvj = −40 °C to + 150 °C; Rbus = 45 Ω; RTRXD = 200 Ω unless otherwise specified. All voltages are defined with respect to
ground; positive currents flow into the IC.[1][2]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Io(idle)BM
idle output current on pin
BM
−60 V < |VBM| < +60 V
1
-
7.5
mA
Vo(idle)(dif)
differential idle output
voltage
−25
0
+25
mV
VOH(dif)
differential HIGH-level
output voltage
40 Ω < Rbus < 55 Ω;
VCC = VBUF = 5 V
600
800
1200
mV
VOL(dif)
differential LOW-level
output voltage
40 Ω < Rbus < 55 Ω;
VCC = VBUF = 5 V
−1200
−800
−600
mV
VIH(dif)
differential HIGH-level
input voltage
normal power modes;
−10 V < VBP < +15 V;
−10 V < VBM < +15 V
150
225
300
mV
VIL(dif)
differential LOW-level
input voltage
normal power modes;
−10 V < VBP < +15 V;
−10 V < VBM < +15 V
−300
−225
−150
mV
low power modes;
−10 V < VBP < +15 V;
−10 V < VBM < +15 V
−400
−225
−125
mV
|Vi(dif)det(act)|
activity detection
differential input voltage
(absolute value)
normal power modes
150
225
300
mV
|Io(sc)(BP)|
short-circuit output
current on pin BP
(absolute value)
VBP = 0 V, 60 V
10
20
30
mA
|Io(sc)(BM)|
short-circuit output
current on pin BM
(absolute value)
VBM = 0 V, 60 V
10
20
30
mA
Ri(BP)
input resistance on pin BP idle level; Rbus = ∞ Ω
10
20
40
kΩ
Ri(BM)
input resistance on pin
BM
idle level; Rbus = ∞ Ω
10
20
40
kΩ
Ri(dif)(BP-BM)
differential input
resistance between pin
BP and pin BM
idle level; Rbus = ∞ Ω
20
40
80
kΩ
Vcm(bus)(DATA_0) DATA_0 bus
common-mode voltage
Rbus = 45 Ω
0.4VBUF
0.5VBUF
0.6VBUF
V
Vcm(bus)(DATA_1) DATA_1 bus
common-mode voltage
Rbus = 45 Ω
0.4VBUF
0.5VBUF
0.6VBUF
V
∆Vcm(bus)
Rbus = 45 Ω
−25
0
+25
mV
bus common-mode
voltage difference
Pin INH1
VOH(INH1)
HIGH-level output voltage IINH1 = −0.2 mA
on pin INH1
VBAT − 0.8
-
VBAT
V
IL(INH1)
leakage current on pin
INH1
Sleep mode
−5
0
+5
µA
IOL(INH1)
LOW-level output current
on pin INH1
VINH1 = 0 V
−15
-
-
mA
TJA1080_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 12 July 2007
31 of 48
TJA1080
NXP Semiconductors
FlexRay transceiver
Table 14. Static characteristics …continued
All parameters are guaranteed for VBAT = 6.5 V to 60 V; VCC = 4.75 V to 5.25 V; VBUF = 4.75 V to 5.25 V; VIO = 2.2 V to 5.25 V;
Tvj = −40 °C to + 150 °C; Rbus = 45 Ω; RTRXD = 200 Ω unless otherwise specified. All voltages are defined with respect to
ground; positive currents flow into the IC.[1][2]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Pin INH2
VOH(INH2)
HIGH-level output voltage IINH2 = −0.2 mA
on pin INH2
VBAT − 0.8
-
VBAT
V
IL(INH2)
leakage current on pin
INH2
Sleep mode
−5
0
+5
µA
IOL(INH2)
LOW-level output current
on pin INH2
VINH2 = 0 V
−15
-
-
mA
Vth(det)(WAKE)
detection threshold
voltage on pin WAKE
low power mode
2.5
-
4.5
V
IIL(WAKE)
LOW-level input current
on pin WAKE
VWAKE = 2.4 V for
t > twake(WAKE)
3
-
11
µA
IIH(WAKE)
HIGH-level input current
on pin WAKE
VWAKE = 4.6 V for
t > twake(WAKE)
−11
-
−3
µA
Pin WAKE
Temperature protection
Tj(warn)(medium)
medium warning junction
temperature
155
165
175
°C
Tj(dis)(high)
high disable junction
temperature
180
190
200
°C
[1]
All parameters are guaranteed over the virtual junction temperature range by design, but only 100 % are tested at 125 °C for dies on
wafer level (pre-testing) and above this for cased products 100 % are tested at Tamb = −40 °C and +25 °C (final testing) unless otherwise
specified. Both pre-testing and final testing use correlated test conditions to cover the specified temperature and power supply voltage
range. For bare dies all parameters are only guaranteed with the backside of the bare die connected to ground.
[2]
At power-up VBAT should be supplied first. When VBAT reaches 6.5 V, VCC and VIO may be switched on with a delay of at least 60 µs with
respect to VBAT.
[3]
Current flows from VCC to VBUF. This means that the maximum sum current ICC + IBUF is 35 mA.
TJA1080_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 12 July 2007
32 of 48
TJA1080
NXP Semiconductors
FlexRay transceiver
11. Dynamic characteristics
Table 15. Dynamic characteristics
All parameters are guaranteed for VBAT = 6.5 V to 60 V; VCC = 4.75 V to 5.25 V; VBUF = 4.75 V to 5.25 V; VIO = 2.2 V to 5.25 V;
Tvj = −40 °C to + 150 °C; Rbus = 45 Ω; RTRXD = 200 Ω unless otherwise specified. All voltages are defined with respect to
ground; positive currents flow into the IC[1].
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
delay time from TXD to bus
Normal or Star-transmit
mode
DATA_0
-
-
50
ns
DATA_1
-
-
50
ns
-
-
4
ns
-
-
50
ns
-
-
50
ns
-
-
5
ns
DATA_0
-
-
50
ns
DATA_1
-
-
50
ns
-
-
5
ns
-
-
50
ns
-
-
50
ns
-
-
5
ns
Pins BP and BM
td(TXD-bus)
[2]
∆td(TXD-bus)
delay time difference from TXD
to bus
Normal or Star-transmit
mode; between DATA_0
and DATA_1
[2]
td(TRXD-bus)
delay time from TRXD to bus
Star-transmit mode
[3]
DATA_0
DATA_1
∆td(TRXD-bus)
delay time difference from TRXD Star-transmit mode;
to bus
between DATA_0 and
DATA_1
td(bus-RXD)
delay time from bus to RXD
[3][4]
Normal or Star-transmit
mode; CRXD = 15 pF; see
Figure 11
∆td(bus-RXD)
delay time difference from bus to Normal or Star-transmit
RXD
mode; CRXD = 15 pF;
between DATA_0 and
DATA_1; see Figure 11
td(bus-TRXD)
delay time from bus to TRXD
Star-receive mode; see
Figure 11
DATA_0
DATA_1
∆td(bus-TRXD)
delay time difference from bus to Star-receive mode;
TRXD
between DATA_0 and
DATA_1; see Figure 11
td(TXEN-busidle)
delay time from TXEN to bus
idle
Normal mode
-
-
50
ns
td(TXEN-busact)
delay time from TXEN to bus
active
Normal mode
-
-
50
ns
td(BGE-busidle)
delay time from BGE to bus idle Normal mode
-
-
50
ns
td(BGE-busact)
delay time from BGE to bus
active
Normal mode
-
-
50
ns
tr(dif)(bus)
bus differential rise time
10 % to 90 %; RL = 45 Ω;
CL = 100 pF
8
12
23
ns
tf(dif)(bus)
bus differential fall time
90 % to 10 %; RL = 45 Ω;
CL = 100 pF
8
12
23
ns
TJA1080_2
Product data sheet
[4]
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 12 July 2007
33 of 48
TJA1080
NXP Semiconductors
FlexRay transceiver
Table 15. Dynamic characteristics …continued
All parameters are guaranteed for VBAT = 6.5 V to 60 V; VCC = 4.75 V to 5.25 V; VBUF = 4.75 V to 5.25 V; VIO = 2.2 V to 5.25 V;
Tvj = −40 °C to + 150 °C; Rbus = 45 Ω; RTRXD = 200 Ω unless otherwise specified. All voltages are defined with respect to
ground; positive currents flow into the IC[1].
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
DATA_0 wake-up detection time Standby, Sleep,
Star-standby or
idle wake-up detection time
Star-sleep mode;
total wake-up detection time
−10 V < VBP < +15 V;
−10 V < VBM < +15 V
1
-
4
µs
1
-
4
µs
50
-
115
µs
tdet(uv)(VCC)
undervoltage detection time on
pin VCC
100
-
670
ms
trec(uv)(VCC)
undervoltage recovery time on
pin VCC
1
-
5.2
ms
tdet(uv)(VIO)
undervoltage detection time on
pin VIO
100
-
670
ms
tto(uv)(VCC)
undervoltage time-out time on
pin VCC for entering Standby
mode
star configuration; wake
flag is set
432
-
900
µs
WAKE symbol detection
tdet(wake)DATA_0
tdet(wake)idle
tdet(wake)tot
Undervoltage
Activity detection
tdet(act)(TXEN)
activity detection time on pin
TXEN
star configuration
100
-
200
ns
tdet(act)(TRXD)
activity detection time on pin
TRXD
star configuration
100
-
200
ns
tdet(act)(bus)
activity detection time on bus
pins
Vdif: 0 mV → 400 mV
100
-
250
ns
tdet(idle)(TXEN)
idle detection time on pin TXEN star configuration
100
-
200
ns
tdet(idle)(TRXD)
idle detection time on pin TRXD star configuration
tdet(idle)(bus)
idle detection time on bus pins
Vdif: 400 mV → 0 mV
50
-
100
ns
100
-
250
ns
640
-
2660
ms
Star modes
tto(idle-sleep)
idle to sleep time-out time
tto(tx-locked)
transmit to locked time-out time
2600
-
10400
µs
tto(rx-locked)
receive to locked time-out time
2600
-
10400
µs
tto(locked-sleep)
locked to sleep time-out time
64
-
333
ms
tto(locked-idle)
locked to idle time-out time
1.4
-
5.1
µs
-
-
2
µs
Node modes
td(STBN-RXD)
STBN to RXD delay time
wake flag set
td(STBN-INH2)
STBN to INH2 delay time
-
-
10
µs
th(gotosleep)
go-to-sleep hold time
20
35
50
µs
Status register
tdet(EN)
detection time on pin EN
for mode control
20
-
80
µs
TEN
time period on pin EN
for reading status bits
4
-
20
µs
td(EN-ERRN)
delay time from EN to ERRN
for reading status bits
-
-
2
µs
TJA1080_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 12 July 2007
34 of 48
TJA1080
NXP Semiconductors
FlexRay transceiver
Table 15. Dynamic characteristics …continued
All parameters are guaranteed for VBAT = 6.5 V to 60 V; VCC = 4.75 V to 5.25 V; VBUF = 4.75 V to 5.25 V; VIO = 2.2 V to 5.25 V;
Tvj = −40 °C to + 150 °C; Rbus = 45 Ω; RTRXD = 200 Ω unless otherwise specified. All voltages are defined with respect to
ground; positive currents flow into the IC[1].
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
wake-up time on pin WAKE
low power mode; falling
edge on pin WAKE;
6.5 V < VBAT < 27 V
5
25
100
µs
low power mode; falling
edge on pin WAKE;
27 V < VBAT < 60 V
25
75
175
µs
2600
-
10400
µs
WAKE
twake(WAKE)
Miscellaneous
tdetCL(TXEN_BGE) TXEN_BGE clamp detection
time
[1]
At power-up VBAT should be supplied first. When VBAT reaches 6.5 V, VCC and VIO may be switched on with a delay of at least 60 µs with
respect to VBAT.
[2]
Rise and fall time (10 % to 90 %) of tr(TXD) and tf(TXD) = 5 ns.
[3]
Rise and fall time (10 % to 90 %) of tr(TRXD) and tf(TRXD) = 5 ns.
[4]
The worst case asymmetry from one branch to another is the sum of the delay difference from TRXD0 and TRXD1 to DATA_0 and
DATA_1 plus the delay difference from DATA_0 and DATA_1 to TRXD0 and TRXD1.
TJA1080_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 12 July 2007
35 of 48
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
td(TXEN-busact)
NXP Semiconductors
TJA1080_2
Product data sheet
td(TXD-bus)
td(TXD-bus)
td(BGE-busact)
td(TXEN-busidle)
td(BGE-busidle)
0.7VIO
TXD
0.3VIO
0.7VIO
TXEN
0.3VIO
0.7VIO
BGE
0.3VIO
Rev. 02 — 12 July 2007
BP and BM
90 %
+300 mV
0V
−300 mV
−150 mV
−300 mV
−150 mV
−300 mV
10 %
0.7VIO
RXEN
0.3VIO
0.7VIO
RXD
0.3VIO
td(bus-RXD)
td(bus-RXD)
tdet(idle)(bus)
tdet(act)(bus)
tdet(idle)(bus)
tdet(act)(bus)
tr(dif)(bus)
tf(dif)(bus)
001aae445
Fig 10. Detailed timing diagram in node configuration
TJA1080
FlexRay transceiver
36 of 48
© NXP B.V. 2007. All rights reserved.
TJA1080
NXP Semiconductors
FlexRay transceiver
Vdif
(mV)
22.5 ns
22.5 ns
600
300
57.5 ns
−300
−600
80 ns
td(bus-RXD)
RXD
Vdif
(mV)
td(bus-RXD)
22.5 ns
22.5 ns
600
300
57.5 ns
−300
−600
80 ns
td(bus-RXD)
RXD
td(bus-RXD)
001aae446
Vdif is the receiver test signal.
Fig 11. Receiver test signal
TJA1080_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 12 July 2007
37 of 48
TJA1080
NXP Semiconductors
FlexRay transceiver
12. Test information
+12 V
+5 V
100
nF
10 µF
4
19
VIO
VCC
22 µF
14
20
VBAT
VBUF
BP
18
RL
TJA1080
BM
RXD
CL
17
7
15 pF
001aae447
Fig 12. Test circuit for dynamic characteristics
ISO 7637
PULSE
GENERATOR
12 V or 42 V
+5 V
100
nF
10 µF
4
VIO
19
VCC
10 µF
14
20
VBAT
VBUF
BP
1 nF
18
RL
TJA1080
BM
CL
17
1 nF
ISO 7637
PULSE
GENERATOR
001aae448
The waveforms of the applied transients are in accordance with ISO 7637, test pulses 1, 2, 3a,
3b, 4 and 5.
Test conditions:
Normal mode: bus idle
Normal mode: bus active; TXD at 5 MHz and TXEN at 1 kHz
Fig 13. Test circuit for automotive transients
TJA1080_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 12 July 2007
38 of 48
TJA1080
NXP Semiconductors
FlexRay transceiver
13. Package outline
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm
D
SOT339-1
E
A
X
c
HE
y
v M A
Z
20
11
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
10
w M
bp
e
detail X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
2
0.21
0.05
1.80
1.65
0.25
0.38
0.25
0.20
0.09
7.4
7.0
5.4
5.2
0.65
7.9
7.6
1.25
1.03
0.63
0.9
0.7
0.2
0.13
0.1
0.9
0.5
8
o
0
o
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
OUTLINE
VERSION
SOT339-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-150
Fig 14. Package outline SOT339-1 (SSOP20)
TJA1080_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 12 July 2007
39 of 48
TJA1080
NXP Semiconductors
FlexRay transceiver
14. Soldering
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
14.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus PbSn soldering
14.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
TJA1080_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 12 July 2007
40 of 48
TJA1080
NXP Semiconductors
FlexRay transceiver
14.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 15) than a PbSn process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 16 and 17
Table 16.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
≥ 350
< 2.5
235
220
≥ 2.5
220
220
Table 17.
Lead-free process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 15.
TJA1080_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 12 July 2007
41 of 48
TJA1080
NXP Semiconductors
FlexRay transceiver
temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 15. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
15. Appendix
15.1 Errata: known issues of the TJA1080
15.1.1 Power-up supply sequence
For proper initialization of the internal state machine the VBAT voltage has to be applied
first when powering-up the TJA1080. When VBAT reaches 6.5 V, VCC and VIO may be
switched on with a delay of at least 60 µs with respect to VBAT.
In case the rise time of the VBAT voltage from 0 V to 6.5 V is below 10 ms, VCC and VIO
shall be switched on with a delay time of at least 60 µs after VBAT has reached 6.5 V. In
case the rise time of the VBAT voltage tr(VBAT) is longer than 10 ms, no delayed switching of
VCC and VIO is needed.
The rise time of the VCC voltage should be below the minimum value of the VCC
undervoltage detection time tdet(uv)(VCC). Otherwise, an undervoltage condition at VCC
would be detected and the TJA1080 would enter Standby mode. Similarly, the rise time of
the VIO voltage should be below the minimum value of the VIO undervoltage detection time
tdet(uv)(VIO).
If the voltage on all three supply pins VBAT, VCC and VIO of the TJA1080 drops under 4 V
during a running application, the power sequence as mentioned above has to be applied
again.
TJA1080_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 12 July 2007
42 of 48
TJA1080
NXP Semiconductors
FlexRay transceiver
Consequences of an improper power-up sequence
In case of an improper initialization due to ramping up VBAT and VCC simultaneously, it
may happen that a TJA1080 transceiver applied for star configuration may come up in
node configuration.
The other way around, erroneous configuration in star configuration, while the transceiver
is applied as node transceiver, has not been observed, however it is strongly
recommended to apply the power-up sequence also to node transceivers.
Furthermore, due to improper initialization, it can occur that ERRN becomes clamped to
permanent LOW in both node and star configuration.
Work around
There is no work around for this issue. To ensure a proper device initialization the correct
power-up sequence has to be applied.
15.1.2 Bus error detection when transmitting a wake-up pattern
The TJA1080 expects a data frame that begins with a bit value different from the last bit of
the previous data frame.
This is the case for a valid data frame, which begins with the DATA_0 period of the
Transmission-Start-Sequence (TSS) and ends with the DATA_1 bit of the Frame-EndSequence (FES).
Any violation of this frame format will be detected by the TJA1080. Consequently when
transmitting a wake-up pattern, a bus error will be signaled.
Consequences
This behavior of the TJA1080 is not conform to the FlexRay Electrical Physical Layer
specification [1]
Work around
The error indication when a wake-up pattern is transmitted should be ignored and the
status register should be cleared by reading the vector.
15.1.3 Receiver signal
The delay time and delay time difference from bus to RXD (see Table 15: td(bus-RXD),
∆td(bus-RXD), td(bus-TRXD), ∆td(bus-TRXD)) is guaranteed in the TJA1080 for a minimum bit time
of 80 ns and a receiver test signal of 600 mV differential bus level (see Figure 11). This
receiver test signal is not conform to the FlexRay Electrical Physical Layer
specification (see Ref. 1).
Consequence
If the differential bus level becomes lower than 600 mV, the delay time difference from bus
to RXD (td(bus-RXD)) can become higher than 5 ns.
TJA1080_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 12 July 2007
43 of 48
TJA1080
NXP Semiconductors
FlexRay transceiver
Work around
To keep the differential bus amplitude in the entire system above 600 mV, the cable
impedance of the chosen bus cable shall be higher than 110 Ω. Moreover, the termination
resistance at the two bus ends shall be not lower than 110 Ω.
15.1.4 Wake-up signaling via RXD pin
In case of an undervoltage condition at VCC, RXD might go to LOW level.
Consequence
In case of an undervoltage condition at VCC, while the TJA1080 is in a low power mode,
the TJA1080 can give a continuous signaling of a wake-up event on pin RXD. This
behavior is not conform to the FlexRay Electrical Physical Layer specification (see Ref. 1).
Work around
Use the RXEN pin for wake-up recognition when the VCC voltage is switched off while VIO
is available.
16. Abbreviations
Table 18.
Abbreviations
Abbreviation
Description
CAN
Controller Area Network
CDM
Charged Device Model
EMC
ElectroMagnetic Compatibility
EME
ElectroMagnetic Emission
EMI
ElectroMagnetic Immunity
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
PWON
Power-on
17. References
[1]
EPL — FlexRay Communications System Electrical Physical Layer Specification
Version 2.1 Rev. A, FlexRay Consortium, Dec. 2005
[2]
PS54 — Product Specification: TJA1054; Fault-tolerant CAN transceiver,
www.nxp.com
[3]
PS41 — Product Specification: TJA1041; High speed CAN transceiver,
www.nxp.com
[4]
AN1 — Application hint AN10443_1; TJA1080 FlexRay transceiver
TJA1080_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 12 July 2007
44 of 48
TJA1080
NXP Semiconductors
FlexRay transceiver
18. Revision history
Table 19.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
TJA1080_2
20070712
Product data sheet
-
TJA1080_1
Modifications:
TJA1080_1
•
The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors
•
•
•
•
•
•
Legal texts have been adapted to the new company name where appropriate
Section 4 “Ordering information”, added type number TJA1080TS (lead free version)
Figure 1 and Figure 4 updated
Table 4, Table 5, Table 6, Table 7, Table 8 and Table 10 updated
Section 7.6 “Fail silent behavior”, added more information
Section 15 “Appendix”, added
20060720
Objective data sheet
TJA1080_2
Product data sheet
-
-
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 12 July 2007
45 of 48
TJA1080
NXP Semiconductors
FlexRay transceiver
19. Legal information
19.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
19.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
19.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a NXP Semiconductors product can reasonably be expected to
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Suitability for use in automotive applications only — This NXP
Semiconductors product has been developed for use in automotive
applications only. The product is not designed, authorized or warranted to be
suitable for any other use, including medical, military, aircraft, space or life
support equipment, nor in applications where failure or malfunction of an NXP
Semiconductors product can reasonably be expected to result in personal
injury, death or severe property or environmental damage. NXP
Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customers own risk.
19.4 Licenses
Purchase of NXP ICs with FlexRay functionality
FlexRay license required. This product has been developed within the
framework of the “FlexRay” consortium. FlexRay consortium members are
willing to grant licenses under their essential FlexRay intellectual property
rights to end users of FlexRay-enabled products upon request of an end
user. The sale by NXP Semiconductors of a FlexRay-enabled product will
not be construed as the granting of such a license. Each end user will have
to apply to the FlexRay consortium administration to obtain such a license
or to apply for membership. The FlexRay consortium can be contacted at
[email protected]
19.5 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
TJA1080_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 12 July 2007
46 of 48
TJA1080
NXP Semiconductors
FlexRay transceiver
20. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: [email protected]
TJA1080_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 12 July 2007
47 of 48
TJA1080
NXP Semiconductors
FlexRay transceiver
21. Contents
1
2
2.1
2.2
2.3
2.4
3
4
5
6
6.1
6.2
7
7.1
7.1.1
7.1.2
7.1.3
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.4
7.4.1
7.4.2
7.5
7.5.1
7.5.2
7.5.3
7.5.4
7.6
7.6.1
7.6.2
7.6.3
7.7
7.7.1
7.7.2
7.7.3
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Optimized for time triggered communication
systems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Low power management . . . . . . . . . . . . . . . . . 2
Diagnosis (detection and signalling) . . . . . . . . . 2
Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pinning information . . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functional description . . . . . . . . . . . . . . . . . . . 6
Operating configurations. . . . . . . . . . . . . . . . . . 6
Node configuration . . . . . . . . . . . . . . . . . . . . . . 6
Star configuration . . . . . . . . . . . . . . . . . . . . . . . 6
Bus activity and idle detection . . . . . . . . . . . . . 7
Operating modes in node configuration . . . . . . 7
Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . 14
Receive-only mode . . . . . . . . . . . . . . . . . . . . . 14
Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . 14
Go-to-sleep mode . . . . . . . . . . . . . . . . . . . . . . 14
Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Operating modes in star configuration . . . . . . 15
Star-idle mode . . . . . . . . . . . . . . . . . . . . . . . . 17
Star-transmit mode . . . . . . . . . . . . . . . . . . . . . 18
Star-receive mode . . . . . . . . . . . . . . . . . . . . . 18
Star-standby mode . . . . . . . . . . . . . . . . . . . . . 18
Star-sleep mode . . . . . . . . . . . . . . . . . . . . . . . 19
Star-locked mode . . . . . . . . . . . . . . . . . . . . . . 19
Start-up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Node configuration . . . . . . . . . . . . . . . . . . . . . 19
Star configuration . . . . . . . . . . . . . . . . . . . . . . 19
Wake-up mechanism . . . . . . . . . . . . . . . . . . . 20
Node configuration . . . . . . . . . . . . . . . . . . . . . 20
Star configuration . . . . . . . . . . . . . . . . . . . . . . 20
Bus wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Local wake-up via pin WAKE . . . . . . . . . . . . . 21
Fail silent behavior . . . . . . . . . . . . . . . . . . . . . 21
VBAT undervoltage. . . . . . . . . . . . . . . . . . . . . . 22
VCC undervoltage . . . . . . . . . . . . . . . . . . . . . . 22
VIO undervoltage. . . . . . . . . . . . . . . . . . . . . . . 22
Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Local wake-up source flag . . . . . . . . . . . . . . . 22
Remote wake-up source flag . . . . . . . . . . . . . 22
Wake flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.7.4
7.7.5
7.7.6
7.7.7
7.7.8
7.7.9
7.7.10
7.7.11
7.7.12
7.7.13
7.8
7.9
8
9
10
11
12
13
14
14.1
14.2
14.3
14.4
15
15.1
15.1.1
15.1.2
Power-on flag . . . . . . . . . . . . . . . . . . . . . . . . .
Node configuration flag . . . . . . . . . . . . . . . . .
Temperature medium flag . . . . . . . . . . . . . . .
Temperature high flag . . . . . . . . . . . . . . . . . .
TXEN_BGE clamped flag. . . . . . . . . . . . . . . .
Bus error flag . . . . . . . . . . . . . . . . . . . . . . . . .
UVVBAT flag. . . . . . . . . . . . . . . . . . . . . . . . . . .
UVVCC flag . . . . . . . . . . . . . . . . . . . . . . . . . . .
UVVIO flag. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error flag . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TRXD collision . . . . . . . . . . . . . . . . . . . . . . . .
Status register . . . . . . . . . . . . . . . . . . . . . . . .
Limiting values . . . . . . . . . . . . . . . . . . . . . . . .
Thermal characteristics . . . . . . . . . . . . . . . . .
Static characteristics . . . . . . . . . . . . . . . . . . .
Dynamic characteristics . . . . . . . . . . . . . . . . .
Test information. . . . . . . . . . . . . . . . . . . . . . . .
Package outline . . . . . . . . . . . . . . . . . . . . . . . .
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction to soldering. . . . . . . . . . . . . . . . .
Wave and reflow soldering . . . . . . . . . . . . . . .
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . .
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . .
Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Errata: known issues of the TJA1080. . . . . . .
Power-up supply sequence . . . . . . . . . . . . . .
Bus error detection when transmitting
a wake-up pattern . . . . . . . . . . . . . . . . . . . . .
15.1.3
Receiver signal. . . . . . . . . . . . . . . . . . . . . . . .
15.1.4
Wake-up signaling via RXD pin . . . . . . . . . . .
16
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
17
References . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
Revision history . . . . . . . . . . . . . . . . . . . . . . .
19
Legal information . . . . . . . . . . . . . . . . . . . . . .
19.1
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
19.2
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.3
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4
Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.5
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
20
Contact information . . . . . . . . . . . . . . . . . . . .
21
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
23
23
23
23
24
24
24
24
24
24
24
26
27
27
33
38
39
40
40
40
40
41
42
42
42
43
43
44
44
44
45
46
46
46
46
46
46
47
48
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 12 July 2007
Document identifier: TJA1080_2