AMSCO AS8220

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is now
ams AG
The technical content of this austriamicrosystems datasheet is still valid.
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AS8220A
O bj e c t i v e
D a ta S h e e t
F l e x R a y TM B a s i s Tra n s c e i v e r
2 Key Features
Data transfer up to 10 Mbps
This objective data sheet describes the intended
functionality of the AS8220A bus transceiver. As long
the device is not fully qualified, the parameters are not
characterized in the means that parameters may change
or can be updated during final product qualification and
characterization. This document shows the objective of
the AS8220A and this document is subjected to change
without notice.
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Compliant with FlexRay Electrical Physical Layer
Specification V2.1 Rev. B
Excellent EMC performances. High common mode
range insure excellent EMI
Enable pin for an optional bus guardian
Automatic thermal shutdown protection
The AS8220A is a high-speed automotive transceiver
for fault tolerant and high speed applications, operating
as the bi-directional interface between a generic
communication controller and the twisted pair copper
wires. The device enables two-way communication with
the microcontroller with full mode handling, including the
low-power modes.
Low standby current
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1 General Description
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Supports 2.5, 3, 3.3, 5 V micro controllers and
automatically adapts to interface levels
The transmission rates up to 10Mbps as well as the
implemented Bus Guardian interface enables this
transceiver the usage in fault tolerant and hard real-time
applications in the stringent automotive environment. An
extended diagnostic interface, offers advanced busfailure detection capabilities with the intelligent
combination of bus-current measurement and logical
comparators.
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A thermal sensor circuit with an integral shutdown
mechanism prevents damage to the device in extreme
temperature conditions. The symmetrical transient
control for the high- and low-side driver for both the busminus and bus-plus line allows an ideal balance of
communications over different network topologies, with
excellent EMC performance. The product is available in
SSOP14 package.
Protection against damage due to short circuit
conditions on the bus (positive and negative battery
voltage)
Operating temperature range -40ºC to +125ºC
3 Applications
The device is ideal for high speed automotive bus
systems, backbone bus and gateways, X-by-wire
systems, redundant bus systems, bus topologies with
Active Stars, and safety critical applications. Designed
for FlexRay, where the basic features are demanded.
Figure 1. Block Diagram
ni
VIO
ch
ERRN
VIO
BGE
Communication
Controller
Interface
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Transmitter
Digital Logic
Bus
Guardian
Interface
BP
BM
Receiver
Power Supply
Interface
VIO
VCC
Te
RxD
TxD
TxEN
Bus
Failure
Detector
Host
Controller
Interface
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GND
STBN
AS8220A
1 - 33
AS8220A
Objective Data Sheet
- Applications
Contents
1 General Description ............................................................................................................................... 1
2 Key Features ...........................................................................................................................................1
3 Applications ............................................................................................................................................ 1
4 Pin Assignments .................................................................................................................................... 4
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4.1 Pin Descriptions ................................................................................................................................................4
5 Absolute Maximum Ratings .................................................................................................................. 5
6 Electrical Characteristics....................................................................................................................... 6
7 Typical Operating Characteristics ...................................................................................................... 11
8 Detailed Description ............................................................................................................................. 12
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8.1 Block Description.............................................................................................................................................12
8.2 Events..............................................................................................................................................................12
8.3 Operating Modes.............................................................................................................................................12
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8.3.1 NORMAL mode .....................................................................................................................................13
8.3.2 STANDBY mode ...................................................................................................................................13
8.4 Non Operating Mode .......................................................................................................................................13
8.4.1 Power Off .............................................................................................................................................13
8.5 Undervoltage Events .......................................................................................................................................13
8.5.1 Undervoltage VIO...................................................................................................................................13
8.5.2 Undervoltage VCC .................................................................................................................................13
8.6 Power On/Off Events.......................................................................................................................................14
8.7 System Description .........................................................................................................................................14
8.8 Fail Silent Behavior .........................................................................................................................................15
8.8.1 State transitions due to under voltage detection ...................................................................................15
8.8.2 State transitions due to voltage recovery detection ..............................................................................15
8.9 Mode Transitions .............................................................................................................................................15
8.9.1 ERRN Signalling ...................................................................................................................................16
8.10 Loss of ground...............................................................................................................................................16
8.11 Error Flags Description ..................................................................................................................................16
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8.11.1 Bus error .............................................................................................................................................16
8.11.2 Low current on BP high side driver .....................................................................................................16
8.11.3 Low current on BP low side driver.......................................................................................................16
8.11.4 Low current on BM high side driver.....................................................................................................16
8.11.5 Low current on BM low side driver ......................................................................................................16
8.11.6 High current on BP high side driver ....................................................................................................16
8.11.7 High current on BP low side driver ......................................................................................................16
8.11.8 High current on BM high side driver ....................................................................................................17
8.11.9 High current on BM low side driver .....................................................................................................17
8.11.10 BP open line ......................................................................................................................................17
8.11.11 BM open line .....................................................................................................................................17
8.11.12 BP short circuit to VCC .......................................................................................................................17
8.11.13 BP short circuit to GND .....................................................................................................................17
8.11.14 BM short circuit toVCC .......................................................................................................................17
8.11.15 BM short circuit to GND ....................................................................................................................17
8.11.16 Short circuit between BP and BM .....................................................................................................17
8.11.17 Over temperature ..............................................................................................................................17
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AS8220A
Objective Data Sheet
- Applications
8.11.18 TxEN_BGE timeout ...........................................................................................................................17
8.11.19 Error flag ...........................................................................................................................................17
8.12 Status Flags Description................................................................................................................................17
8.12.1 Power on flag ......................................................................................................................................17
8.13 Transmitter ....................................................................................................................................................18
8.14 Receiver ........................................................................................................................................................20
Bus activity and idle detection (only in NORMAL mode).....................................................................20
Bus data detection (NORMAL mode)..................................................................................................20
Receiver test signal .............................................................................................................................22
Transceiver Timing..............................................................................................................................23
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8.14.1
8.14.2
8.14.3
8.14.4
8.15 Test Circuits ...................................................................................................................................................24
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9 Appendix ............................................................................................................................................... 25
10 Package Drawings and Markings...................................................................................................... 31
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11 Ordering Information.......................................................................................................................... 32
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AS8220A
Objective Data Sheet
- Pin Assignments
4 Pin Assignments
14
VCC
TxD
2
13
BP
TxEN
3
12
BM
RxD
4
11
GND
BGE
5
10
ERRN
STBN
6
9
7
8
AS8220A
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Pin Descriptions
VIO
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Figure 2. Pin Assignments SSOP14 Package
Table 1. Pin Descriptions
Pin Number
1
2
3
4
5
6
10
11
12
13
14
Description
I/O supply voltage
Transmit data input
Transmitter enable input
Receive data output
Bus guardian enable input
Standby input
Error diagnosis output
Ground
Bus line Minus
Bus line Plus
Supply Voltage
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Pin Name
VIO
TxD
TxEN
RxD
BGE
STBN
ERRN
GND
BM
BP
VCC
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AS8220A
Objective Data Sheet
- Absolute Maximum Ratings
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other conditions beyond those indicated in Section 6 Electrical
Characteristics on page 6 is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
Table 2. Absolute Maximum Ratings
Min
Max
Units
Notes
Supply Voltage (VCC)
-0.3
+7.0
V
Supply Voltage (VIO)
-0.3
+7.0
V
DC Voltage at EN, STBN, ERRN, TxD,
RxD, TxEN, BGE, RxEN
-0.3
VIO +
0.3
V
DC Voltage at BP and BM
-40
+50
V
Input current (latchup immunity)
-100
100
mA
According to JEDEC 78
Electrostatic discharge at bus lines BP
and BM
-4
+4
kV
According to AEC-Q100-002
Electrostatic discharge
-2
+2
kV
According to AEC-Q100-002
Transient voltage on BP, BM
-200
+200
V
According to ISO7637 part3 test pulses
a and b; class C; RL=45 W, CL= 100 pF;
(see Figure 17 on page 24).
150
mW
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Parameter
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VIO < VCC
Total power dissipation (all supplies and
outputs)
Storage temperature
-55
+150
ºC
Junction temperature
-40
+150
ºC
250
ºC
85
%
1
Package body temperature
Humidity non-condensing
5
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1. The reflow peak soldering temperature (body temperature) specified is in accordance with IPC/JEDEC J-STD020C “Moisture/Reflow Sensitivity Classification for Non-Hermetic Solid State Surface Mount Devices”. The lead
finish for Pb-free leaded packages is matte tin (100% Sn).
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AS8220A
Objective Data Sheet
- Electrical Characteristics
6 Electrical Characteristics
Tvj = -40 to +150 ºC, VCC = +4.75V to +5.25V, VIO = +2.2 to VCC, RL= 45Ω, CL= 100 pF unless otherwise specified.
Table 3. Electrical Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Supply Voltage
Ambient temperature
-40
+125
ºC
VCC-VIO
Difference of supplies
-0.1
3.05
V
30
µA
45
mA
15
mA
VCC current consumption
NORMAL mode, driver
enabled
0
NORMAL Mode, driver
enabled, RBUS = ∞Ω
0
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ICC
-5
NORMAL mode, driver
disabled
0
10
mA
STANDBY mode
VIO = 0V to +5.25V
-5
5
µA
NORMAL Mode
0
1
mA
1
50
µs
1
IIO
VIO current consumption
State Transitions
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1
STANDBY Mode
VCC = 0V to +5.25V
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Tamb
Delay STBN high to RxD
high with wake flag set
tSTANDBY
go-to STANDBY hold time
INH1 low = 20% VBAT
10
70
µs
VBUS_DIFF_D0
Differential bus voltage low
in NORMAL mode (Data0)
VBPdata0 - VBMdata0;
40Ω < RL < 55Ω
-2
-0.6
V
VBUS_DIFF_D1
Differential bus voltage
high in NORMAL mode
(Data1)
VBPdata1 - VBMdata1;
40Ω < RL < 55Ω
0.6
2
V
ΔVBUS_DIFF
Matching between Data0
and Data1 differential bus
voltage in NORMAL mode
VBUS_DIFF_D0 - VBUS_DIFF_D1
40Ω < RL < 55Ω
-200
200
mV
VBUS_COM_D0
Common mode bus voltage
in case of Data0 in
NORMAL mode
VBPdata0/2 + VBMdata0/2
40Ω < RL < 55Ω
0.4 *
VCC
0.6 *
VCC
V
VBPdata1/2 + VBMdata1/2
40Ω < RL < 55Ω
0.4 *
VCC
0.6 *
VCC
V
-200
200
mV
30
mV
ni
Transmitter
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tSTBN_RxD
Common mode bus voltage
in case of Data1 in
NORMAL mode
ch
VBUS_COM_D1
ΔVBUS_COM
Matching between Data0 V
BUS_COM_D0 - VBUS_COM_D1
and Data1 common mode
40Ω < RL < 55Ω
voltage
Absolute differential bus
voltage in idle mode
IBPBMShortMax
IBMBPShortMax
Absolute max current when
BP is shorted to BM
VBP=VBM
+100
mA
IBPGNDShortMax
Absolute max current when
BP is shorted to GND
VBP= 0V
+100
mA
IBMGNDShortMax
Absolute max current when
BM is shorted to GND
VBM= 0V
+100
mA
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VBUS_DIFF_Idle
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AS8220A
Objective Data Sheet
- Electrical Characteristics
Table 3. Electrical Characteristics
IBP-5VShortMax
Absolute max current when
BP is shorted to -5 V
IBM-5VShortMax
Max
Units
VBP= -5V
+100
mA
Absolute max current when
BM is shorted to -5 V
VBM= -5V
+100
mA
IBP27VShortMax
Absolute max current when
BP is shorted to 27 V
VBP= 27V
+100
mA
IBM27VShortMax
Absolute max current when
BM is shorted to 27 V
VBM= 27V
+100
mA
IBP48VShortMax
Absolute max current when
BP is shorted to 48 V
VBP= 48V
+100
mA
IBM48VShortMax
Absolute max current when
BM is shorted to 48 V
VBM= 48V
tTxD_BUS01
Delay time from TxD to
BUS positive edge
tTxD_RISE = 5ns
Delay time from TxD to
BUS negative edge
tTxD_FALL = 5ns
Delay time from TxD to
BUS mismatch
tTxD_BUS10 - tTxD_BUS01
tBUS10
Fall time differential bus
voltage
tBUS01
Rise time differential bus
voltage
tTxEN_BUS_Idle_Active
tTxD_BUS10
Min
Typ
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Conditions
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Parameter
+100
mA
50
ns
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Symbol
50
ns
-4
4
ns
80% - 20% of VBUS
3.75
18.75
ns
20% - 80% of VBUS
3.75
18.75
ns
Delay time from TxEN to
bus active
50
ns
tTxEN_BUS_Active_Idle
Delay time from TxEN to
bus idle
50
ns
tTxEN_MISMATCH
Delay time from TxEN to
bus mismatch
50
ns
tBGE_BUS_Idle_Active
Delay time from BGE to
bus active
50
ns
tBGE_BUS_Active_Idle
Delay time from BGE to
bus idle
50
ns
Differential bus voltage
transition time: idle to
active
30
ns
tBUS_Active_Idle
Differential bus voltage
transition time: active to
idle
30
ns
tTxEN_timeout
TxEN timeout
0.64
3.07
ms
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tBUS_Idle_Active
|tTxEN_BUS_Idle_Active tTxEN_BUS_Active_Idle|
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tTxD_MISMATCH
Receiver
BP, BM input resistance
Idle mode; RBUS=∞
10
40
KΩ
RDIFF
BP, BM differential input
resistance
Idle mode; RBUS=∞
20
80
KΩ
VBPidle,
VBMidle
Idle voltage in NORMAL
mode on pin BP, BM
NORMAL mode; VTxEN =
VIO
0.4*
VCC
0.5*
VCC
0.6*
VCC
V
VBPidle_low,
VBMidle_low
Idle voltage in STANDBY
mode on pin BP, BM
STANDBY mode
-0.2
0
+0.2
V
Te
RBP, RBM
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Revision 17920-001-10a
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AS8220A
Objective Data Sheet
- Electrical Characteristics
Parameter
Conditions
Min
IBPidle
Absolute idle output current
on pin BP
-40V < VBP < 50V
IBMidle
Absolute idle output current
on pin BM
IBPleak,
IBMleak
Units
0
7.5
mA
-40V < VBM < 50V
0
7.5
mA
Absolute leakage current,
when not powered
VBP = VBM = 5V, VCC = 0V,
VBAT = 0V; VIO = 0V
0
+10
uA
VBUSActiveHigh
Activity detection
differential input voltage
high
NORMAL mode
-10V < (VBP , VBM) < 15V
150
225
400
mV
VBUSActiveLow
Activity detection
differential input voltage
low
NORMAL mode
-10V < (VBP , VBM)< 15V
-400
-225
-150
mV
VData1
Data1 detection differential
input voltage
Pre-condition: activity already
detected. NORMAL mode.
-10V < (VBP , VBM)< 15V
150
225
300
mV
VData0
Data0 detection differential
input voltage
Pre-condition: activity already
detected. NORMAL mode.
-10V < (VBP , VBM)< 15V
-300
VDataErr
Mismatch between Data0
and Data1 differential input
voltage
tBUS_RxD10
Delay from BUS to RxD
negative edge
CRxD = 15 pF
tBUS_RxD01
Delay from BUS to RxD
positive edge
tBIT
Bit time
tRxD_ASYM
Delay time from BUS to
RxD mismatch
tRxD_FALL
Fall time RxD voltage
tBUSIdleDetection
-150
mV
10
%
3
80
ns
CRxD = 15 pF
3
80
ns
CRxD = 15 pF
3
2 x (⎜⎜VData0⎜- ⎜VData1⎜⎜) /
(⎜VData0⎜+⎜VData1⎜)
2
54
CRXD=15 pF;
|tBUS_RxD10- tBUS_RxD01|
3
80% - 20% of VRxD;
CRxD=15 pF
3
20% - 80% of VRxD;
CRxD=15 pF
-225
3
ns
5
ns
5
ns
5
ns
Idle detection time
VBUS: 400mV → 0V
50
200
ns
Activity detection time
VBUS: 0V → 400mV
100
250
ns
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tBUSActivitiyDetection
Rise time RxD voltage
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tRxD_RISE
Typ
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Symbol
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Table 3. Electrical Characteristics
Idle reaction time
VBUS: 400mV → 0V
50
300
ns
tBUSActivityReaction
Activity reaction time
VBUS: 0V → 400mV
100
350
ns
VCC under-voltage
recovery threshold
3.5
4.5
V
VCCTHL
VCC undervoltage detection
threshold
2.5
3.5
V
VIOTHH
VIO undervoltage recovery
threshold
1.25
2.0
V
VIOTHL
VIO undervoltage detection
threshold
0.75
1.5
V
ch
tBUSIdleReaction
Supply Voltage Monitor
Te
VCCTHH
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AS8220A
Objective Data Sheet
- Electrical Characteristics
Table 3. Electrical Characteristics
Parameter
Conditions
tUV_DETECT
Detection time for
undervoltage at VBAT, VCC,
VIO
tUV_REC
Detection time for
undervoltage recovery at
VCC, VIO
Min
Typ
Max
Units
100
700
ms
0.7
5
ms
Bus Error Detection
Absolute bus current for
low current detection
NORMAL mode, Transmitter
enabled
5
ITHH
Absolute bus current for
high current detection
NORMAL mode, Transmitter
enabled
40
VSHORT
Differential voltage on BP
and BM for detecting short
circuit between bus lines
NORMAL mode, Transmitter
enabled
tBUS_ERROR
Bus error detection time
OTTH
OTTL
mA
225
NORMAL mode, Transmitter
enabled
mV
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Over Temperature
mA
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ITHL
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Symbol
20
µs
Over temperature
threshold
150
180
ºC
Over temperature
hysteresis
10
20
ºC
0.7*
VIO
V
Communication Controller Interface
VTxDIH
Threshold for detecting
TxD as on logical high
Threshold for detecting
TxD as on logical low
0.3*
VIO
ITxDIH
TxD high level input current
30
100
µA
ITxDIL
TxD low level input current
-5
5
µA
VTxENIH
Threshold for detecting
TxEN as on logical high
0.7*
VIO
V
VTXENIL
Threshold for detecting
TxEN as on logical low
0.3*
VIO
TxEN high level input
current
-5
5
µA
TxEN low level input
current
-100
-30
µA
IRxD = -4mA, VIO = 5V
0.8*
VIO
1.0*
VIO
V
IRxD = 4mA, VIO = 5V
0
0.2*
VIO
V
0.7*
VIO
V
ITxENIL
ca
VTxDIL
VRxDOH
RxD high level output
voltage
ch
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ITxENIH
VRxDOL
RxD low level output
voltage
V
V
Host Interface
Threshold for detecting
STBN as on logical high
VSTBNIL
Threshold for detecting
STBN as on logical low
0.3*
VIO
ISTBNIH
STBN high level input
current
30
Te
VSTBNIH
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Revision 17920-001-10a
V
100
µA
9 - 33
AS8220A
Objective Data Sheet
- Electrical Characteristics
Table 3. Electrical Characteristics
Conditions
ISTBNIL
STBN low level input
current
tSTBN_DEB_STBY
Min
Max
Units
-5
5
µA
STBN de-bouncing time
STANDBY mode
0.1
40
µs
tSTBN_DEB_NORM
STBN de-bouncing time
NORMAL mode
0.1
2
µs
VERRNOH
ERRN high level output
voltage
IERRN = -4mA, VIO = 5V
0.8*
VIO
1.0*
VIO
V
VERRNOL
ERRN low level output
voltage
IERRN = 4mA, VIO = 5V
0
0.2*
VIO
V
Bus Guardian Interface
Typ
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Parameter
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Symbol
Threshold for detecting
BGE as on logical high
VBGEIL
Threshold for detecting
BGE as on logical low
0.3*
VIO
BGE high level input
current
30
100
µA
BGE low level input current
-5
5
µA
IBGEIH
IBGEIL
0.7*
VIO
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VBGEIH
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1. STBN, ERRN, TxD, RxD, TxEN, and BGE open
2. Test condition: (VBP + VBM) / 2 = 2,5V ± 5%
3. For test signal (see Figure 15)
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AS8220A
Objective Data Sheet
- Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s
7 Typical Operating Characteristics
Figure 4.
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Figure 3.
Figure 6.
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Figure 5.
Figure 8.
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Figure 7.
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AS8220A
Objective Data Sheet
- Detailed Description
8 Detailed Description
The AS8220A is a high-speed fault tolerant device operating as an interface between a generic controller and the
copper wire physical bus. The AS8220A is designed to extend the application range for high speed and safety critical
time triggered bus systems in an automotive environment. The drivers are short circuit protected against the positive
and negative supply voltage to increase the robustness and reliability of automotive systems. The AS8220A operates
at baudrates up to 10 Mbps to increase the bandwidth for automotive applications.
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Block Description
The AS8220A consists of 8 different functional blocks (see Figure 1):
Table 4. Functional Blocks
Short Description
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Functional Block
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The electrical AS8220A high-speed bus-system transceiver is the interface between a FlexRay™ network node
module and the channel. The transceiver provides differential transmit and receive capability to the bus, allowing the
node module bidirectional time multiplexed binary data stream transfer. Besides the transmit and receive function, the
transceiver provides low power management, supply voltage monitoring (under voltage detection) as well as bus
failure detection and represents a ESD-protection barrier between the bus and the ECU.
Host Controller Interface (HCI)
Digital interface between the transceiver and the host controller (HC)
The host interface comprises the read out handler, which delivers failure and
status information via the ERRN pin to the host controller.
Communication Controller Interface Digital interface between the transceiver and the FlexRay communication
(CCI)
controller (CC)
Bus Guarding Interface (BGI)
Power Supply Interface
(PSI)
Digital interface between the transceiver and the FlexRay bus guardian (BG)
The power supply interface consists of an sub functional block, the voltage
monitor (VM) and includes two analogue inhibit outputs for signalling the
internal state of the transceiver
Internal Logic (IL)
The digital signals from the functional blocks of the device are fed into the
internal logic where the forwarding of FlexRay messages from analogue side
to digital interfaces and vice versa is done. The state machine is performed in
this block and is dealing the error, wake and power-on flags.
Bus Failure Detector (BFD)
Temperature Protection (TP)
The bus failure detector is directly connected to the bus pins, in order to detect
several external failure conditions which may occur on the bus.
The temperature protection turns off the output driver when reaching the
specified internal temperature in order to protect the device.
The transmitter provides the bus signals as specified on the bus lines.
ca
Transmitter
Events
The receiver captures FlexRay valid signals on the bus lines and provides
received data streams to the internal logic
ni
Receiver
ch
Transitions in order to change between the operation modes are possible only when events are detected. The device
supports two type of events, events on the host controller interface (STBN) and detection of undervoltage or supply
voltage recovery. Whenever an event is recognized, a transition can be performed.
Te
Operating Modes
The AS8220A provides the following operating modes:
NORMAL: non low power mode
STANDBY: low power mode
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Revision 17920-001-10a
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AS8220A
Objective Data Sheet
- Detailed Description
NORMAL mode
In this mode the transceiver is able to send and receive data signals on the bus. TxEN and BGE control the state of the
transmitter. RxD reflects the bus data and reflect the bus state. In this mode, the transmitter state can be selected as
shown in the Table 5. In case the over-temperature flag is set the transmitter is disabled. The bus wires are terminated
to VCC/2 via receiver input resistances.
Table 5. Transmitter State
TxEN
TxD
Transmitter state
Bus State
H
L
H
Enabled
Data1 (BP is driven high, BM is driven low)
H
L
L
Enabled
Data0 (BP is driven low, BM is driven High)
X
H
X
Disabled
Idle (BP and BM are not driven)
L
X
X
Disabled
Idle (BP and BM are not driven)
lv
al
id
BGE
If the differential bus voltage is higher than VBUSActivehigh or lower than VBUSActivelow for a time longer than tBUSActhen activity is detected on the bus (Bus = active), RxD is released.
tivityDetection,
am
lc s
on A
te G
nt
st
il
If, after the activity detection, the differential bus voltage is higher than VData1, RxD is high.
If, after the activity detection, the differential bus voltage is lover than VData0, RxD is low.
If the absolute differential bus voltage is lower than VBUSActivehigh and higher than VBUSActivelow for a time longer
than tBUSIdleDetection, then idle is detected on the bus (Bus=idle), RxD is switched to logical “high”
STANDBY mode
In this mode the transceiver is not able to send and receive data signals from the bus. The power consumption is
significantly reduced respect the NORMAL mode. The bus wires are terminated to GND (bus state: Idle_LP).
Non Operating Mode
The AS8220A provides the following non operating mode:
Power Off
In this mode the transceiver is not able to operate. RxD is set to high and ERRN is set to low. The bus wires are not
connected to GND (bus state: Idle_HZ).
Undervoltage Events
Undervoltage VIO
ni
Undervoltage VCC
ca
When VIO voltage falls below VIOTHL for a time longer than tUV_DETECT then the undervoltage VIO flag is set and it is
reset when VIO exceeds the voltage threshold VIOTHH for a time longer than tUV_REC. The flag can be set or reset in all
the operation modes. The flag is reset at power off.
Te
ch
When VCC voltage falls below VCCTHL for a time longer than tUV_DETECT then the undervoltage VCC flag is set and it is
reset when VCC exceeds the voltage threshold VCCTHH for a time longer than tUV_REC. The flag can be set or reset in
all the operation modes. The flag is reset at power off.
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Revision 17920-001-10a
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AS8220A
Objective Data Sheet
- Detailed Description
Power On/Off Events
Starting from power off mode a power on event occurs in case undervoltage flag is reset.
Starting from every operation mode a power off event occurs in case VCC undervoltage flag is set.
System Description
al
id
Figure 9. State Diagram
VREC_VCC
UV_VCC
UV_VIO
OR
STBN=0
Power Off
VREC_VIO WHILE (STBN=1)
OR
STBN=1
am
lc s
on A
te G
nt
st
il
UV
Input:
STBN = 1
C
_V C
lv
Normal
UV_VCC
ni
ca
Standby
Input:
STBN = 0
VREC_VIO WHILE (STBN=0)
ch
Note: In Table 7 the corresponding transition table is shown
Prefix of “WHILE” is always the event and suffix in brackets checks the flags or in case of STBN the input condition.
For example: VREC_VBAT WHILE (STBN=1)
Te
After the event VIO supply voltage recovery is detected, the transition is performed if STBN is “high”.
Legend:
UV_VIO: Undervoltage event and/or flag for VIO supply voltage
UV_VCC: Undervoltage event and/or flag for VCC supply voltage
VREC_VIO: Voltage recovery event and/or flag for VIO supply voltage
VREC_VCC: Voltage recovery event and/or flag for VCC supply voltage
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AS8220A
Objective Data Sheet
- Detailed Description
Fail Silent Behavior
In order to be fail silent, undervoltage detection on the two power supplies VIO and VCC is implemented
VIO: Supply voltage for I/O digital level adaptation
VCC: Supply voltage (+5V)
State transitions due to under voltage detection
al
id
In case of VIO undervoltage is detected, STANDBY mode will be entered regardless of the voltage present on pin
STBN.
In case VCC undervoltage is present, the device will enter power off mode (bus state: Idle_HZ), regardless on
supply voltage at VIO and the voltage present on STBN.
State transitions due to voltage recovery detection
lv
Starting from the power off, the device enters STANDBY mode only in case VCC undervoltage flag is reset..
When VCC ≤ VCCTHL the device is in power off state and the bus wires are not terminated (bus state: Idle_HZ).
am
lc s
on A
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nt
st
il
Mode Transitions
In case all the undervoltage flags are reset the operation mode is selected by STBN according to Table 6.
Table 6. Pin Signalling and Operating modes
Inputs
OutPut
Operation Mode
STBN
H
NORMAL
L
RxD
RxEN
L
Bus = Data_0
L
Bus = Active
H
Bus = Idle or Data_1
H
Bus = Idle
H
H
STANDBY
Where: H = Digital level high
L = Digital level low
x = Do not care
Float = The analog output is not driven
Table 7. Transition Table
Intial Mode
ca
Supply Voltage Flag Event
Host Event
VIO
VCC
STBN
L
L
H→L
L→H
L
X
H→L
L
H
L
L
L→H
Power Off
X
H→L
X
Standby
Any
X
L→H
X
Power Off
ni
Normal
Standby
Normal
Te
ch
Standby
Next Mode
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AS8220A
Objective Data Sheet
- Detailed Description
ERRN Signalling
The ERRN signalling is shown in Table 8.
Table 8. ERRN signalling
HOST COMMAND
STBN
ERRN
L
H
not failure
L
L
H
L
X
L
Note: ERROR means the logic OR of the error flags
lv
Loss of ground
al
id
SUPPLY VOLTAGE FLAG EVENT
VIO
In case the ground of the device is disconnected and the host pins are open, the bus lines are switched to Idle_HZ.
am
lc s
on A
te G
nt
st
il
Error Flags Description
Bus error
The bus error flag is set when 2 consecutive rising edges on the TxD pin without any rising edge on the RxD pin are
detected or when 2 consecutive falling edges on the TxD pin without any falling edge on the RxD pin are detected. This
flag is reset when a rising edge on the TxD pin is followed by a rising edge on RxD pin before of the next TxD rising
edge or when a falling edge on the TxD pin is followed by a falling edge on RxD pin before of the next TxD falling edge.
This flag can be set or reset only in NORMAL mode when the transmitter is enabled. The flag is reset at power off.
Low current on BP high side driver
This flag can only be set/reset in NORMAL mode when the driver is enabled and during the transmission of a stable
Data1 longer than tBUS_ERROR. If the absolute value of the BP pin current is lower than ITHL after tBUS_ERROR since the
driver enable signal then the flag is set otherwise it is reset. The flag is reset at power off.
Low current on BP low side driver
This flag can only be set/reset in NORMAL mode when the driver is enabled and during the transmission of a stable
Data0 longer than tBUS_ERROR. If the absolute value of the BP pin current is lower than ITHL after tBUS_ERROR since the
driver enable signal then the flag is set otherwise it is reset. The flag is reset at power off.
Low current on BM high side driver
ca
This flag can only be set/reset in NORMAL mode when the driver is enabled and during the transmission of a stable
Data0 longer than tBUS_ERROR. If the absolute value of the BM pin current is lower than ITHL after tBUS_ERROR since the
driver enable signal then the flag is set otherwise it is reset. The flag is reset at power off.
ni
Low current on BM low side driver
ch
This flag can only be set/reset in NORMAL mode when the driver is enabled and during the transmission of a stable
Data1 longer than tBUS_ERROR. If the absolute value of the BM pin current is lower than ITHL after tBUS_ERROR since the
driver enable signal then the flag is set otherwise it is reset. The flag is reset at power off.
High current on BP high side driver
Te
This flag can only be set/reset in NORMAL mode when the driver is enabled and during the transmission of a stable
Data1 longer than tBUS_ERROR. If the absolute value of the BP pin current is higher than ITHH after tBUS_ERROR since
the driver enable signal then the flag is set otherwise it is reset. The flag is reset at power off.
High current on BP low side driver
This flag can only be set/reset in NORMAL mode when the driver is enabled and during the transmission of a stable
Data0 longer than tBUS_ERROR. If the absolute value of the BP pin current is higher than ITHH after tBUS_ERROR since
the driver enable signal then the flag is set otherwise it is reset. The flag is reset at power off.
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Revision 17920-001-10a
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AS8220A
Objective Data Sheet
- Detailed Description
High current on BM high side driver
This flag can only be set/reset in NORMAL mode when the driver is enabled and during the transmission of a stable
Data0 longer than tBUS_ERROR. If the absolute value of the BM pin current is higher than ITHH after tBUS_ERROR since
the driver enable signal then the flag is set otherwise it is reset. The flag is reset at power off.
High current on BM low side driver
BP open line
This flag is the logical “AND” between: low current on BP high side and low current on BP low side.
lv
BM open line
al
id
This flag can only be set/reset in NORMAL mode when the driver is enabled and during the transmission of a stable
Data1 longer than tBUS_ERROR. If the absolute value of the BM pin current is higher than ITHH after tBUS_ERROR since
the driver enable signal then the flag is set otherwise it is reset. The flag is reset at power off.
This flag is the logical “AND” between: low current on BM high side and low current on BM low side.
BP short circuit to VCC
am
lc s
on A
te G
nt
st
il
This flag is the logical “AND” between: low current on BP high side and high current on BP low side.
BP short circuit to GND
This flag is the logical “AND” between: high current on BP high side and low current on BP low side.
BM short circuit toVCC
This flag is the logical “AND” between: low current on BM high side and high current on BM low side.
BM short circuit to GND
This flag is the logical “AND” between: high current on BM high side and low current on BM low side.
Short circuit between BP and BM
This flag can only be set or reset in NORMAL mode when the driver is enabled. After a time tBUS_ERROR since TxD
edge if the absolute value of the differential bus voltage is lower than VSHORT then the flag is set otherwise it is reset.
he flag is reset at power off.
Over temperature
This flag can only be set or reset in the non low power modes. The flag is set when the junction temperature exceeds
OTTH and it is reset when the junction temperature falls below OTTL.
ca
TxEN_BGE timeout
Error flag
ni
This flag can only be set in NORMAL mode when the driver is enabled (TxEN is low and BGE is high) for a time longer
than tTxEN_max. It is reset every transition on TxEN or BGE or if the device exits NORMAL mode. If the flag is set the
driver is disabled.
ch
This flag is set if at least one error flag or if VIO flag is set and it is reset if none of the previous flag is set.
Status Flags Description
Te
Power on flag
The power on flag is set leaving the power off state and it is reset entering a low power mode after a non low power
mode.
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AS8220A
Objective Data Sheet
- Detailed Description
Transmitter
The transmitter generates out of a digital input signal on TxD the FlexRay differential bus voltage. The transmitter is
only active in NORMAL mode when BGE is on logical high and TxEN is on logical low.
Figure 10. Transmitter characteristics (TxD → BUS)
al
id
VTxD
70% * VIO
30% * VIO
Data0: x * tBIT
lv
Data1: x * tBIT
VBUS
VBUS_DIFF_D1
80% * VBUS_DIFF
tTxD_BUS10
tBUS01
tBUS01
am
lc s
on A
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nt
st
il
tTxD_BUS01
+ VBUS_DIFF_Idle
- VBUS_DIFF_Idle
20% * VBUS_DIFF
VBUS_DIFF_D0
Data1: x * tBIT
Data0: x * tBIT
VTxEN
70% * VIO
30% * VIO
ni
VBUS
ca
Figure 11. Transmitter characteristics (TxEN → BUS)
tTxEN_BUS_Active_Idle
< tTxEN_timeout
tTxEN_BUS_Idle_Active
< tTxEN_timeout
tBUS_Active_Idle
tBUS_Idle_Active
ch
VBUS_DIFF_D1
300 mV
Te
+ VBUS_DIFF_Idle
- VBUS_DIFF_Idle
- 300 mV
VBUS_DIFF_D0
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AS8220A
Objective Data Sheet
- Detailed Description
Figure 12. Timing characteristics (BGE → BUS)
VBGE
30% * VIO
< tTxEN_timeout
< tTxEN_timeout
VBUS
tBGE_BUS_Idle_Active
tBUS_Active_Idle
tBUS_Idle_Active
lv
tBGE_BUS_Active_Idle
al
id
70% * VIO
VBUS_DIFF_D1
300 mV
am
lc s
on A
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nt
st
il
+ VBUS_DIFF_Idle
- VBUS_DIFF_Idle
- 300 mV
VBUS_DIFF_D0
Te
ch
ni
ca
In NORMAL mode the transmitter drives on the bus Idle in case no data are transmitted. In STANDBY mode the
transmitter drives Idle_LP (idle low power) on the bus pins. In POWER OFF mode the bus pins shows Idle_HZ (idle
high impedance).
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AS8220A
Objective Data Sheet
- Detailed Description
Receiver
The receiver generates from the FlexRay differential bus voltage a digital signal on the RxD pin. RxD shows the data
(Data0 and Data1). The receiver is only active in NORMAL mode.
Figure 13. Timing characteristics of the bus signals to RxD
al
id
VBUS
VBUS_ ActiveHigh
VData1
+VBUS_DIFF_Idle
- VBUS_DIFF_Idle
Data1: x *tBIT
am
lc s
on A
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nt
st
il
Data0: x * tBIT
lv
VBUS_ ActiveLow
VData0
VRxD
tBUS_RxD10
tBUS_RxD01
tRxD_FALL
tRxD_RISE
70% *VIO
30% *VIO
Bus activity and idle detection (only in NORMAL mode)
If the absolute differential bus voltage is higher than VBUSActiveLow and less than VBUSActiveHigh for a time longer than
tBUSIdleDetection, bus Idle is detected, RxD is switched to logical high after a time tBUSIdleReaction.
If the absolute differential bus voltage is higher than VBUSActiveHigh or lower than VBUSActiveLow for a time loner than
tBUSActivitiyDetection, bus Activity is detected, RxD is following the detected bus data states as indicated below with a
time tBUSActivityReaction.
Table 9. Logic table for receiver bus signal detection
ca
Receiver Operation mode
RxD
Idle
H
Data0
L
Data1
H
ni
NORMAL mode
Bus signals
Bus data detection (NORMAL mode)
ch
If, after the activity detection the differential bus voltage is higher than VData1, RxD will be high after a time tBUS_RxD01.
Te
If, after the activity detection the differential bus voltage is lower than VData0, RxD will be low after a time tBUS_RxD10.
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AS8220A
Objective Data Sheet
- Detailed Description
Figure 14. Receiver characteristics (BUS → RxD, )
VBUS
VBUS_ ActiveHigh
VData1
am
lc s
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nt
st
il
VBUS_ ActiveLow
VData0
lv
VBUS
al
id
VRxD
Data0
Activity
Data1
Activity
Te
ch
ni
ca
Idle
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AS8220A
Objective Data Sheet
- Detailed Description
Receiver test signal
Figure 15. Receiver test signal
V BUS
22 ns
22 ns
al
id
400 mV
300 mV
lv
-300 mV
am
lc s
on A
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nt
st
il
-400 mV
tBIT
tBUS_RxD01
RxD
V BUS
22 ns
22 ns
400 mV
ca
300 mV
ch
ni
-300 mV
-400 mV
tBUS_RxD10
tBUS_RxD10
tBUS_RxD01
Te
RxD
tBIT
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Revision 17920-001-10a
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www.austriamicrosystems.com
Revision 17920-001-10a
RxD
VBUS
TxEN
BGE
TxD
0.3 * VIO
0.7 * VIO
300 mV
0.3 * Vcc
0.7 * Vcc
0.3 * Vcc
0.7 * Vcc
tBUS_RxD01
tBUS_RxD10
-300 mV
30 mV
tBGE_BUS_Idle_Active
tBUS_Idle_Active
tBUSIdleReaction
tBUSActivityReaction
-300 mV
tBUS_Active_Idle
30 mV
tTxEN_BUS_Active_Idle
tTxEN_BUS_Idle_Active
tBUS10
al
id
tBUS01
lv
-300 mV
am
lc s
on A
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nt
st
il
tBGE_BUS_Active_Idle
ca
ni
tTxD_BUS10
ch
tTxD_BUS01
Te
20 %
80 %
AS8220A
Objective Data Sheet
- Detailed Description
Transceiver Timing
Figure 16. Timing Diagram
23 - 33
AS8220A
Objective Data Sheet
- Detailed Description
Test Circuits
Figure 17. Test Circuit for Automotive Transients
+5V
Transients in accordance with ISO: 7637
test pulses 1, 2, 3a, 3b, 4, 5
Test conditions
: Normal mode bus idle
Normal mode bus active(TXD=5 MHz, TXEN=1kHz)
VCC
1
VIO
4
RXD
lv
14
al
id
100nF
15pF
am
lc s
on A
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nt
st
il
AS8220
1nF
13
BP
ISO7637
PULSE
GENERATOR
12
BM
RL
CL
1nF
Figure 18. Test circuit for dynamic characteristics
+5V
100nF
1
ca
14
VIO
RXD
4
15pF
AS 8220
Te
ch
ni
VCC
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BP
BM
Revision 17920-001-10a
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12
RL
CL
24 - 33
AS8220A
Objective Data Sheet
- Appendix
9 Appendix
The following table shows the comparison of conventions used in AS8220A datasheet and FlexRay Electrical Physical
Layer Specification V2.1 Rev. B.
Table 10. Comparison table
Symbol
al
id
FlexRay
Electrical Physical Layer Specification V2.1 RevB
AS8220A Datasheet
Parameter
Name
Description
-
Battery Supply Voltage (VBAT)
-
-
-
Supply Voltage (VCC)
-
-
-
Supply Voltage (VIO)
-
-
-
DC Voltage at EN, STBN, ERRN,
TxD, RxD, TxEN, BGE, RxEN
-
-
DC Voltage on pin WAKE, INH1, INH2
-
-
-
DC Voltage at BP and BM
-
-
-
Input current (latchup immunity)
-
-
-
Electrostatic discharge at bus lines
BP, BM, VBAT, WAKE
uESDExt
ESD protection on pins that lead to
ECU external terminals
-
Electrostatic discharge
uESDint
ESD on all other pins
Transient voltage on BP, BM
-
-
Transient voltage on VBAT
-
-
-
Total power dissipation (all supplies
and outputs)
-
-
-
Storage temperature
-
-
Junction temperature
-
-
Package body temperature
-
-
Humidity non-condensing
-
-
Ambient temperature
T
Ambient temperature
Difference of supplies
-
-
VCC current consumption
-
-
VIO current consumption
-
-
Delay STBN high to RxD high with
wake flag set
-
-
go-to STANDBY hold time
-
-
VBUS_DIFF_D0
Differential bus voltage low in
NORMAL mode (Data0)
-
-
VBUS_DIFF_D1
Differential bus voltage high in
NORMAL mode (Data1)
-
-
Supply Voltage
Tamb
ch
ni
VCC - VIO
IIO
-
am
lc s
on A
te G
nt
st
il
-
ca
-
ICC
lv
General Parameters
State Transitions
Te
tSTBN_RxD
tSTANDBY
Transmitter
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Revision 17920-001-10a
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AS8220A
Objective Data Sheet
- Appendix
Table 10. Comparison table
FlexRay
Electrical Physical Layer Specification V2.1 RevB
AS8220A Datasheet
Parameter
Name
Description
VBUS_DIFF
Matching between Data0 and Data1
differential bus voltage in NORMAL
mode
-
-
VBUS_COM_D0
Common mode bus voltage in case of
Data0 in NORMAL mode
-
-
VBUS_COM_D1
Common mode bus voltage in case of
Data1 in NORMAL mode
-
VBUS_COM
Matching between Data0 and Data1
common mode voltage
-
VBUS_DIFF_Idle
Absolute differential bus voltage in
idle mode
uBDTxidle
Absolute value of uBus, while Idle
IBPBMShortMax
IBMBPShortMax
Absolute max current when BP is
shorted to BM
IBPBMShortMax
IBMBPShortMax
Absolute maximum output current
when BP shorted to BM
IBPGNDShortMax
Absolute max current when BP is
shorted to GND
IBPGNDShortMax
Absolute maximum output current
when shorted to GND
IBMGNDShortMax
Absolute max current when BM is
shorted to GND
IBMGNDShortMax
Absolute maximum output current
when shorted to GND
IBP-5VShortMax
Absolute max current when BP is
shorted to -5 V
IBP-5VShortMax
Absolute maximum output current
when shorted to -5V
IBM-5VShortMax
Absolute max current when BM is
shorted to -5 V
IBM-5VShortMax
A Absolute maximum output current
when shorted to -5V
IBP27VShortMax
Absolute max current when BP is
shorted to 27 V
IBPBAT27VShortMax
Absolute maximum output current
when shorted to 27V
IBM27VShortMax
Absolute max current when BM is
shorted to 27 V
IBMBAT27VShortMax
Absolute maximum output current
when shorted to 27V
Absolute max current when BP is
shorted to 48 V
IBPBAT48VShortMax
Absolute maximum output current
when shorted to 48V
IBM48VShortMax
Absolute max current when BM is
shorted to 48 V
IBMBAT48VShortMax
Absolute maximum output current
when shorted to 48V
tTxD_BUS01
Delay time from TxD to BUS positive
edge
dBDTx10
Transmitter delay, negative edge
tTxD_BUS10
Delay time from TxD to BUS negative
edge
dBDTx01
Transmitter delay, positive edge
tTxD_MISMATCH
Delay time from TxD to BUS
mismatch
dTxAsym
Transmitter delay mismatch
| dBDTx10 - dBDTx01 |
tBUS_10
Fall time differential bus voltage
dBusTx10
Fall time differential bus voltage
(80% → 20%)
tBUS_01
Rise time differential bus voltage
dBusTx01
Rise time differential bus voltage
(20% → 80%)
Te
lv
-
-
am
lc s
on A
te G
nt
st
il
ca
ch
ni
IBP48VShortMax
al
id
Symbol
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Revision 17920-001-10a
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AS8220A
Objective Data Sheet
- Appendix
Table 10. Comparison table
FlexRay
Electrical Physical Layer Specification V2.1 RevB
Parameter
Name
Description
tTxEN_BUS_Idle_Acti
Delay time from TxEN to bus active
dBDTxia
Propagation delay idle →active
tTxEN_BUS_Active_Id
Delay time from TxEN to bus idle
dBDTxai
Propagation delay active → idle
tTxEN_MISMATCH
Delay time from TxEN to bus
mismatch
dBDTxDM
| dBDTxia - dBDTxai |
tBGE_BUS_Idle_Activ
Delay time from BGE to bus active
dBDTxia
Propagation delay idle → active
tBGE_BUS_Active_Idl
Delay time from BGE to bus idle
dBDTXai
Propagation delay active → idle
tBUS_Idle_Active
Differential bus voltage transition
time: idle to active
dBusTxia
Transition time idle → active
tBUS_Active_Idle
Differential bus voltage transition
time: active to idle
dBusTxai
Transition time active → idle
tTxEN_timeout
TxEN timeout
-
-
BP, BM input resistance
RCM1, RCM2
Receiver common mode input
resistance
RDIFF
BP, BM differential input resistance
-
-
VBPidle, VBMidle
Idle voltage in NORMAL mode on pin
BP,BM
uBias
Bus bias voltage during BD_Normal
mode
VBPidle_low,
VBMidle_low
Idle voltage in NORMAL mode on pin
BP, BM
uBias
Bus bias voltage during low power
modes
IBPidle
Absolute idle output current on pin BP
-
-
IBMidle
Absolute idle output current on pin
BM
-
-
IBPleak, IBMleak
Absolute leakage current, when not
powered
iBPLeak, iBMLeak
Absolute leakage current, when not
powered
VBUSActiveHigh
Activity detection differential input
voltage high
uBusActiveHigh
Upper receiver threshold for
detecting activity
VBUSActiveLow
Activity detection differential input
voltage low
uBusActiveLow
Lower receiver threshold for
detecting activity
VData1
Data1 detection differential input
voltage
uData1
Receiver threshold for detecting
Data_1
Data0 detection differential input
voltage
uData0
Receiver threshold for detecting
Data_0
VDataErr
Mismatch between Data0 and Data1
differential input voltage
uData
Mismatch of receiver thresholds
tBUS_RxD10
Delay from bus to RxD negative edge
dBDRx10
Receiver delay, negative edge
tBUS_RxD01
Delay from bus to RxD positive edge
dBDRx01
Receiver delay, positive edge
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Receiver
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RBP, RBM
VData0
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AS8220A Datasheet
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AS8220A
Objective Data Sheet
- Appendix
Table 10. Comparison table
FlexRay
Electrical Physical Layer Specification V2.1 RevB
AS8220A Datasheet
Parameter
Name
Description
tBIT
Bit time
-
-
tRxD_ASYM
Delay time from bus to RxD mismatch
dRxAsym
Receiver delay mismatch
| dBDRx10 – dBDRx01 |
tBUSIdleDetection
Idle detection time
dIdleDetection
Filter-time for idle detection
tBUSActivityDetection
Activity detection time
dActivityDetection
Filter-time for activity detection
tBUSIdleReaction
Idle reaction time
dBDRxai
Idle reaction time
tBUSActivityReaction
Activity reaction time
dBDRxia
Activity reaction time
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VCC undervoltage recovery threshold
-
-
VCCTHL
VCC undervoltage detection threshold
uUVCC
Undervoltage detection threshold
VIOTHH
VIO undervoltage recovery threshold
-
-
VIOTHL
VIO undervoltage detection threshold
uUVIO
Undervoltage detection threshold
tUV_DETECT
Detection time for undervoltage at
VCC, VIO
dUVCC, dUVIO
Undervoltage reaction time
tUV_REC
Detection time for undervoltage
recovery at VCC, VIO
-
-
ITHL
Absolute bus current for low current
detection
-
-
ITHH
Absolute bus current for high current
detection
-
-
VSHORT
Differential voltage on BP and BM
for detecting short circuit between bus
lines
-
-
Bus error detection time
-
Detection only required while actively
transmitting a data frame, error
indication to host latest when
transmission stops.
Over temperature threshold
-
-
Over temperature hysteresis
-
-
uVIO-IN-HIGH
Threshold for detecting a digital input
as on logical high
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Bus Error Detection
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VCCTHH
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tBUS_ERROR
Over Temperature
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OTTH
OTTL
Communication Controller Interface
VTxDIH
Threshold for detecting TxD as on
logical high
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Revision 17920-001-10a
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AS8220A
Objective Data Sheet
- Appendix
Table 10. Comparison table
FlexRay
Electrical Physical Layer Specification V2.1 RevB
AS8220A Datasheet
Parameter
Name
Description
VTxDIL
Threshold for detecting TxD as on
logical low
uVIO-IN-LOW
Threshold for detecting a digital input
as on logical low
ITxDIH
TxD high level input current
-
-
ITxDIL
TxD low level input current
-
-
VTxENIH
Threshold for detecting TxEN as on
logical high
uVIO-IN-HIGH
Threshold for detecting a digital input
as on logical high
VTXENIL
Threshold for detecting TxEN as on
logical low
uVIO-IN-LOW
Threshold for detecting a digital input
as on logical low
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Symbol
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-
TxEN low level input current
-
-
RxD high level output voltage
uVIO-OUT-HIGH
Output voltage on a digital output,
when in logical high state
RxD low level output voltage
uVIO-OUT-LOW
Output voltage on a digital output,
when in logical low state
VSTBNIH
Threshold for detecting STBN as on
logical high
uVIO-IN-HIGH
Threshold for detecting a digital input
as on logical high
VSTBNIL
Threshold for detecting STBN as on
logical low
uVIO-IN-LOW
Threshold for detecting a digital input
as on logical low
ISTBNIH
STBN high level input current
-
-
STBN low level input current
-
-
STBN de-bouncing time low power
modes
-
-
STBN de-bouncing time non low
power modes
-
-
VERRNOH
ERRN high level output voltage
uVIO-OUT-HIGH
Output voltage on a digital output,
when in logical high state
VERRNOL
ERRN low level output voltage
uVIO-OUT-LOW
Output voltage on a digital output,
when in logical low state
uVIO-IN-HIGH
Threshold for detecting a digital input
as on logical high
ITxENIL
VRxDOH
VRxDOL
Host Interface
ISTBNIL
tSTBN_DEB_LP
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tSTBN_DEB_NLP
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TxEN high level input current
Bus Guardian Interface
VBGEIH
Threshold for detecting BGE as on
logical high
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Revision 17920-001-10a
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AS8220A
Objective Data Sheet
- Appendix
Table 10. Comparison table
FlexRay
Electrical Physical Layer Specification V2.1 RevB
AS8220A Datasheet
Parameter
Name
Description
VBGEIL
Threshold for detecting BGE as on
logical low
uVIO-IN-LOW
Threshold for detecting a digital input
as on logical low
IBGEIH
BGE high level input current
-
-
IBGEIL
BGE low level input current
-
-
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Symbol
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AS8220A
Objective Data Sheet
- Package Drawings and Markings
10 Package Drawings and Markings
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Figure 19. package Diagram
Max
1.99
0.21
1.78
0.38
0.33
0.20
0.16
5.38
7.90
Symbol
L
L1
N
R
AA
AB
AC
AD
AE
AF
Min
0.63
0º
0.09
6.07
6.07
7.07
8.07
10.07
10.07
Typ
0.75
1.25 REF
See Variations
4º
0.15
6.20
6.20
7.20
8.20
10.20
10.20
Max
0.95
8º
6.33
6.33
7.33
8.33
10.33
10.33
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Table 11. package Dimensions
Symbol
Min
Typ
A
1.73
1.86
A1
0.05
0.13
A2
1.68
1.73
b
0.25
b1
0.25
0.30
C
0.09
C1
0.09
0.15
D
See Variations
E
5.20
5.30
e
0.65 BSC
H
7.65
7.80
Note:
1. Dimensioning and tolerancing conform to ASME Y14.5M-1994.
2. All dimensions are in millimeters, angle is in degrees.
3. N is the total number of terminals.
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AS8220A
Objective Data Sheet
- Ordering Information
11 Ordering Information
Table 12. Ordering Information
Marking
Description
Delivery Form
Package
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Type
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AS8220A
Objective Data Sheet
- Ordering Information
Copyrights
Copyright © 1997-2008, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe.
Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged,
translated, stored, or used without the prior written consent of the copyright owner.
All products and companies mentioned are trademarks or registered trademarks of their respective companies.
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Disclaimer
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Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing
in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding
the information set forth herein or regarding the freedom of the described devices from patent infringement.
austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice.
Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for
current information. This product is intended for use in normal commercial applications. Applications requiring
extended temperature range, unusual environmental requirements, or high reliability applications, such as military,
medical life-support or life-sustaining equipment are specifically not recommended without additional processing by
austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show
deviations from the standard production flow, such as test flow or test location.
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The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However,
austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to
personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or
consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the
technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of
austriamicrosystems AG rendering of technical or other services.
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Contact Information
Headquarters
austriamicrosystems AG
A-8141 Schloss Premstaetten, Austria
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Tel: +43 (0) 3136 500 0
Fax: +43 (0) 3136 525 01
For Sales Offices, Distributors and Representatives, please visit:
http://www.austriamicrosystems.com/contact
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