PHILIPS HEF4040

INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4040B
MSI
12-stage binary counter
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
HEF4040B
MSI
12-stage binary counter
DESCRIPTION
The HEF4040B is a 12-stage binary ripple counter with a
clock input (CP), an overriding asynchronous master reset
input (MR) and twelve fully buffered outputs (O0 to O11).
The counter advances on the HIGH to LOW transition of
CP. A HIGH on MR clears all counter stages and forces all
outputs LOW, independent of CP. Each counter stage is a
static toggle flip-flop. Schmitt-trigger action in the clock
input makes the circuit highly tolerant to slower clock rise
and fall times.
Fig.1 Functional diagram.
PINNING
CP
clock input (HIGH to LOW edge-triggered)
MR
master reset input (active HIGH)
O0 to O11
parallel outputs
APPLICATION INFORMATION
Some examples of applications for the HEF4040B are:
• Frequency dividing circuits
• Time delay circuits
• Control counters
Fig.2 Pinning diagram.
FAMILY DATA, IDD LIMITS category MSI
HEF4040BP(N):
16-lead DIL; plastic
HEF4040BD(F):
16-lead DIL; ceramic (cerdip)
See Family Specifications
(SOT38-1)
(SOT74)
HEF4040BT(D):
16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
January 1995
2
Philips Semiconductors
Product specification
HEF4040B
MSI
12-stage binary counter
Fig.3 Logic diagram.
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL
TYPICAL EXTRAPOLATION
FORMULA
MIN. TYP. MAX.
Propagation delays
CP → O0
HIGH to LOW
5
10
tPHL
15
5
LOW to HIGH
10
tPLH
15
On → On + 1
HIGH to LOW
5
10
tPHL
15
5
LOW to HIGH
10
tPLH
15
MR → On
HIGH to LOW
Output transition times
HIGH to LOW
LOW to HIGH
210
ns
78 ns
+
(0,55 ns/pF) CL
45
90
ns
34 ns
+
(0,23 ns/pF) CL
35
70
ns
27 ns
+
(0,16 ns/pF) CL
85
170
ns
58 ns
+
(0,55 ns/pF) CL
40
80
ns
29 ns
+
(0,23 ns/pF) CL
30
60
ns
22 ns
+
(0,16 ns/pF) CL
35
70
ns
note 1
(0,55 ns/pF) CL
15
30
ns
note 1
(0,23 ns/pF) CL
10
20
ns
note 1
(0,16 ns/pF) CL
35
70
ns
note 1
(0,55 ns/pF) CL
15
30
ns
note 1
(0,23 ns/pF) CL
10
20
ns
note 1
(0,16 ns/pF) CL
90
180
ns
63 ns
+
(0,55 ns/pF) CL
40
80
ns
29 ns
+
(0,23 ns/pF) CL
15
30
60
ns
22 ns
+
(0,16 ns/pF) CL
5
60
120
ns
10 ns
+
(1,0 ns/pF) CL
5
10
tPHL
30
60
ns
9 ns
+
(0,42 ns/pF) CL
15
20
40
ns
6 ns
+
(0,28 ns/pF) CL
5
60
120
ns
10 ns
+
(1,0 ns/pF) CL
30
60
ns
9 ns
+
(0,42 ns/pF) CL
20
40
ns
6 ns
+
(0,28 ns/pF) CL
10
10
tTHL
tTLH
15
January 1995
105
3
Philips Semiconductors
Product specification
HEF4040B
MSI
12-stage binary counter
VDD
V
Minimum clock
pulse width; HIGH
5
25
ns
15
ns
20
10
ns
5
40
20
ns
10
tWCPH
tWMRH
30
15
ns
15
20
10
ns
5
40
20
ns
30
15
ns
15
20
10
ns
5
10
20
MHz
15
30
MHz
25
50
MHz
10
Maximum clock
pulse frequency
50
30
10
Recovery time
for MR
TYPICAL EXTRAPOLATION
FORMULA
MIN. TYP. MAX.
15
Minimum MR
pulse width; HIGH
SYMBOL
10
15
tRMR
fmax
see also waveforms
Fig.4
Note
1. For other loads than 50 pF at the nth output, use the slope given.
VDD
V
Dynamic power
dissipation per
package (P)
TYPICAL FORMULA FOR P (µW)
5
400 fi + ∑ (foCL) × VDD2
10
2 000 fi + ∑ (foCL) × VDD2
fi = input freq. (MHz)
15
5 200 fi + ∑ (foCL) ×
fo = output freq. (MHz)
VDD2
where
CL = load cap. (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
4
Philips Semiconductors
Product specification
HEF4040B
MSI
12-stage binary counter
Fig.4
Waveforms showing propagation delays for MR to On and CP to O0, minimum MR and CP pulse widths.
January 1995
5
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