INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4024B MSI 7-stage binary counter Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification HEF4024B MSI 7-stage binary counter DESCRIPTION The HEF4024B is a 7-stage binary ripple counter with a clock input (CP), and overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs (O0 to O6). The counter advances on the HIGH to LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of CP. Each counter stage is a static toggle flip-flop. Fig.1 Functional diagram. PINNING CP clock input (HIGH to LOW triggered) MR master reset input O0 to O6 buffered parallel outputs APPLICATION INFORMATION Some examples of applications for the HEF4024B are: • Frequency dividers • Time delay circuits Fig.2 Pinning diagram. FAMILY DATA, IDD LIMITS category MSI See Family Specifications HEF4024BP(N): 14-lead DIL; plastic (SOT27-1) HEF4024BD(F): 14-lead DIL; ceramic (cerdip) (SOT73) HEF4024BT(D): 14-lead SO; plastic (SOT108-1) ( ): Package Designator North America January 1995 2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Philips Semiconductors 7-stage binary counter January 1995 Fig.3 Logic diagram. 3 Product specification HEF4024B MSI Philips Semiconductors Product specification HEF4024B MSI 7-stage binary counter AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns; see also waveforms Fig.4 VDD V SYMBOL MIN. TYPICAL EXTRAPOLATION FORMULA TYP. MAX. 100 200 ns 73 ns + (0,55 ns/pF) CL 40 75 ns 29 ns + (0,23 ns/pF) CL 25 50 ns 17 ns + (0,16 ns/pF) CL 105 210 ns 78 ns + (0,55 ns/pF) CL 45 85 ns 34 ns + (0,23 ns/pF) CL 30 60 ns 22 ns + (0,16 ns/pF) CL 60 120 ns 33 ns + (0,55 ns/pF) CL 25 50 ns 14 ns + (0,23 ns/pF) CL 20 40 ns 12 ns + (0,16 ns/pF) CL Propagation delays CP → O0 HIGH to LOW 5 10 tPHL 15 5 LOW to HIGH 10 tPLH 15 On → On + 1 HIGH to LOW 5 10 tPHL 15 50 100 ns 23 ns + (0,55 ns/pF) CL 20 40 ns 9 ns + (0,23 ns/pF) CL 15 30 ns 7 ns + (0,16 ns/pF) CL 120 240 ns 93 ns + (0,55 ns/pF) CL 45 90 ns 34 ns + (0,23 ns/pF) CL 15 30 60 ns 22 ns + (0,16 ns/pF) CL 5 60 120 ns 10 ns + (1,0 ns/pF) CL 5 LOW to HIGH 10 tPLH 15 MR → On HIGH to LOW Output transition times HIGH to LOW LOW to HIGH 5 10 tPHL 30 60 ns 9 ns + (0,42 ns/pF) CL 15 20 40 ns 6 ns + (0,28 ns/pF) CL 5 60 120 ns 10 ns + (1,0 ns/pF) CL 30 60 ns 9 ns + (0,42 ns/pF) CL 20 40 ns 6 ns + (0,28 ns/pF) CL 10 10 tTHL tTLH 15 Minimum clock pulse width; HIGH Minimum MR pulse width; HIGH 5 10 60 tWCPH 30 ns 30 15 ns 15 20 10 ns 5 80 40 ns 10 tWMRH 35 20 ns 15 25 15 ns Recovery time 5 20 10 ns for MR 10 Maximum clock pulse frequency 15 5 ns 15 5 ns 5 5 10 MHz 13 25 MHz 18 35 MHz 10 15 January 1995 tRMR 15 fmax 4 Philips Semiconductors Product specification HEF4024B MSI 7-stage binary counter VDD V Dynamic power dissipation per package (P) TYPICAL FORMULA FOR P (µW) 5 500 fi + ∑ (foCL) × VDD2 10 2100 fi + ∑ (foCL) × VDD 2 15 5200 fi + ∑ (foCL) × VDD 2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load cap. (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) Fig.4 Waveforms showing propagation delays for MR to On and CP to O0, minimum MR and CP pulse widths and recovery time for MR. January 1995 5