Philips Semiconductors Advanced BiCMOS Products Product specification Dual 10-bit bus interface latch (3-State) MB2841 • Output capability: +64mA/–32mA • Latch-up protection exceeds 500mA per FEATURES • High speed parallel latches • Live insertion/extraction permitted • Extra data width for wide address/data The MB2841 consists of two sets of ten D-type latches with 3-State outputs. The flip-flops appear transparent to the data when Latch Enable (nLE) is High. This allows asynchronous operation, as the output transition follows the data in transition. On the nLE High-to-Low transition, the data that meets the setup and hold time is latched. Jedec JC40.2 Std 17 • ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model paths or buses carrying parity • Power-up 3-State • Power-up reset • Ideal where high speed, light loading, or DESCRIPTION Data appears on the bus when the Output Enable (nOE) is Low. When nOE is High the output is in the High-impedance state. The MB2841 Bus interface register is designed to provide extra data width for wider data/address paths of buses carrying parity. increased fan-in are required with MOS microprocessors QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS Tamb = 25°C; GND = 0V TYPICAL UNIT tPLH tPHL Propagation delay nDx to nQx CL = 50pF; VCC = 5V 3.5 ns CIN Input capacitance VI = 0V or VCC 4 pF COUT Output capacitance VO = 0V or VCC; 3-State 7 pF ICCZ Total supply current Outputs disabled; VCC = 5.5V 120 µA ORDERING INFORMATION PACKAGES TEMPERATURE RANGE ORDER CODE DRAWING NUMBER 52-pin Plastic Quad Flat Pack (PQFP) -40°C to +85°C MB2841BB 1418B Vcc 1D3 1D2 GND 1D1 1D0 1LE LOGIC SYMBOL 1OE 1Q0 1Q1 1Q2 1Q3 Vcc PIN CONFIGURATION 45 52 51 50 49 48 47 46 45 44 43 42 È È È 1Q4 1 39 1D4 1Q5 2 38 1D5 1Q6 3 37 1D6 GND 4 36 1D7 1Q7 5 35 1D8 1Q8 6 1Q9 7 2Q0 8 32 2D1 2Q1 9 31 2D2 MB2841 52-pin PQFP 2Q3 11 29 2D3 2Q5 13 27 2D5 2D6 2D7 2D8 26 2D9 2OE 2Q9 2Q8 GND 2Q7 Vcc 2Q6 21 22 23 24 25 Vcc 28 2D4 2LE 2Q4 12 August 24, 1993 46 1LE 47 1OE 41 39 38 37 36 35 34 1D7 1D8 1D9 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 1Q9 33 2D0 30 GND 17 18 19 20 42 1D0 1D1 1D2 1D3 1D4 1D5 1D6 34 1D9 2Q2 10 14 15 16 44 41 40 48 49 50 51 1 2 3 5 6 7 33 32 31 29 28 27 25 24 23 22 2D0 2D1 2D2 2D3 2D4 2D5 2D6 21 2LE 20 2OE 2D7 2D8 2D9 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2Q9 8 1 9 10 11 12 13 15 16 18 19 853-1668 10619 Philips Semiconductors Advanced BiCMOS Products Product specification Dual 10-bit bus interface latch (3-State) MB2841 PIN DESCRIPTION PIN NUMBER SYMBOL FUNCTION 45, 44, 42, 41, 39, 38, 37, 36, 35, 34, 33, 32, 31, 29, 28, 27, 25, 24, 23, 22 1D0 – 1D9 2D0 – 2D9 Data inputs 48, 49, 50, 51, 1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15, 16, 18, 19 1Q0 – 1Q9 2Q0 – 2Q9 Data outputs 47, 20 1OE, 2OE Output enable inputs (active-Low) Latch enable inputs (active rising edge) 46, 21 1LE, 2LE 4, 17, 30, 43 GND Ground (0V) 14, 26, 40, 52 VCC Positive supply voltage LOGIC SYMBOL (IEEE/IEC) 47 46 45 20 EN 21 C1 EN C1 48 33 44 49 32 9 42 50 31 10 41 51 29 11 39 1 28 12 38 2 27 13 37 3 25 15 36 5 24 16 35 6 23 18 34 7 22 19 1D 1D 8 FUNCTION TABLE INPUTS H = h = L = l = ↓ = NC= X = Z = OUTPUTS OPERATING MODE nOE nLE nDx nQ0 – nQ9 L L H H L H L H Transparent L L ↓ ↓ l h L H Latched H X X Z High impedance L L X NC High voltage level High voltage level one set-up time prior to the High-to-Low LE transition Low voltage level Low voltage level one set-up time prior to the High-to-Low LE transition High-to-Low LE transition No change Don’t care High impedance “off” state August 24, 1993 2 Hold Philips Semiconductors Advanced BiCMOS Products Product specification Dual 10-bit bus interface latch (3-State) MB2841 LOGIC DIAGRAM nD0 nD1 D L nD2 D Q L nD3 D Q nD4 D L Q L nD5 D Q nD6 D L Q L nD7 D Q L nD8 D Q L nD9 D Q D L Q L Q nLE nOE nQ0 nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7 nQ8 nQ9 ABSOLUTE MAXIMUM RATINGS1, 2 PARAMETER SYMBOL VCC CONDITIONS RATING UNIT –0.5 to +7.0 V –18 mA –1.2 to +7.0 V VO < 0 –50 mA output in Off or High state –0.5 to +5.5 V output in Low state 128 mA –65 to 150 °C DC supply voltage IIK DC input diode current VI DC input voltage3 IOK DC output diode current VI < 0 voltage3 VOUT DC output IOUT DC output current Tstg Storage temperature range NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER LIMITS DC supply voltage UNIT Min Max 4.5 5.5 V 0 VCC V VI Input voltage VIH High-level input voltage VIL Low-level Input voltage 0.8 V IOH High-level output current –32 mA IOL Low-level output current 64 mA 0 5 ns/V –40 +85 °C ∆t/∆v Input transition rise or fall rate Tamb Operating free-air temperature range August 24, 1993 2.0 3 V Philips Semiconductors Advanced BiCMOS Products Product specification Dual 10-bit bus interface latch (3-State) MB2841 DC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN VIK VOH Input clamp voltage High-level output voltage Tamb = –40°C to +85°C Tamb = +25°C VCC = 4.5V; IIK = –18mA TYP MAX –0.9 –1.2 MIN UNIT MAX –1.2 V VCC = 4.5V; IOH = –3mA; VI = VIL or VIH 2.5 2.9 2.5 V VCC = 5.0V; IOH = –3mA; VI = VIL or VIH 3.0 3.4 3.0 V VCC = 4.5V; IOH = –32mA; VI = VIL or VIH 2.0 2.4 2.0 V VOL Low-level output voltage VCC = 4.5V; IOL = 64mA; VI = VIL or VIH 0.42 0.55 0.55 V VRST Power-up output voltageNO TAG VCC = 5.5V; IO = 1mA; VI = GND or VCC 0.13 0.55 0.55 V Input leakage current VCC = 5.5V; VI = GND or 5.5V ±0.01 ±1.0 ±1.0 µA Power-off leakage current VCC = 0.0V; VO or VI ≤ 4.5V ±5.0 ±100 ±100 µA Power-up/down 3-State output current4 VCC = 2.1V; VO = 0.5V; VI = GND or VCC; V OE = Don’t care ±5.0 ±50 ±50 µA IOZH 3-State output High current VCC = 5.5V; VO = 2.7V; VI = VIL or VIH 5.0 50 50 µA IOZL 3-State output Low current VCC = 5.5V; VO = 0.5V; VI = VIL or VIH –5.0 –50 –50 µA ICEX Output High leakage current VCC = 5.5V; VO = 5.5V; VI = GND or VCC 5.0 50 50 µA Output current1 VCC = 5.5V; VO = 2.5V –70 –180 –180 mA VCC = 5.5V; Outputs High, VI = GND or VCC 120 250 250 µA VCC = 5.5V; Outputs Low, VI = GND or VCC 56 76 76 mA VCC = 5.5V; Outputs 3-State; VI = GND or VCC 120 250 250 µA VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND 0.5 1.5 1.5 mA II IOFF IPU/PD IO ICCH ICCL Quiescent supply current ICCZ ∆ICC Additional supply current per input pin2 –50 –50 NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V. 3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 4. This parameter is valid for any VCC between 0V and 2.1V with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V ± 10% a transition time of up to 100µsec is permitted. AC CHARACTERISTICS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER Tamb = -40 to +85oC VCC = +5.0V ±0.5V Tamb = +25oC VCC = +5.0V WAVEFORM UNIT MIN TYP MAX MIN MAX 2 1.5 1.7 3.1 3.5 4.4 4.7 1.5 1.7 5.0 5.3 ns Propagation delay nLE to nQx 1 2.4 2.9 4.2 4.6 5.7 6.0 2.4 2.9 6.5 6.7 ns tPZH tPZL Output enable time to High and Low level 4 5 1.3 2.3 3.1 4.0 4.2 5.2 1.3 2.3 4.9 5.9 ns tPHZ tPLZ Output disable time from High and Low level 4 5 1.0 1.5 3.3 3.2 4.6 4.5 1.0 1.5 5.1 5.0 ns tPLH tPHL Propagation delay nDx to nQx tPLH tPHL August 24, 1993 4 Philips Semiconductors Advanced BiCMOS Products Product specification Dual 10-bit bus interface latch (3-State) MB2841 AC SETUP REQUIREMENTS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER Tamb = -40 to +85oC VCC = +5.0V ±0.5V Tamb = +25oC VCC = +5.0V WAVEFORM Min Typ Max Min UNIT Max ts(H) ts(L) Setup time, High or Low nDx to nLE 3 2.0 1.5 0.8 0.4 2.0 1.5 ns th(H) th(L) Hold time, High or Low nDx to nLE 3 0.5 0.5 –0.3 –0.7 0.5 0.5 ns tw(H) nLE pulse width High 1 2.9 1.9 2.9 ns AC WAVEFORMS VM = 1.5V, VIN = GND to 3.0V nDx INPUT nLE VM VM VM VM VM tPLH tw(H) tPHL tPHL tPLH nQx VM VM ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉ Waveform 1. Propagation Delay, Latch Enable Input to Output, and Enable Pulse Width nDx VM ts(H) VM VM nQx OUTPUT Waveform 2. Propagation Delay for Data to Outputs VM VM th(H) VM ts(L) th(L) nLE VM VM Waveform 3. Data Setup and Hold Times nOE VM tPZH nQx nOE VM tPHZ VM VM VM tPZL VOH –0.3V nQx tPLZ VM VOL +0.3V 0V Waveform 4. 3–State Output Enable Time to High Level and Output Disable Time from High Level Waveform 5. 3–State Output Enable Time to Low Level and Output Disable Time from Low Level NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. August 24, 1993 5 Philips Semiconductors Advanced BiCMOS Products Product specification Dual 10-bit bus interface latch (3-State) MB2841 TEST CIRCUIT AND WAVEFORM VCC 7.0V VOUT VIN PULSE GENERATOR tW 90% VM NEGATIVE PULSE RL 10% 0V tTHL (tF) CL tTLH (tR) tTLH (tR) RL tTHL (tF) 90% POSITIVE PULSE Test Circuit for 3-State Outputs AMP (V) 90% VM VM 10% 10% tW SWITCH POSITION TEST SWITCH tPLZ closed tPZL closed All other open 0V VM = 1.5V Input Pulse Definition INPUT PULSE REQUIREMENTS DEFINITIONS FAMILY RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. MB RT = Termination resistance should be equal to ZOUT of pulse generators. August 24, 1993 AMP (V) VM 10% D.U.T RT 90% 6 Amplitude Rep. Rate tW tR tF 3.0V 1MHz 500ns 2.5ns 2.5ns Philips Semiconductors Advanced BiCMOS Products Product specification Dual 10-bit bus interface latch (3-State) MB2841 tPLH vs Temperature (Tamb) CL = 50pF, 1 Output Switching nDx to nQx 6 Adjustment of tPLH for Load Capacitance and # of Outputs Switching nDx to nQx 5 4 5 MAX 20 switching 3 10 switching 2 1 switching Offset in ns ns 4 4.5VCC 5.5VCC 3 2 1 MIN 0 1 –1 0 –2 –55 –35 –15 5 25 45 65 85 105 0 125 50 °C 150 200 pF tPHL vs Temperature (Tamb) CL = 50pF, 1 Output Switching nDx to nQx 7 100 Adjustment of tPHL for Load Capacitance and # of Outputs Switching nDx to nQx 5 6 4 5 Offset in ns MAX 4 2 MIN ns 3 4.5VCC 5.5VCC 3 20 switching 10 switching 2 1 switching 1 0 1 –1 0 –2 –55 –35 –15 5 25 45 65 85 105 125 0 50 °C 200 Adjustment of tPLH for Load Capacitance and # of Outputs Switching nLE to nQx 5 7 4 Offset in ns MAX 6 5 3 MIN ns 4 4.5VCC 5.5VCC 3 20 switching 10 switching 2 1 switching 1 0 2 –1 1 –55 150 pF tPLH vs Temperature (Tamb) CL = 50pF, 1 Output Switching nLE to nQx 8 100 –2 –35 –15 5 25 45 65 85 105 125 0 °C August 24, 1993 50 100 pF 7 150 200 Philips Semiconductors Advanced BiCMOS Products Product specification Dual 10-bit bus interface latch (3-State) MB2841 tPHL vs Temperature (Tamb) CL = 50pF, 1 Output Switching nLE to nQx 8 Adjustment of tPHL for Load Capacitance and # of Outputs Switching nLE to nQx 5 4 7 MAX 3 20 switching 10 switching 2 1 switching 5 Offset in ns ns 6 4.5VCC 5.5VCC 4 1 0 MIN 3 –1 2 –2 –55 –35 –15 5 25 45 65 85 105 0 125 50 °C 150 200 pF tPZH vs Temperature (Tamb) CL = 50pF, 1 Output Switching nOE to nQx 6 100 Adjustment of tPZH for Load Capacitance and # of Outputs Switching nOE to nQx 5 4 5 MAX 20 switching 3 4 Offset in ns 10 switching ns 4.5VCC 3 5.5VCC 2 2 1 switching 1 0 MIN 1 –1 0 –2 –55 –35 –15 5 25 45 65 85 105 0 125 50 °C 150 200 pF tPZL vs Temperature (Tamb) CL = 50pF, 1 Output Switching nOE to nQx 7 100 5 Adjustment of tPZL for Load Capacitance and # of Outputs Switching nOE to nQx 4 6 20 switching 10 switching MAX 3 Offset in ns ns 5 4.5VCC 4 5.5VCC 3 1 switching 2 1 0 MIN 2 –1 1 –55 –2 –35 –15 5 25 45 65 85 105 0 125 °C August 24, 1993 50 100 pF 8 150 200 Philips Semiconductors Advanced BiCMOS Products Product specification Dual 10-bit bus interface latch (3-State) MB2841 tPHZ vs Temperature (Tamb) CL = 50pF, 1 Output Switching nOE to nQx 6 Adjustment of tPHZ for Load Capacitance and # of Outputs Switching nOE to nQx 8 20 switching 10 switching 1 switching 7 MAX 5 6 5 Offset in ns 4 ns 4.5VCC 3 5.5VCC 2 4 3 2 1 0 MIN 1 –1 –2 0 –55 –3 –35 –15 5 25 45 65 85 105 125 0 50 °C 6 5 MAX 2 Offset in ns ns 4.5VCC 5.5VCC 3 20 switching 10 switching 1 switching 4 4 MIN 3 2 1 0 1 –1 0 –2 –35 –15 5 25 45 65 85 105 125 0 50 °C 100 150 200 pF tTLH vs Temperature (Tamb) CL = 50pF, 1 Output Switching 4 Adjustment of tTLH for Load Capacitance and # of Outputs Switching 9 7 20 switching 10 switching 1 switching 3 Offset in ns 5 ns 200 Adjustment of tPLZ for Load Capacitance and # of Outputs Switching nOE to nQx 5 –55 150 pF tPLZ vs Temperature (Tamb) CL = 50pF, 1 Output Switching nOE to nQx 6 100 4.5VCC 2 5.5VCC 3 1 1 –1 0 –55 –3 –35 –15 5 25 45 65 85 105 0 125 °C August 24, 1993 50 100 pF 9 150 200 Philips Semiconductors Advanced BiCMOS Products Product specification Dual 10-bit bus interface latch (3-State) MB2841 tTHL vs Temperature (Tamb) CL = 50pF, 1 Output Switching 4 Adjustment of tTHL for Load Capacitance and # of Outputs Switching 5 4 20 switching 3 Offset in ns ns 3 4.5VCC 2 5.5VCC 10 switching 1 switching 2 1 0 1 –1 0 –2 –55 –35 –15 5 25 45 65 85 105 0 125 50 °C 200 VOHP and VOLV vs Load Capacitance VCC = 5V, VIN = 0 to 3V 6 3.5 5 125°C 25°C –55°C 3.0 4 125°C 25°C –55°C 3 Volts 2.5 Volts 150 pF VOHV and VOLP vs Load Capacitance VCC = 5V, VIN = 0 to 3V 4.0 100 2.0 1.5 2 1 0 125°C 25°C –55°C 1.0 0.5 125°C 25°C –55°C –1 –2 0 –3 0 50 100 150 0 200 pF August 24, 1993 50 100 pF 10 150 200