Philips Semiconductors Product specification 8-bit bus interface latch with set and reset (3-State) FEATURES 74ABT845 DESCRIPTION • High speed parallel latches • Ideal where high speed, light loading, or increased fan-in are The 74ABT845 consists of eight D-type latches with 3-State outputs. In addition to the LE, OE, MR and PRE pins, the 74ABT845 has two additional OE pins, making a total of three Output Enable (OE0, OE1, OE2) pins. The multiple Output enables allow multiuser control of the interface, e.g., CS, DMA, and RD/WR. required with MOS microprocessors • Broadside pinout • Output capability: +64mA/–32mA • Power-up 3-State • Power-up reset • Latch-up protection exceeds 500mA per Jedec Std 17 • ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model QUICK REFERENCE DATA SYMBOL CONDITIONS Tamb = 25°C; GND = 0V PARAMETER TYPICAL UNIT 5.4 ns tPLH tPHL Propagation delay Dn to Qn CL = 50pF; VCC = 5V CIN Input capacitance VI = 0V or VCC 4 pF COUT Output capacitance Outputs disabled; VO = 0V or VCC 7 pF ICCZ Total supply current Outputs disabled; VCC = 5.5V 500 nA ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 24-Pin Plastic DIP –40°C to +85°C 74ABT845 N 74ABT845 N SOT222-1 24-Pin plastic SO –40°C to +85°C 74ABT845 D 74ABT845 D SOT137-1 24-Pin Plastic SSOP Type II –40°C to +85°C 74ABT845 DB 74ABT845 DB SOT340-1 24-Pin Plastic TSSOP Type I –40°C to +85°C 74ABT845 PW 74ABT845PW DH SOT355-1 PIN CONFIGURATION PIN DESCRIPTION PIN NUMBER SYMBOL FUNCTION 1, 2, 23 OE0 – OE2 3, 4, 5, 6, 7, 8, 9, 10 D0-D7 Data inputs Data outputs Output enable inputs (active-Low) OE0 1 24 VCC OE1 2 23 OE2 D0 3 22 Q0 D1 4 21 Q1 5 20 Q2 22, 21, 20, 19,18, 17, 16, 15 Q0-Q7 D2 D3 6 19 Q3 11 MR Master reset input (active-Low) D4 7 18 Q4 13 LE D5 8 17 Q5 Latch enable input (active-High) D6 9 16 Q6 14 PRE Preset input (active-Low) 15 Q7 12 GND Ground (0V) 24 VCC Positive supply voltage D7 10 MR 11 14 PRE GND 12 13 LE TOP VIEW SA00258 1995 Sep 06 1 853-1703 15702 Philips Semiconductors Product specification 8-bit bus interface latch with set and reset (3-State) LOGIC SYMBOL (IEEE/IEC) 1 74ABT845 LOGIC SYMBOL & 2 3 EN 4 5 6 7 8 9 10 23 14 11 13 S2 D0 D1 D2 D3 D4 D5 D6 D7 R 13 LE C1 14 PRE 11 MR 22 1 OE0 4 21 2 OE1 5 20 23 6 19 7 18 8 17 9 16 10 15 3 1D 2 OE2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 22 21 20 19 18 17 16 15 SA00260 SA00259 FUNCTION TABLE OUTPU TS INPUTS OE n PR E MR LE Dn Qn L L X X X H Preset L H L X X L Clear L L H H H H H H L H L H Transparent L L H H H H ↓ ↓ l h L H Latched High impedance H X X X X Z L H H L X NC H = High voltage level h = High voltage level one set-up time prior to the High-to-Low LE transition L = Low voltage level l = Low voltage level one set-up time prior to the High-to-Low LE transition NC= No change X = Don’t care Z = High impedance “off” state ↓ = High-to-Low transition OPERATING MODE Hold LOGIC DIAGRAM D0 D1 D2 D3 D4 D5 D6 3 4 5 6 7 8 9 D7 10 14 PRE P P D L P D C Q L P D C Q L C P D Q L P D C Q L P D C Q L P D C Q L D C Q L C Q 11 MR 13 LE 1 OE0 2 OE1 OE2 23 22 Q0 21 Q1 20 19 Q2 Q3 18 Q4 17 Q5 16 Q6 15 Q7 SA00261 1995 Sep 06 2 Philips Semiconductors Product specification 8-bit bus interface latch with set and reset (3-State) 74ABT845 ABSOLUTE MAXIMUM RATINGS1,2 SYMBOL VCC IIK PARAMETER CONDITIONS RATING UNIT –0.5 to +7.0 V –18 mA –1.2 to +7.0 V VO < 0 –50 mA output in Off or High state –0.5 to +5.5 V output in Low state 128 mA –65 to 150 °C DC supply voltage DC input diode current VI < 0 voltage3 VI DC input IOK DC output diode current voltage3 VOUT DC output IOUT DC output current Tstg Storage temperature range NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER LIMITS DC supply voltage UNIT Min Max 4.5 5.5 V 0 VCC V VI Input voltage VIH High-level input voltage VIL Low-level input voltage 0.8 V IOH High-level output current –32 mA IOL Low-level output current 64 mA 0 5 ns/V –40 +85 °C ∆t/∆v Input transition rise or fall rate Tamb Operating free-air temperature range 1995 Sep 06 2.0 3 V Philips Semiconductors Product specification 8-bit bus interface latch with set and reset (3-State) 74ABT845 DC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITIONS Min VIK VOH Input clamp voltage High–level output voltage Tamb = –40°C to +85°C Tamb = +25°C VCC = 4.5V; IIK = –18mA Typ Max –0.9 –1.2 Min UNIT Max –1.2 V VCC = 4.5V; IOH = –3mA; VI = VIL or VIH 2.5 2.9 2.5 V VCC = 5.0V; IOH = –3mA; VI = VIL or VIH 3.0 3.4 3.0 V VCC = 4.5V; IOH = –32mA; VI = VIL or VIH 2.0 2.4 2.0 V VOL Low–level output voltage VCC = 4.5V; IOL = 64mA; VI = VIL or VIH 0.42 0.55 0.55 V VRST Power-up output low voltage3 VCC = 5.5V; IO = 1mA; VI = GND or VCC 0.13 0.55 0.55 V II Input leakage current VCC = 5.5V; VI = GND or 5.5V ±0.01 ±1.0 ±1.0 µA Power-off leakage current VCC = 0.0V; VO or VI ≤ 4.5V ±5.0 ±100 ±100 µA Power-up/down 3-state output current4 VCC = 2.1V; VO = 0.5V; V OE = VCC; VI = GND or VCC ±5.0 ±50 ±50 µA IOZH 3-State output High current VCC = 5.5V; VO = 2.7V; VI = VIL or VIH 5.0 50 50 µA IOZL 3-State output Low current VCC = 5.5V; VO = 0.5V; VI = VIL or VIH –5.0 –50 –50 µA ICEX Output High leakage current VCC = 5.5V; VO = 5.5V; VI = GND or VCC 5.0 50 50 µA –80 –180 –180 mA VCC = 5.5V; Outputs High, VI = GND or VCC 0.5 250 250 µA VCC = 5.5V; Outputs Low, VI = GND or VCC 24 30 30 mA VCC = 5.5V; Outputs 3-State; VI = GND or VCC 0.5 250 250 µA VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND 0.5 1.5 1.5 mA IOFF IPU/PD IO Output current1 ICCH ICCL Quiescent supply current ICCZ ∆ICC Additional supply current per input pin2 VCC = 5.5V; VO = 2.5V –50 –50 NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V. 3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 4. This parameter is valid for any VCC between 0V and 2.1V with a transition time of up to 10msec. For VCC = 2.1V to VCC = 5V 10%, a transition time of up to 100µsec is permitted. 1995 Sep 06 4 Philips Semiconductors Product specification 8-bit bus interface latch with set and reset (3-State) 74ABT845 AC CHARACTERISTICS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER Tamb = -40 to +85oC VCC = +5.0V ±0.5V Tamb = +25oC VCC = +5.0V WAVEFORM Min Typ Max Min Max UNIT tPLH tPHL Propagation delay Dn to Qn 1 1.0 2.2 3.9 5.4 5.4 6.8 1.0 2.2 6.2 7.8 ns tPLH tPHL Propagation delay LE to Qn 2 2.0 2.8 5.1 6.4 6.6 7.9 2.0 2.8 7.5 8.9 ns tPLH tPHL Propagation delay PRE to Qn 1 2.2 3.0 4.9 5.3 6.6 6.8 2.2 3.0 7.8 7.4 ns tPLH tPHL Propagation delay MR to Qn 1 2.4 3.1 4.9 5.9 6.4 7.3 2.4 3.1 7.3 8.5 ns tPZH tPZL Output enable time OEn to Qn 4 5 1.0 2.0 3.8 4.7 5.4 6.1 1.0 2.0 6.3 6.7 ns tPHZ tPLZ Output disable time OEn to Qn 4 5 1.9 2.2 4.6 4.7 6.2 6.4 1.9 2.2 7.2 7.0 ns AC SETUP REQUIREMENTS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER WAVEFORM +25oC Tamb = VCC = +5.0V Tamb = -40 to +85oC VCC = +5.0V ±0.5V Min Typ Min UNIT ts(H) ts(L) Setup time, High or Low Dn to LE 3 2.8 3.5 1.0 1.4 2.8 3.5 ns th(H) th(L) Hold time, High or Low Dn to LE 3 1.0 1.0 –1.2 –0.6 1.0 1.0 ns tw(H) LE pulse width, High 3 3.0 1.5 3.0 ns tw(L) PRE pulse width, Low 6 3.5 2.0 3.5 ns tw(L) MR pulse width, Low 6 2.8 1.3 2.8 ns trec PRE recovery time 6 3.0 1.4 3.0 ns trec MR recovery time 6 3.4 1.6 3.4 ns 1995 Sep 06 5 Philips Semiconductors Product specification 8-bit bus interface latch with set and reset (3-State) 74ABT845 AC WAVEFORMS NOTE: For all waveforms, VM = 1.5V. Dn PRE VM VM MR, Dn LE tPLH Qn VM VM tPHL VM tPLH VM tPHL Qn VM VM SA00254 SA00255 Waveform 1. Propagation Delay, Data to Output, Preset to Output, and Master Reset to Output Waveform 2. Propagation Delay, Latch Enable to Output ÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉ VM Dn VM ts(H) VM th(H) VM ts(L) OE tw(H) VM LE VM VM th(L) VM tPZH VM Qn tPHZ VOH–0.3V VM 0V NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. SA00256 SA00066 Waveform 3. Data Setup and Hold Times and Latch Enable Pulse Width OE VM PRE, MR VM tPZL Qn Waveform 4. 3-State Output Enable Time to High Level and Output Disable Time from High Level VM tw(L) tPLZ LE VM VM tREC VM VOL +0.3V VOL Qn SA00109 Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level Qn SA00257 Waveform 6. Master Reset and Preset Pulse Width and Master Reset and Preset to Latch Enable Recovery Time 1995 Sep 06 6 Philips Semiconductors Product specification 8-bit bus interface latch with set and reset (3-State) 74ABT845 TEST CIRCUIT AND WAVEFORM VCC 7.0V PULSE GENERATOR VIN tW 90% VOUT VM NEGATIVE PULSE CL 10% 0V RL tTHL (tF) tTLH (tR) tTLH (tR) tTHL (tF) 90% POSITIVE PULSE Test Circuit for 3-State Outputs AMP (V) 90% VM VM 10% 10% tW SWITCH POSITION TEST SWITCH tPLZ closed tPZL closed All other open AMP (V) VM 10% RL D.U.T. RT 90% 0V VM = 1.5V Input Pulse Definition INPUT PULSE REQUIREMENTS DEFINITIONS FAMILY RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. 74ABT Amplitude Rep. Rate tW tR tF 3.0V 1MHz 500ns 2.5ns 2.5ns SA00012 1995 Sep 06 7