74AUP1G57 Low-power configurable multiple function gate Rev. 01. — 16 January 2006 Preliminary data sheet 1. General description The 74AUP1G57 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74AUP1G57 provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND, NOR, XNOR, inverter and buffer. All inputs can be connected to VCC or GND. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. The inputs switch at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT− is defined as the input hysteresis voltage VH. 2. Features ■ Wide supply voltage range from 0.8 V to 3.6 V ■ High noise immunity ■ ESD protection: ◆ HBM JESD22-A114-C Class 3A. Exceeds 5000 V ◆ MM JESD22-A115-A exceeds 200 V ◆ CDM JESD22-C101-C exceeds 1000 V ■ Low static power consumption; ICC = 0.9 µA (maximum) ■ Latch-up performance exceeds 100 mA per JESD 78 Class II ■ Inputs accept voltages up to 3.6 V ■ Low noise overshoot and undershoot < 10 % of VCC ■ IOFF circuitry provides partial Power-down mode operation ■ Multiple package options ■ Specified from −40 °C to +85 °C and −40 °C to +125 °C 74AUP1G57 Philips Semiconductors Low power configurable multiple function gate 3. Quick reference data Table 1: Quick reference data GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3 ns. Symbol Parameter tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay A, B and C to Y Conditions Min Typ Max Unit CL = 5 pF; RL = 1 MΩ; VCC = 0.8 V - 22.6 - ns CL = 5 pF; RL = 1 MΩ; VCC = 1.1 V to 1.3 V 2.8 6.5 12.6 ns CL = 5 pF; RL = 1 MΩ; VCC = 1.4 V to 1.6 V 2.2 4.6 7.6 ns CL = 5 pF; RL = 1 MΩ; VCC = 1.65 V to 1.95 V 2.1 3.9 6.2 ns CL = 5 pF; RL = 1 MΩ; VCC = 2.3 V to 2.7 V 2.0 3.1 4.5 ns CL = 5 pF; RL = 1 MΩ; VCC = 3.0 V to 3.6 V 1.8 2.8 3.9 ns input capacitance CI power dissipation capacitance CPD - 1.1 - pF VCC = 1.8 V; f = 1 MHz [1] [2] - 3.4 - pF VCC = 3.3 V; f = 1 MHz [1] [2] - 4.5 - pF [1] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. [2] The condition is VI = GND to VCC. 4. Ordering information Table 2: Ordering information Type number Package Temperature range Name Description Version 74AUP1G57GW −40 °C to +125 °C SC-88 plastic surface mounted package; 6 leads SOT363 74AUP1G57GM −40 °C to +125 °C XSON6 plastic extremely thin small outline package; no leads; SOT886 6 terminals; body 1 × 1.45 × 0.5 mm 74AUP1G57GF −40 °C to +125 °C XSON6 plastic extremely thin small outline package; no leads; SOT891 6 terminals; body 1 × 1 × 0.5 mm 74AUP1G57_1 Preliminary data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01.00 — 16 January 2006 2 of 22 74AUP1G57 Philips Semiconductors Low power configurable multiple function gate 5. Marking Table 3: Marking Type number Marking code 74AUP1G57GW aC 74AUP1G57GM aC 74AUP1G57GF aC 6. Functional diagram A 3 4 B C Y 1 6 001aab583 Fig 1. Logic symbol 7. Pinning information 7.1 Pinning 74AUP1G57 74AUP1G57 B 1 6 C GND 2 5 VCC A 3 4 Y B 1 6 C GND 2 5 VCC A 3 4 Y 001aab592 Transparent top view 001aab591 Fig 2. Pin configuration SOT363 (SC-88) Fig 3. Pin configuration SOT886 (XSON6) 74AUP1G57 B 1 6 C GND 2 5 VCC A 3 4 Y 001aae058 Transparent top view Fig 4. Pin configuration SOT891 (XSON6) 74AUP1G57_1 Preliminary data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01.00 — 16 January 2006 3 of 22 74AUP1G57 Philips Semiconductors Low power configurable multiple function gate 7.2 Pin description Table 4: Pin description Symbol Pin Description B 1 data input B GND 2 ground (0 V) A 3 data input A Y 4 data output Y VCC 5 supply voltage C 6 data input C 8. Functional description 8.1 Function table Table 5: Function table [1] Input Output C B A Y L L L H L L H L L H L H L H H L H L L L H L H L H H L H H H H H [1] H = HIGH voltage level; L = LOW voltage level. 8.2 Logic configurations Table 6: Function selection table Logic function Figure 2-input AND see Figure 5 2-input AND with both inputs inverted see Figure 8 2-input NAND with inverted input see Figure 6 and 7 2-input OR with inverted input see Figure 6 and 7 2-input NOR see Figure 8 2-input NOR with both inputs inverted see Figure 5 2-input XNOR see Figure 9 Inverter see Figure 10 Buffer see Figure 11 74AUP1G57_1 Preliminary data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01.00 — 16 January 2006 4 of 22 74AUP1G57 Philips Semiconductors Low power configurable multiple function gate VCC B C B C Y B Y 1 6 2 5 3 4 VCC B C C Y Y B C B Y 1 6 2 5 3 4 C Y 001aab585 001aab584 Fig 5. 2-input AND gate or 2-input NOR gate with both inputs inverted Fig 6. 2-input NAND gate with input B inverted or 2-input OR gate with inverted C input VCC VCC A C A C Y A Y 1 6 2 5 3 4 A C C Y Y A C Y A 1 6 2 5 3 4 001aab586 C Y 001aab587 Fig 7. 2-input NAND gate with input C inverted or 2-input OR gate with inverted A input Fig 8. 2-input NOR gate or 2-input AND gate with both inputs inverted VCC VCC B B C Y 1 6 2 5 3 4 C A Y Y A 1 6 2 5 3 4 Y 001aab588 001aab589 Fig 9. 2-input XNOR gate Fig 10. Inverter VCC B B Y 1 6 2 5 3 4 Y 001aab590 Fig 11. Buffer 74AUP1G57_1 Preliminary data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01.00 — 16 January 2006 5 of 22 74AUP1G57 Philips Semiconductors Low power configurable multiple function gate 9. Limiting values Table 7: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current VO < 0 V VO output voltage active mode and Power-down mode VO = 0 V to VCC VI < 0 V [1] [1] Min Max Unit −0.5 +4.6 V - −50 mA −0.5 +4.6 V - −50 mA −0.5 +4.6 V IO output current - ±20 mA ICC quiescent supply current - +50 mA IGND ground current - −50 mA Tstg storage temperature −65 +150 °C Ptot total power dissipation - 250 mW Tamb = −40 °C to +125 °C [2] [1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SC-88 packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K. For XSON6 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K. 10. Recommended operating conditions Table 8: Recommended operating conditions Min Max Unit VCC Symbol Parameter supply voltage Conditions 0.8 3.6 V VI input voltage 0 3.6 V VO output voltage active mode 0 VCC V Power-down mode; VCC = 0 V 0 3.6 V Tamb ambient temperature −40 +125 °C 74AUP1G57_1 Preliminary data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01.00 — 16 January 2006 6 of 22 74AUP1G57 Philips Semiconductors Low power configurable multiple function gate 11. Static characteristics Table 9: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit IO = −20 µA; VCC = 0.8 V to 3.6 V VCC − 0.1 - - V IO = −1.1 mA; VCC = 1.1 V 0.75 × VCC - - V IO = −1.7 mA; VCC = 1.4 V 1.11 - V Tamb = 25 °C VOH VOL HIGH-state output voltage LOW-state output voltage VI = VIH or VIL - IO = −1.9 mA; VCC = 1.65 V 1.32 - - V IO = −2.3 mA; VCC = 2.3 V 2.05 - - V IO = −3.1 mA; VCC = 2.3 V 1.9 - - V IO = −2.7 mA; VCC = 3.0 V 2.72 - - V IO = −4.0 mA; VCC = 3.0 V 2.6 - - V IO = 20 µA; VCC = 0.8 V to 3.6 V - - 0.1 V IO = 1.1 mA; VCC = 1.1 V - - 0.3 × VCC V VI = VIH or VIL IO = 1.7 mA; VCC = 1.4 V - - 0.31 V IO = 1.9 mA; VCC = 1.65 V - - 0.31 V IO = 2.3 mA; VCC = 2.3 V - - 0.31 V IO = 3.1 mA; VCC = 2.3 V - - 0.44 V IO = 2.7 mA; VCC = 3.0 V - - 0.31 V IO = 4.0 mA; VCC = 3.0 V - - 0.44 V II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - ±0.1 µA IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - ±0.2 µA ∆IOFF additional power-off leakage VI or VO = 0 V to 3.6 V; current VCC = 0 V to 0.2 V - - ±0.2 µA ICC quiescent supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 0.5 µA ∆ICC additional quiescent supply current VI = VCC − 0.6 V; IO = 0 A; VCC = 3.3 V - - 40 µA CI input capacitance VI = GND or VCC; VCC = 0 V to 3.6 V - 1.1 - pF CO output capacitance VO = GND; VCC = 0 V - 1.7 - pF IO = −20 µA; VCC = 0.8 V to 3.6 V VCC − 0.1 - - V IO = −1.1 mA; VCC = 1.1 V 0.7 × VCC - - V IO = −1.7 mA; VCC = 1.4 V 1.03 - - V IO = −1.9 mA; VCC = 1.65 V 1.30 - - V IO = −2.3 mA; VCC = 2.3 V 1.97 - - V IO = −3.1 mA; VCC = 2.3 V 1.85 - - V IO = −2.7 mA; VCC = 3.0 V 2.67 - - V IO = −4.0 mA; VCC = 3.0 V 2.55 - - V Tamb = −40 °C to +85 °C VOH HIGH-state output voltage VI = VIH or VIL 74AUP1G57_1 Preliminary data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01.00 — 16 January 2006 7 of 22 74AUP1G57 Philips Semiconductors Low power configurable multiple function gate Table 9: Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VOL VI = VIH or VIL LOW-state output voltage Min Typ Max Unit IO = 20 µA; VCC = 0.8 V to 3.6 V - - 0.1 V IO = 1.1 mA; VCC = 1.1 V - - 0.3 × VCC V IO = 1.7 mA; VCC = 1.4 V - - 0.37 V IO = 1.9 mA; VCC = 1.65 V - - 0.35 V IO = 2.3 mA; VCC = 2.3 V - - 0.33 V IO = 3.1 mA; VCC = 2.3 V - - 0.45 V IO = 2.7 mA; VCC = 3.0 V - - 0.33 V IO = 4.0 mA; VCC = 3.0 V - - 0.45 V ±0.5 µA II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - VI or VO = 0 V to 3.6 V; VCC = 0 V IOFF power-off leakage current - - ±0.5 µA ∆IOFF additional power-off leakage VI or VO = 0 V to 3.6 V; current VCC = 0 V to 0.2 V - - ±0.6 µA ICC quiescent supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 0.9 µA ∆ICC additional quiescent supply current VI = VCC − 0.6 V; IO = 0 A; VCC = 3.3 V - - 50 µA Tamb = −40 °C to +125 °C VOH VOL HIGH-state output voltage LOW-state output voltage VI = VIH or VIL IO = −20 µA; VCC = 0.8 V to 3.6 V VCC − 0.11 - - V IO = −1.1 mA; VCC = 1.1 V 0.6 × VCC - - V IO = −1.7 mA; VCC = 1.4 V 0.93 - - V IO = −1.9 mA; VCC = 1.65 V 1.17 - - V IO = −2.3 mA; VCC = 2.3 V 1.77 - - V IO = −3.1 mA; VCC = 2.3 V 1.67 - - V IO = −2.7 mA; VCC = 3.0 V 2.40 - - V IO = −4.0 mA; VCC = 3.0 V 2.30 - - V IO = 20 µA; VCC = 0.8 V to 3.6 V - - 0.11 V IO = 1.1 mA; VCC = 1.1 V - - 0.33 × VCC V VI = VIH or VIL IO = 1.7 mA; VCC = 1.4 V - - 0.41 V IO = 1.9 mA; VCC = 1.65 V - - 0.39 V IO = 2.3 mA; VCC = 2.3 V - - 0.36 V IO = 3.1 mA; VCC = 2.3 V - - 0.50 V IO = 2.7 mA; VCC = 3.0 V - - 0.36 V IO = 4.0 mA; VCC = 3.0 V - - 0.50 V II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - ±0.75 µA IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - ±0.75 µA 74AUP1G57_1 Preliminary data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01.00 — 16 January 2006 8 of 22 74AUP1G57 Philips Semiconductors Low power configurable multiple function gate Table 9: Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit ∆IOFF additional power-off leakage VI or VO = 0 V to 3.6 V; current VCC = 0 V to 0.2 V - - ±0.75 µA ICC quiescent supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 1.4 µA ∆ICC additional quiescent supply current VI = VCC − 0.6 V; IO = 0 A; VCC = 3.3 V - - 75 µA 12. Dynamic characteristics Table 10: Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13 Symbol Parameter Conditions Min Typ VCC = 0.8 V - VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V [1] Max Unit 22.6 - ns 2.8 6.5 12.6 ns 2.2 4.6 7.6 ns VCC = 1.65 V to 1.95 V 2.1 3.9 6.2 ns VCC = 2.3 V to 2.7 V 2.0 3.1 4.5 ns VCC = 3.0 V to 3.6 V 1.8 2.8 3.9 ns VCC = 0.8 V - 26.1 - ns VCC = 1.1 V to 1.3 V 3.2 7.3 14.4 ns VCC = 1.4 V to 1.6 V 2.6 5.2 8.7 ns VCC = 1.65 V to 1.95 V 2.5 4.5 7.0 ns VCC = 2.3 V to 2.7 V 2.4 3.7 5.2 ns VCC = 3.0 V to 3.6 V 2.3 3.4 4.6 ns VCC = 0.8 V - 31.6 - ns VCC = 1.1 V to 1.3 V 3.4 8.0 15.7 ns VCC = 1.4 V to 1.6 V 2.8 5.7 9.4 ns VCC = 1.65 V to 1.95 V 2.6 4.9 7.7 ns VCC = 2.3 V to 2.7 V 2.6 4.1 5.7 ns VCC = 3.0 V to 3.6 V 2.5 3.8 5.0 ns Tamb = 25 °C; CL = 5 pF tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay A, B and C to Y see Figure 12 Tamb = 25 °C; CL = 10 pF tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay A, B and C to Y see Figure 12 Tamb = 25 °C; CL = 15 pF tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay A, B and C to Y see Figure 12 74AUP1G57_1 Preliminary data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01.00 — 16 January 2006 9 of 22 74AUP1G57 Philips Semiconductors Low power configurable multiple function gate Table 10: Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13 Symbol Parameter Conditions Min Typ [1] Max Unit Tamb = 25 °C; CL = 30 pF tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay A, B and C to Y see Figure 12 VCC = 0.8 V - 37.8 - ns VCC = 1.1 V to 1.3 V 4.6 10.4 20.9 ns VCC = 1.4 V to 1.6 V 3.6 7.4 12.2 ns VCC = 1.65 V to 1.95 V 3.5 6.2 9.9 ns VCC = 2.3 V to 2.7 V 3.4 5.2 7.4 ns VCC = 3.0 V to 3.6 V 3.2 4.9 6.6 ns VCC = 0.8 V - 2.9 - pF VCC = 1.1 V to 1.3 V - 3.0 - pF VCC = 1.4 V to 1.6 V - 3.2 - pF VCC = 1.65 V to 1.95 V - 3.4 - pF VCC = 2.3 V to 2.7 V - 3.9 - pF VCC = 3.0 V to 3.6 V - 4.5 - pF Tamb = 25 °C power dissipation capacitance f = 1 MHz CPD [1] All typical values are measured at nominal VCC. [2] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. [3] The condition is VI = GND to VCC. [2] [3] 74AUP1G57_1 Preliminary data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01.00 — 16 January 2006 10 of 22 74AUP1G57 Philips Semiconductors Low power configurable multiple function gate Table 11: Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13 Symbol Parameter −40 °C to +85 °C Conditions Min −40 °C to +125 °C Max Min Unit Max CL = 5 pF tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay A, B and C to Y see Figure 12 VCC = 1.1 V to 1.3 V 2.5 13.0 2.5 13.2 ns VCC = 1.4 V to 1.6 V 2.5 8.2 2.5 8.6 ns VCC = 1.65 V to 1.95 V 2.0 6.8 2.0 7.2 ns VCC = 2.3 V to 2.7 V 1.8 5.1 1.8 5.3 ns VCC = 3.0 V to 3.6 V 1.5 4.1 1.5 4.3 ns VCC = 1.1 V to 1.3 V 2.8 14.9 2.8 15.2 ns VCC = 1.4 V to 1.6 V 2.8 9.3 2.8 9.8 ns CL = 10 pF tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay A, B and C to Y see Figure 12 VCC = 1.65 V to 1.95 V 2.2 7.8 2.2 8.2 ns VCC = 2.3 V to 2.7 V 2.1 5.9 2.1 6.2 ns VCC = 3.0 V to 3.6 V 1.9 4.9 1.9 5.1 ns VCC = 1.1 V to 1.3 V 3.1 16.7 3.1 17.0 ns VCC = 1.4 V to 1.6 V 3.1 10.4 3.1 10.9 ns VCC = 1.65 V to 1.95 V 2.5 8.7 2.5 9.2 ns VCC = 2.3 V to 2.7 V 2.4 6.5 2.4 6.9 ns VCC = 3.0 V to 3.6 V 2.2 5.5 2.2 5.7 ns CL = 15 pF tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay A, B and C to Y see Figure 12 CL = 30 pF tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay A, B and C to Y see Figure 12 VCC = 1.1 V to 1.3 V 3.9 21.8 3.9 22.3 ns VCC = 1.4 V to 1.6 V 3.8 13.4 3.8 14.1 ns VCC = 1.65 V to 1.95 V 3.1 11.1 3.1 11.8 ns VCC = 2.3 V to 2.7 V 3.1 8.3 3.1 8.8 ns VCC = 3.0 V to 3.6 V 2.8 7.0 2.8 7.4 ns 74AUP1G57_1 Preliminary data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01.00 — 16 January 2006 11 of 22 74AUP1G57 Philips Semiconductors Low power configurable multiple function gate 13. Waveforms VI A, B, C input VM VM GND t PHL t PLH VOH VM Y output VM VOL t PLH t PHL VOH Y output VM VM VOL 001aab593 Measurement points are given in Table 12. VOL and VOH are typical output voltage drop that occur with the output load. Fig 12. Input A, B and C to output Y propagation delay times Table 12: Measurement points Supply voltage Output Input VCC VM VM VI tr = tf 0.8 V to 3.6 V 0.5 × VCC 0.5 × VCC VCC ≤ 3.0 ns 74AUP1G57_1 Preliminary data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01.00 — 16 January 2006 12 of 22 74AUP1G57 Philips Semiconductors Low power configurable multiple function gate VCC VEXT 5 kΩ PULSE GENERATOR VI VO DUT RT CL RL 001aac521 Test data is given in Table 13. Definitions for test circuit: RL = Load resistance CL = Load capacitance including jig and probe capacitance RT = Termination resistance should be equal to the output impedance Zo of the pulse generator VEXT = External voltage for measuring switching times. Fig 13. Load circuitry for switching times Table 13: Test data Supply voltage Load VEXT VCC CL 0.8 V to 3.6 V 5 pF, 10 pF, 5 kΩ or 1 MΩ open 15 pF and 30 pF [1] RL [1] tPLH, tPHL tPZH, tPHZ tPZL, tPLZ GND 2 × VCC For measuring enable and disable times RL = 5 kΩ, for measuring propagation delays, setup and hold times and pulse width RL = 1 MΩ. 14. Transfer characteristics Table 14: Transfer characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit VCC = 0.8 V 0.30 - 0.60 V VCC = 1.1 V 0.53 - 0.90 V VCC = 1.4 V 0.74 - 1.11 V VCC = 1.65 V 0.91 - 1.29 V VCC = 2.3 V 1.37 - 1.77 V VCC = 3.0 V 1.88 - 2.29 V Tamb = 25 °C VT+ positive-going threshold voltage see Figure 14 and Figure 15 74AUP1G57_1 Preliminary data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01.00 — 16 January 2006 13 of 22 74AUP1G57 Philips Semiconductors Low power configurable multiple function gate Table 14: Transfer characteristics …continued Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VT− see Figure 14 and Figure 15 VH negative-going threshold voltage Min Typ Max Unit VCC = 0.8 V 0.10 - 0.60 V VCC = 1.1 V 0.26 - 0.65 V VCC = 1.4 V 0.39 - 0.75 V VCC = 1.65 V 0.47 - 0.84 V VCC = 2.3 V 0.69 - 1.04 V VCC = 3.0 V 0.88 - 1.24 V VCC = 0.8 V 0.07 - 0.50 V VCC = 1.1 V 0.08 - 0.46 V VCC = 1.4 V 0.18 - 0.56 V VCC = 1.65 V 0.27 - 0.66 V VCC = 2.3 V 0.53 - 0.92 V VCC = 3.0 V 0.79 - 1.31 V VCC = 0.8 V 0.30 - 0.60 V VCC = 1.1 V 0.53 - 0.90 V VCC = 1.4 V 0.74 - 1.11 V VCC = 1.65 V 0.91 - 1.29 V VCC = 2.3 V 1.37 - 1.77 V VCC = 3.0 V 1.88 - 2.29 V VCC = 0.8 V 0.10 - 0.60 V VCC = 1.1 V 0.26 - 0.65 V VCC = 1.4 V 0.39 - 0.75 V VCC = 1.65 V 0.47 - 0.84 V VCC = 2.3 V 0.69 - 1.04 V VCC = 3.0 V 0.88 - 1.24 V VCC = 0.8 V 0.07 - 0.50 V VCC = 1.1 V 0.08 - 0.46 V VCC = 1.4 V 0.18 - 0.56 V VCC = 1.65 V 0.27 - 0.66 V VCC = 2.3 V 0.53 - 0.92 V VCC = 3.0 V 0.79 - 1.31 V hysteresis voltage see Figure 14, Figure 15, (VT+ − VT−) Figure 16 and Figure 17 Tamb = −40 °C to +85 °C VT+ VT− VH positive-going threshold voltage negative-going threshold voltage see Figure 14 and Figure 15 see Figure 14 and Figure 15 hysteresis voltage see Figure 14, Figure 15, (VT+ − VT−) Figure 16 and Figure 17 74AUP1G57_1 Preliminary data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01.00 — 16 January 2006 14 of 22 74AUP1G57 Philips Semiconductors Low power configurable multiple function gate Table 14: Transfer characteristics …continued Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit VCC = 0.8 V 0.30 - 0.62 V VCC = 1.1 V 0.53 - 0.92 V VCC = 1.4 V 0.74 - 1.13 V VCC = 1.65 V 0.91 - 1.31 V VCC = 2.3 V 1.37 - 1.80 V VCC = 3.0 V 1.88 - 2.32 V VCC = 0.8 V 0.10 - 0.60 V VCC = 1.1 V 0.26 - 0.65 V VCC = 1.4 V 0.39 - 0.75 V VCC = 1.65 V 0.47 - 0.84 V VCC = 2.3 V 0.69 - 1.04 V VCC = 3.0 V 0.88 - 1.24 V VCC = 0.8 V 0.07 - 0.50 V VCC = 1.1 V 0.08 - 0.46 V VCC = 1.4 V 0.18 - 0.56 V VCC = 1.65 V 0.27 - 0.66 V VCC = 2.3 V 0.53 - 0.92 V VCC = 3.0 V 0.79 - 1.31 V Tamb = −40 °C to +125 °C VT+ VT− VH positive-going threshold voltage negative-going threshold voltage see Figure 14 and Figure 15 see Figure 14 and Figure 15 hysteresis voltage see Figure 14, Figure 15, (VT+ − VT−) Figure 16 and Figure 17 15. Waveforms transfer characteristics VT+ VO VI VH VT− VO VI VH VT− VT+ mna208 mna207 VT+ and VT− limits at 70 % and 20 %. Fig 14. Transfer characteristic Fig 15. Definition of VT+, VT− and VH 74AUP1G57_1 Preliminary data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01.00 — 16 January 2006 15 of 22 74AUP1G57 Philips Semiconductors Low power configurable multiple function gate 001aad691 240 ICC (µA) 160 80 0 0 0.4 0.8 1.2 1.6 2.0 VI (V) Fig 16. Typical transfer characteristics; VCC = 1.8 V 001aad692 1200 ICC (µA) 800 400 0 0 1.0 2.0 3.0 VI (V) Fig 17. Typical transfer characteristics; VCC = 3.0 V 74AUP1G57_1 Preliminary data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01.00 — 16 January 2006 16 of 22 74AUP1G57 Philips Semiconductors Low power configurable multiple function gate 16. Package outline Plastic surface mounted package; 6 leads SOT363 D E B y X A HE 6 5 v M A 4 Q pin 1 index A A1 1 2 e1 3 bp c Lp w M B e detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp c D E e e1 HE Lp Q v w y mm 1.1 0.8 0.1 0.30 0.20 0.25 0.10 2.2 1.8 1.35 1.15 1.3 0.65 2.2 2.0 0.45 0.15 0.25 0.15 0.2 0.2 0.1 OUTLINE VERSION REFERENCES IEC SOT363 JEDEC JEITA SC-88 EUROPEAN PROJECTION ISSUE DATE 97-02-28 04-11-08 Fig 18. Package outline SOT363 (SC-88) 74AUP1G57_1 Preliminary data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01.00 — 16 January 2006 17 of 22 74AUP1G57 Philips Semiconductors Low power configurable multiple function gate XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm SOT886 b 1 2 3 4× (2) L L1 e 6 5 e1 4 e1 6× A (2) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A (1) max A1 max b D E e e1 L L1 mm 0.5 0.04 0.25 0.17 1.5 1.4 1.05 0.95 0.6 0.5 0.35 0.27 0.40 0.32 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT886 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 04-07-15 04-07-22 MO-252 Fig 19. Package outline SOT886 (XSON6) 74AUP1G57_1 Preliminary data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01.00 — 16 January 2006 18 of 22 74AUP1G57 Philips Semiconductors Low power configurable multiple function gate XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm 1 SOT891 b 3 2 L L1 e 6 5 e1 4 e1 A A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 max b D E e e1 L L1 mm 0.5 0.04 0.20 0.12 1.05 0.95 1.05 0.95 0.55 0.35 0.35 0.27 0.40 0.32 OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 05-03-11 05-04-06 SOT891 Fig 20. Package outline SOT891 (XSON6) 74AUP1G57_1 Preliminary data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01.00 — 16 January 2006 19 of 22 74AUP1G57 Philips Semiconductors Low power configurable multiple function gate 17. Abbreviations Table 15: Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor Transistor Logic 18. Revision history Table 16: Revision history Document ID Release date Data sheet status Change notice Doc. number Supersedes 74AUP1G57_1 <tbd> Preliminary data sheet - - - 74AUP1G57_1 Preliminary data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01.00 — 16 January 2006 20 of 22 74AUP1G57 Philips Semiconductors Low power configurable multiple function gate 19. Data sheet status Level Data sheet status [1] Product status [2] [3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 20. Definitions customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 22. Trademarks 21. Disclaimers Notice — All referenced brands, product names, service names and trademarks are the property of their respective owners. Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors 23. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: [email protected] 74AUP1G57_1 Preliminary data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01.00 — 16 January 2006 21 of 22 74AUP1G57 Philips Semiconductors Low power configurable multiple function gate 24. Contents 1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Logic configurations . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Transfer characteristics. . . . . . . . . . . . . . . . . . 13 Waveforms transfer characteristics . . . . . . . . 15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 20 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 21 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Contact information . . . . . . . . . . . . . . . . . . . . 21 © Koninklijke Philips Electronics N.V. 2006 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 16 January 2006 Document number: 74AUP1G57_1 Published in The Netherlands