PHILIPS PHU101NQ03LT

PHP/PHU101NQ03LT
TrenchMOS™ logic level FET
Rev. 02 — 25 February 2003
Product data
1. Description
N-channel logic level field-effect power transistor in a plastic package using
TrenchMOS™ technology.
Product availability:
PHP101NQ03LT in SOT78 (TO-220AB)
PHU101NQ03LT in SOT533 (I-PAK).
2. Features
■ Low gate charge
■ Low on-state resistance.
3. Applications
■ Optimized as a control FET in DC to DC converters.
4. Pinning information
Table 1:
Pinning - SOT78, SOT533 simplified outline and symbol
Pin Description
1
gate (g)
2
drain (d)
3
source (s)
mb
mounting base,
connected to drain (d)
Simplified outline
Symbol
d
mb
g
MBB076
MBK106
1
2
3
1 2 3
Top view
SOT78 (TO-220AB)
MBK915
SOT533 (I-PAK)
s
PHP/PHU101NQ03LT
Philips Semiconductors
TrenchMOS™ logic level FET
5. Quick reference data
Table 2:
Quick reference data
Symbol Parameter
Conditions
Typ
Max
Unit
VDS
drain-source voltage (DC)
25 °C ≤ Tj ≤ 175 °C
-
30
V
ID
drain current (DC)
Tmb = 25 °C; VGS = 5 V
-
75
A
Ptot
total power dissipation
Tmb = 25 °C
-
166
W
Tj
junction temperature
-
175
°C
RDSon
drain-source on-state resistance
Tj = 25 °C; VGS = 10 V; ID = 25 A
4.5
5.5
mΩ
Tj = 25 °C; VGS = 5 V; ID = 25 A
5.8
7.0
mΩ
Min
Max
Unit
6. Limiting values
Table 3: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
VDS
drain-source voltage (DC)
25 °C ≤ Tj ≤ 175 °C
-
30
V
VDGR
drain-gate voltage (DC)
25 °C ≤ Tj ≤ 175 °C; RGS = 20 kΩ
-
30
V
VGS
gate-source voltage (DC)
-
±20
V
VGSM
gate-source voltage
tp ≤ 50 µs; pulsed;
duty cycle 25%; Tj ≤ 150 °C
-
±25
V
ID
drain current (DC)
Tmb = 25 °C; VGS = 5 V; Figure 2 and 3
-
75
A
Tmb = 100 °C; VGS = 5 V; Figure 2
-
75
A
IDM
peak drain current
Tmb = 25 °C; pulsed; tp ≤ 10 µs; Figure 3
-
240
A
Tmb = 25 °C; Figure 1
Ptot
total power dissipation
-
166
W
Tstg
storage temperature
−55
+175
°C
Tj
junction temperature
−55
+175
°C
Source-drain diode
IS
source (diode forward) current (DC) Tmb = 25 °C
-
75
A
ISM
peak source (diode forward) current Tmb = 25 °C; pulsed; tp ≤ 10 µs
-
240
A
-
185
mJ
Avalanche ruggedness
EDS(AL)S non-repetitive drain-source
avalanche energy
unclamped inductive load; ID = 43 A;
tp = 0.19 ms; VDD ≤ 15 V; RGS = 50 Ω;
VGS = 10 V; starting Tj = 25 °C
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9397 750 10927
Product data
Rev. 02 — 25 February 2003
2 of 13
PHP/PHU101NQ03LT
Philips Semiconductors
TrenchMOS™ logic level FET
03aa16
120
03ai19
120
Pder
(%)
Ider
(%)
80
80
40
40
0
0
0
50
100
150
200
Tmb (°C)
0
P tot
P der = ---------------------- × 100%
P
°
50
100
150
200
Tmb (°C)
ID
I der = ------------------- × 100%
I
°
tot ( 25 C )
D ( 25 C )
Fig 1. Normalized total power dissipation as a
function of mounting base temperature.
Fig 2. Normalized continuous drain current as a
function of mounting base temperature.
03ai21
103
ID
(A)
Limit RDSon = VDS / ID
tp = 10 µ s
100 µ s
102
DC
1 ms
10
10 ms
1
1
10
VDS (V)
102
Tmb = 25 °C; IDM is single pulse; VGS = 10V.
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9397 750 10927
Product data
Rev. 02 — 25 February 2003
3 of 13
PHP/PHU101NQ03LT
Philips Semiconductors
TrenchMOS™ logic level FET
7. Thermal characteristics
Table 4:
Thermal characteristics
Symbol Parameter
Conditions
Rth(j-mb)
thermal resistance from junction to mounting base Figure 4
Rth(j-a)
thermal resistance from junction to ambient
Min Typ Max Unit
-
-
0.9
K/W
SOT78
vertical in still air
-
60
-
K/W
SOT533
vertical in still air
-
70
-
K/W
7.1 Transient thermal impedance
03ai20
10
Zth(j-mb)
(K/W)
1
δ = 0.5
0.2
10-1
0.1
0.05
0.02
δ=
P
10-2
tp
T
single pulse
t
tp
T
10-3
10-5
10-4
10-3
10-2
10-1
tp (s)
1
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration.
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9397 750 10927
Product data
Rev. 02 — 25 February 2003
4 of 13
PHP/PHU101NQ03LT
Philips Semiconductors
TrenchMOS™ logic level FET
8. Characteristics
Table 5: Characteristics
Tj = 25 °C unless otherwise specified
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tj = 25 °C
30
-
-
V
Tj = −55 °C
27
-
-
V
Tj = 25 °C
1
1.9
2.5
V
Tj = 175 °C
0.6
-
-
V
Tj = −55 °C
-
-
2.9
V
-
0.05
1
µA
Static characteristics
V(BR)DSS drain-source breakdown voltage
VGS(th)
IDSS
gate-source threshold voltage
drain-source leakage current
ID = 0.25 mA; VGS = 0 V
ID = 1 mA; VDS = VGS; Figure 9
VDS = 30 V; VGS = 0 V
Tj = 25 °C
Tj = 175 °C
-
-
500
µA
-
10
100
nA
Tj = 25 °C
-
5.8
7
mΩ
Tj = 175 °C
-
10.5
12.6
mΩ
-
4.5
5.5
mΩ
IGSS
gate-source leakage current
VGS = ±20 V; VDS = 0 V
RDSon
drain-source on-state resistance
VGS = 5 V; ID = 25 A; Figure 7 and 8
VGS = 10 V; ID = 25 A; Figure 7
Tj = 25 °C
Dynamic characteristics
Qg(tot)
total gate charge
-
23
-
nC
Qgs
gate-source charge
ID = 50 A; VDD = 15 V; VGS = 5 V; Figure 13
-
10.5
-
nC
Qgd
gate-drain (Miller) charge
-
8
-
nC
Ciss
input capacitance
-
2180 -
pF
VGS = 0 V; VDS = 25 V; f = 1 MHz; Figure 11
Coss
output capacitance
-
600
-
pF
Crss
reverse transfer capacitance
-
225
-
pF
td(on)
turn-on delay time
-
23
-
ns
tr
rise time
-
90
-
ns
td(off)
turn-off delay time
-
37
-
ns
tf
fall time
-
33
-
ns
-
0.85
1.2
V
-
37
-
ns
-
33
-
nC
VDD = 15 V; ID = 25 A;
VGS = 4.5 V; RG = 5.6 Ω
Source-drain diode
VSD
source-drain (diode forward) voltage IS = 25 A; VGS = 0 V; Figure 12
trr
reverse recovery time
Qr
recovered charge
IS = 10 A; dIS/dt = −100 A/µs; VGS = 0 V
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9397 750 10927
Product data
Rev. 02 — 25 February 2003
5 of 13
PHP/PHU101NQ03LT
Philips Semiconductors
TrenchMOS™ logic level FET
03ai22
80
10 V 5 V 4.5 V
Tj = 25 °C
ID
(A)
03ai24
80
4V
3.8 V
VDS > ID x RDSon
ID
(A)
60
60
3.6 V
40
40
3.4 V
3.2 V
20
20
175 °C
3V
Tj = 25 °C
VGS = 2.8 V
0
0
0
0.2
0.4
0.6
0.8
1
VDS (V)
Tj = 25 °C
0
2
3 V
4
GS (V)
Tj = 25 °C and 175 °C; VDS > ID x RDSon
Fig 5. Output characteristics: drain current as a
function of drain-source voltage; typical values.
Fig 6. Transfer characteristics: drain current as a
function of gate-source voltage; typical values.
03ai23
16
Tj = 25 °C
RDSon
(mΩ)
1
VGS = 3.8 V
03af18
2
a
12
1.5
4V
8
4.5 V
5V
1
10 V
4
0.5
0
0
0
20
40
60
ID (A) 80
Tj = 25 °C
-60
60
120
Tj (°C)
180
R DSon
a = --------------------------R DSon ( 25 °C )
Fig 7. Drain-source on-state resistance as a function
of drain current; typical values.
Fig 8. Normalized drain-source on-state resistance
factor as a function of junction temperature.
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9397 750 10927
Product data
0
Rev. 02 — 25 February 2003
6 of 13
PHP/PHU101NQ03LT
Philips Semiconductors
TrenchMOS™ logic level FET
03ai29
3.2
03ai28
10-1
ID
(A)
10-2
VGS(th)
(V)
max
2.4
10-3
typ
min
typ
max
1.6
10-4
min
0.8
10-5
10-6
0
-60
0
60
120
Tj (°C)
180
0
0.8
1.6
2.4
VGS(V)
3.2
Tj = 25 °C; VDS = 5 V
ID = 1 mA; VDS = VGS
Fig 9. Gate-source threshold voltage as a function of
junction temperature.
Fig 10. Sub-threshold drain current as a function of
gate-source voltage.
03ai26
104
C
(pF)
Ciss
103
Coss
Crss
102
10-1
1
10
2
VDS (V) 10
VGS = 0 V; f = 1 MHz
Fig 11. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values.
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9397 750 10927
Product data
Rev. 02 — 25 February 2003
7 of 13
PHP/PHU101NQ03LT
Philips Semiconductors
TrenchMOS™ logic level FET
03ai25
80
ID = 50 A
VGS
(V)
8
VGS = 0 V
IS
(A)
03ai27
10
Tj = 25 °C
VDD = 15 V
60
6
40
4
20
175 °C
2
Tj = 25 °C
0
0
0
0.3
0.6
0.9 V
1.2
SD (V)
Tj = 25 °C and 175 °C; VGS = 0 V
0
20
30
40
50
QG (nC)
ID = 50 A; VDD = 15 V
Fig 12. Source (diode forward) current as a function of
source-drain (diode forward) voltage; typical
values.
Fig 13. Gate-source voltage as a function of gate
charge; typical values.
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9397 750 10927
Product data
10
Rev. 02 — 25 February 2003
8 of 13
PHP/PHU101NQ03LT
Philips Semiconductors
TrenchMOS™ logic level FET
9. Package outline
Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220AB
E
SOT78
A
A1
p
q
mounting
base
D1
D
L2
L1(1)
Q
b1
L
1
2
3
b
c
e
e
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
b
b1
c
D
D1
E
e
L
L1(1)
L2
max.
p
q
Q
mm
4.5
4.1
1.39
1.27
0.9
0.7
1.3
1.0
0.7
0.4
15.8
15.2
6.4
5.9
10.3
9.7
2.54
15.0
13.5
3.30
2.79
3.0
3.8
3.6
3.0
2.7
2.6
2.2
Note
1. Terminals in this zone are not tinned.
OUTLINE
VERSION
REFERENCES
IEC
SOT78
JEDEC
EIAJ
3-lead TO-220AB
SC-46
EUROPEAN
PROJECTION
ISSUE DATE
00-09-07
01-02-16
Fig 14. SOT78 (TO-220AB).
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9397 750 10927
Product data
Rev. 02 — 25 February 2003
9 of 13
PHP/PHU101NQ03LT
Philips Semiconductors
TrenchMOS™ logic level FET
Plastic single-ended package (Philips version of I-PAK); 3 leads (in-line)
SOT533
E
A
A1
E1
D1
mounting
base
D
Q
L
1
2
e1
3
b
c
w M
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
mm
2.38
2.22
0.89
0.71
b
c
0.89 0.56
0.71 0.46
OUTLINE
VERSION
SOT533
D
D1
E
E1
7.28
6.94
1.06
0.96
6.73
6.47
5.36
5.26
e
L
Q
9.8
9.4
1.00
1.10
e1
4.57 2.285
REFERENCES
IEC
JEDEC
EIAJ
TO-251
EUROPEAN
PROJECTION
ISSUE DATE
99-02-18
Fig 15. SOT533 (I-PAK).
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9397 750 10927
Product data
Rev. 02 — 25 February 2003
10 of 13
PHP/PHU101NQ03LT
Philips Semiconductors
TrenchMOS™ logic level FET
10. Revision history
Table 6:
Revision history
Rev Date
02
20030225
CPCN
Description
-
Product data (9397 750 10927)
Modifications:
•
•
•
•
01
20020220
-
Removal of PHD101NQ03LT (Now in separate data sheet).
Removal of PHB101NQ03LT (Now in separate data sheet).
Section 7 “Thermal characteristics” Clarification of thermal resistance table.
Graphics updated to latest standard.
Product data (9397 750 09307); initial version
11. Trademarks
TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V.
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9397 750 10927
Product data
Rev. 02 — 25 February 2003
11 of 13
PHP/PHU101NQ03LT
Philips Semiconductors
TrenchMOS™ logic level FET
12. Data sheet status
Level
Data sheet status[1]
Product status[2][3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
[2]
[3]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
13. Definitions
14. Disclaimers
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Contact information
For additional information, please visit http://www.semiconductors.philips.com.
For sales office addresses, send e-mail to: [email protected]
Product data
Fax: +31 40 27 24825
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9397 750 10927
Rev. 02 — 25 February 2003
12 of 13
Philips Semiconductors
PHP/PHU101NQ03LT
TrenchMOS™ logic level FET
Contents
1
2
3
4
5
6
7
7.1
8
9
10
11
12
13
14
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pinning information . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
Thermal characteristics. . . . . . . . . . . . . . . . . . . 4
Transient thermal impedance . . . . . . . . . . . . . . 4
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 12
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
© Koninklijke Philips Electronics N.V. 2003.
Printed in The Netherlands
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 25 February 2003
Document order number: 9397 750 10927